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freedreno/a5xx: fix SSBO emit for non-zero offset
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd5_emit.h"
38 #include "fd5_blend.h"
39 #include "fd5_context.h"
40 #include "fd5_image.h"
41 #include "fd5_program.h"
42 #include "fd5_rasterizer.h"
43 #include "fd5_texture.h"
44 #include "fd5_format.h"
45 #include "fd5_zsa.h"
46
47 /* regid: base const register
48 * prsc or dwords: buffer containing constant values
49 * sizedwords: size of const value buffer
50 */
51 static void
52 fd5_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
53 uint32_t regid, uint32_t offset, uint32_t sizedwords,
54 const uint32_t *dwords, struct pipe_resource *prsc)
55 {
56 uint32_t i, sz;
57 enum a4xx_state_src src;
58
59 debug_assert((regid % 4) == 0);
60 debug_assert((sizedwords % 4) == 0);
61
62 if (prsc) {
63 sz = 0;
64 src = SS4_INDIRECT;
65 } else {
66 sz = sizedwords;
67 src = SS4_DIRECT;
68 }
69
70 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sz);
71 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
72 CP_LOAD_STATE4_0_STATE_SRC(src) |
73 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
74 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
75 if (prsc) {
76 struct fd_bo *bo = fd_resource(prsc)->bo;
77 OUT_RELOC(ring, bo, offset,
78 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
79 } else {
80 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
81 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
82 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
83 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
84 }
85 for (i = 0; i < sz; i++) {
86 OUT_RING(ring, dwords[i]);
87 }
88 }
89
90 static void
91 fd5_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
92 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
93 {
94 uint32_t anum = align(num, 2);
95 uint32_t i;
96
97 debug_assert((regid % 4) == 0);
98
99 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * anum));
100 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
101 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
102 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
103 CP_LOAD_STATE4_0_NUM_UNIT(anum/2));
104 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
105 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
106 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
107
108 for (i = 0; i < num; i++) {
109 if (prscs[i]) {
110 if (write) {
111 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
112 } else {
113 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
114 }
115 } else {
116 OUT_RING(ring, 0xbad00000 | (i << 16));
117 OUT_RING(ring, 0xbad00000 | (i << 16));
118 }
119 }
120
121 for (; i < anum; i++) {
122 OUT_RING(ring, 0xffffffff);
123 OUT_RING(ring, 0xffffffff);
124 }
125 }
126
127 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
128 * the same as a6xx then move this somewhere common ;-)
129 *
130 * Entry layout looks like (total size, 0x60 bytes):
131 */
132
133 struct PACKED bcolor_entry {
134 uint32_t fp32[4];
135 uint16_t ui16[4];
136 int16_t si16[4];
137 uint16_t fp16[4];
138 uint16_t rgb565;
139 uint16_t rgb5a1;
140 uint16_t rgba4;
141 uint8_t __pad0[2];
142 uint8_t ui8[4];
143 int8_t si8[4];
144 uint32_t rgb10a2;
145 uint32_t z24; /* also s8? */
146 uint8_t __pad1[32];
147 };
148
149 #define FD5_BORDER_COLOR_SIZE 0x60
150 #define FD5_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD5_BORDER_COLOR_SIZE)
151
152 static void
153 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
154 {
155 unsigned i, j;
156 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE);
157
158 for (i = 0; i < tex->num_samplers; i++) {
159 struct bcolor_entry *e = &entries[i];
160 struct pipe_sampler_state *sampler = tex->samplers[i];
161 union pipe_color_union *bc;
162
163 if (!sampler)
164 continue;
165
166 bc = &sampler->border_color;
167
168 /*
169 * XXX HACK ALERT XXX
170 *
171 * The border colors need to be swizzled in a particular
172 * format-dependent order. Even though samplers don't know about
173 * formats, we can assume that with a GL state tracker, there's a
174 * 1:1 correspondence between sampler and texture. Take advantage
175 * of that knowledge.
176 */
177 if ((i >= tex->num_textures) || !tex->textures[i])
178 continue;
179
180 const struct util_format_description *desc =
181 util_format_description(tex->textures[i]->format);
182
183 e->rgb565 = 0;
184 e->rgb5a1 = 0;
185 e->rgba4 = 0;
186 e->rgb10a2 = 0;
187 e->z24 = 0;
188
189 for (j = 0; j < 4; j++) {
190 int c = desc->swizzle[j];
191
192 if (c >= 4)
193 continue;
194
195 if (desc->channel[c].pure_integer) {
196 uint16_t clamped;
197 switch (desc->channel[c].size) {
198 case 2:
199 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
200 clamped = CLAMP(bc->ui[j], 0, 0x3);
201 break;
202 case 8:
203 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
204 clamped = CLAMP(bc->i[j], -128, 127);
205 else
206 clamped = CLAMP(bc->ui[j], 0, 255);
207 break;
208 case 10:
209 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
210 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
211 break;
212 case 16:
213 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
214 clamped = CLAMP(bc->i[j], -32768, 32767);
215 else
216 clamped = CLAMP(bc->ui[j], 0, 65535);
217 break;
218 default:
219 assert(!"Unexpected bit size");
220 case 32:
221 clamped = 0;
222 break;
223 }
224 e->fp32[c] = bc->ui[j];
225 e->fp16[c] = clamped;
226 } else {
227 float f = bc->f[j];
228 float f_u = CLAMP(f, 0, 1);
229 float f_s = CLAMP(f, -1, 1);
230
231 e->fp32[c] = fui(f);
232 e->fp16[c] = util_float_to_half(f);
233 e->ui16[c] = f_u * 0xffff;
234 e->si16[c] = f_s * 0x7fff;
235 e->ui8[c] = f_u * 0xff;
236 e->si8[c] = f_s * 0x7f;
237 if (c == 1)
238 e->rgb565 |= (int)(f_u * 0x3f) << 5;
239 else if (c < 3)
240 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
241 if (c == 3)
242 e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
243 else
244 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
245 if (c == 3)
246 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
247 else
248 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
249 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
250 if (c == 0)
251 e->z24 = f_u * 0xffffff;
252 }
253 }
254
255 #ifdef DEBUG
256 memset(&e->__pad0, 0, sizeof(e->__pad0));
257 memset(&e->__pad1, 0, sizeof(e->__pad1));
258 #endif
259 }
260 }
261
262 static void
263 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
264 {
265 struct fd5_context *fd5_ctx = fd5_context(ctx);
266 struct bcolor_entry *entries;
267 unsigned off;
268 void *ptr;
269
270 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE);
271
272 u_upload_alloc(fd5_ctx->border_color_uploader,
273 0, FD5_BORDER_COLOR_UPLOAD_SIZE,
274 FD5_BORDER_COLOR_UPLOAD_SIZE, &off,
275 &fd5_ctx->border_color_buf,
276 &ptr);
277
278 entries = ptr;
279
280 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
281 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
282 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
283
284 OUT_PKT4(ring, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
285 OUT_RELOC(ring, fd_resource(fd5_ctx->border_color_buf)->bo, off, 0, 0);
286
287 u_upload_unmap(fd5_ctx->border_color_uploader);
288 }
289
290 static bool
291 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
292 enum a4xx_state_block sb, struct fd_texture_stateobj *tex)
293 {
294 bool needs_border = false;
295 unsigned bcolor_offset = (sb == SB4_FS_TEX) ? ctx->tex[PIPE_SHADER_VERTEX].num_samplers : 0;
296 unsigned i;
297
298 if (tex->num_samplers > 0) {
299 /* output sampler state: */
300 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (4 * tex->num_samplers));
301 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
302 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
303 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
304 CP_LOAD_STATE4_0_NUM_UNIT(tex->num_samplers));
305 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
306 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
307 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
308 for (i = 0; i < tex->num_samplers; i++) {
309 static const struct fd5_sampler_stateobj dummy_sampler = {};
310 const struct fd5_sampler_stateobj *sampler = tex->samplers[i] ?
311 fd5_sampler_stateobj(tex->samplers[i]) :
312 &dummy_sampler;
313 OUT_RING(ring, sampler->texsamp0);
314 OUT_RING(ring, sampler->texsamp1);
315 OUT_RING(ring, sampler->texsamp2 |
316 A5XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset));
317 OUT_RING(ring, sampler->texsamp3);
318
319 needs_border |= sampler->needs_border;
320 }
321 }
322
323 if (tex->num_textures > 0) {
324 unsigned num_textures = tex->num_textures;
325
326 /* emit texture state: */
327 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (12 * num_textures));
328 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
329 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
330 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
331 CP_LOAD_STATE4_0_NUM_UNIT(num_textures));
332 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
333 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
334 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
335 for (i = 0; i < tex->num_textures; i++) {
336 static const struct fd5_pipe_sampler_view dummy_view = {};
337 const struct fd5_pipe_sampler_view *view = tex->textures[i] ?
338 fd5_pipe_sampler_view(tex->textures[i]) :
339 &dummy_view;
340
341 OUT_RING(ring, view->texconst0);
342 OUT_RING(ring, view->texconst1);
343 OUT_RING(ring, view->texconst2);
344 OUT_RING(ring, view->texconst3);
345 if (view->base.texture) {
346 struct fd_resource *rsc = fd_resource(view->base.texture);
347 OUT_RELOC(ring, rsc->bo, view->offset,
348 (uint64_t)view->texconst5 << 32, 0);
349 } else {
350 OUT_RING(ring, 0x00000000);
351 OUT_RING(ring, view->texconst5);
352 }
353 OUT_RING(ring, view->texconst6);
354 OUT_RING(ring, view->texconst7);
355 OUT_RING(ring, view->texconst8);
356 OUT_RING(ring, view->texconst9);
357 OUT_RING(ring, view->texconst10);
358 OUT_RING(ring, view->texconst11);
359 }
360 }
361
362 return needs_border;
363 }
364
365 static void
366 emit_ssbos(struct fd_context *ctx, struct fd_ringbuffer *ring,
367 enum a4xx_state_block sb, struct fd_shaderbuf_stateobj *so)
368 {
369 unsigned count = util_last_bit(so->enabled_mask);
370
371 if (count == 0)
372 return;
373
374 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (4 * count));
375 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
376 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
377 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
378 CP_LOAD_STATE4_0_NUM_UNIT(count));
379 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(0) |
380 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
381 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
382 for (unsigned i = 0; i < count; i++) {
383 OUT_RING(ring, 0x00000000);
384 OUT_RING(ring, 0x00000000);
385 OUT_RING(ring, 0x00000000);
386 OUT_RING(ring, 0x00000000);
387 }
388
389 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * count));
390 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
391 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
392 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
393 CP_LOAD_STATE4_0_NUM_UNIT(count));
394 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(1) |
395 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
396 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
397 for (unsigned i = 0; i < count; i++) {
398 struct pipe_shader_buffer *buf = &so->sb[i];
399 unsigned sz = buf->buffer_size;
400
401 /* width is in dwords, overflows into height: */
402 sz /= 4;
403
404 OUT_RING(ring, A5XX_SSBO_1_0_WIDTH(sz));
405 OUT_RING(ring, A5XX_SSBO_1_1_HEIGHT(sz >> 16));
406 }
407
408 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * count));
409 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
410 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
411 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
412 CP_LOAD_STATE4_0_NUM_UNIT(count));
413 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(2) |
414 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
415 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
416 for (unsigned i = 0; i < count; i++) {
417 struct pipe_shader_buffer *buf = &so->sb[i];
418 if (buf->buffer) {
419 struct fd_resource *rsc = fd_resource(buf->buffer);
420 OUT_RELOCW(ring, rsc->bo, buf->buffer_offset, 0, 0);
421 } else {
422 OUT_RING(ring, 0x00000000);
423 OUT_RING(ring, 0x00000000);
424 }
425 }
426 }
427
428 void
429 fd5_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd5_emit *emit)
430 {
431 int32_t i, j;
432 const struct fd_vertex_state *vtx = emit->vtx;
433 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
434
435 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
436 if (vp->inputs[i].sysval)
437 continue;
438 if (vp->inputs[i].compmask) {
439 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
440 const struct pipe_vertex_buffer *vb =
441 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
442 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
443 enum pipe_format pfmt = elem->src_format;
444 enum a5xx_vtx_fmt fmt = fd5_pipe2vtx(pfmt);
445 bool isint = util_format_is_pure_integer(pfmt);
446 uint32_t off = vb->buffer_offset + elem->src_offset;
447 uint32_t size = fd_bo_size(rsc->bo) - off;
448 debug_assert(fmt != ~0);
449
450 OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4);
451 OUT_RELOC(ring, rsc->bo, off, 0, 0);
452 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
453 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
454
455 OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2);
456 OUT_RING(ring, A5XX_VFD_DECODE_INSTR_IDX(j) |
457 A5XX_VFD_DECODE_INSTR_FORMAT(fmt) |
458 COND(elem->instance_divisor, A5XX_VFD_DECODE_INSTR_INSTANCED) |
459 A5XX_VFD_DECODE_INSTR_SWAP(fd5_pipe2swap(pfmt)) |
460 A5XX_VFD_DECODE_INSTR_UNK30 |
461 COND(!isint, A5XX_VFD_DECODE_INSTR_FLOAT));
462 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
463
464 OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1);
465 OUT_RING(ring, A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
466 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
467
468 j++;
469 }
470 }
471
472 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1);
473 OUT_RING(ring, A5XX_VFD_CONTROL_0_VTXCNT(j));
474 }
475
476 void
477 fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
478 struct fd5_emit *emit)
479 {
480 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
481 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
482 const struct ir3_shader_variant *fp = fd5_emit_get_fp(emit);
483 const enum fd_dirty_3d_state dirty = emit->dirty;
484 bool needs_border = false;
485
486 emit_marker5(ring, 5);
487
488 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
489 unsigned char mrt_comp[A5XX_MAX_RENDER_TARGETS] = {0};
490
491 for (unsigned i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
492 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
493 }
494
495 OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1);
496 OUT_RING(ring, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
497 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
498 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
499 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
500 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
501 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
502 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
503 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
504 }
505
506 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
507 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
508 uint32_t rb_alpha_control = zsa->rb_alpha_control;
509
510 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
511 rb_alpha_control &= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST;
512
513 OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1);
514 OUT_RING(ring, rb_alpha_control);
515
516 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1);
517 OUT_RING(ring, zsa->rb_stencil_control);
518 }
519
520 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG)) {
521 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
522 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
523
524 if (pfb->zsbuf) {
525 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
526 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
527
528 if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid)
529 gras_lrz_cntl = 0;
530 else if (emit->key.binning_pass && blend->lrz_write && zsa->lrz_write)
531 gras_lrz_cntl |= A5XX_GRAS_LRZ_CNTL_LRZ_WRITE;
532
533 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
534 OUT_RING(ring, gras_lrz_cntl);
535 }
536 }
537
538 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
539 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
540 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
541
542 OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 2);
543 OUT_RING(ring, zsa->rb_stencilrefmask |
544 A5XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
545 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
546 A5XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
547 }
548
549 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
550 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
551 bool fragz = fp->has_kill | fp->writes_pos;
552
553 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_CNTL, 1);
554 OUT_RING(ring, zsa->rb_depth_cntl);
555
556 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_PLANE_CNTL, 1);
557 OUT_RING(ring, COND(fragz, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
558 COND(fragz && fp->frag_coord, A5XX_RB_DEPTH_PLANE_CNTL_UNK1));
559
560 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
561 OUT_RING(ring, COND(fragz, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
562 COND(fragz && fp->frag_coord, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1));
563 }
564
565 if (dirty & FD_DIRTY_SCISSOR) {
566 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
567
568 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
569 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
570 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
571 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
572 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
573
574 OUT_PKT4(ring, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
575 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
576 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
577 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
578 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
579
580 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
581 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
582 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
583 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
584 }
585
586 if (dirty & FD_DIRTY_VIEWPORT) {
587 fd_wfi(ctx->batch, ring);
588 OUT_PKT4(ring, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0, 6);
589 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
590 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
591 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
592 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
593 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
594 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
595 }
596
597 if (dirty & FD_DIRTY_PROG)
598 fd5_program_emit(ctx, ring, emit);
599
600 if (dirty & FD_DIRTY_RASTERIZER) {
601 struct fd5_rasterizer_stateobj *rasterizer =
602 fd5_rasterizer_stateobj(ctx->rasterizer);
603
604 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
605 OUT_RING(ring, rasterizer->gras_su_cntl);
606
607 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
608 OUT_RING(ring, rasterizer->gras_su_point_minmax);
609 OUT_RING(ring, rasterizer->gras_su_point_size);
610
611 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
612 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
613 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
614 OUT_RING(ring, rasterizer->gras_su_poly_offset_clamp);
615
616 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
617 OUT_RING(ring, rasterizer->pc_raster_cntl);
618
619 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
620 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
621 }
622
623 /* note: must come after program emit.. because there is some overlap
624 * in registers, ex. PC_PRIMITIVE_CNTL and we rely on some cached
625 * values from fd5_program_emit() to avoid having to re-emit the prog
626 * every time rast state changes.
627 *
628 * Since the primitive restart state is not part of a tracked object, we
629 * re-emit this register every time.
630 */
631 if (emit->info && ctx->rasterizer) {
632 struct fd5_rasterizer_stateobj *rasterizer =
633 fd5_rasterizer_stateobj(ctx->rasterizer);
634 unsigned max_loc = fd5_context(ctx)->max_loc;
635
636 OUT_PKT4(ring, REG_A5XX_PC_PRIMITIVE_CNTL, 1);
637 OUT_RING(ring, rasterizer->pc_primitive_cntl |
638 A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(max_loc) |
639 COND(emit->info->primitive_restart && emit->info->index_size,
640 A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART));
641 }
642
643 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
644 uint32_t posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
645 unsigned nr = pfb->nr_cbufs;
646
647 if (emit->key.binning_pass)
648 nr = 0;
649 else if (ctx->rasterizer->rasterizer_discard)
650 nr = 0;
651
652 OUT_PKT4(ring, REG_A5XX_RB_FS_OUTPUT_CNTL, 1);
653 OUT_RING(ring, A5XX_RB_FS_OUTPUT_CNTL_MRT(nr) |
654 COND(fp->writes_pos, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z));
655
656 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_CNTL, 1);
657 OUT_RING(ring, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr) |
658 A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid) |
659 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
660 }
661
662 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
663 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
664 if (!emit->key.binning_pass)
665 ir3_emit_fs_consts(fp, ring, ctx);
666
667 struct pipe_stream_output_info *info = &vp->shader->stream_output;
668 if (info->num_outputs) {
669 struct fd_streamout_stateobj *so = &ctx->streamout;
670
671 for (unsigned i = 0; i < so->num_targets; i++) {
672 struct pipe_stream_output_target *target = so->targets[i];
673
674 if (!target)
675 continue;
676
677 unsigned offset = (so->offsets[i] * info->stride[i] * 4) +
678 target->buffer_offset;
679
680 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(i), 3);
681 /* VPC_SO[i].BUFFER_BASE_LO: */
682 OUT_RELOCW(ring, fd_resource(target->buffer)->bo, 0, 0, 0);
683 OUT_RING(ring, target->buffer_size + offset);
684
685 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(i), 3);
686 OUT_RING(ring, offset);
687 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
688 // TODO just give hw a dummy addr for now.. we should
689 // be using this an then CP_MEM_TO_REG to set the
690 // VPC_SO[i].BUFFER_OFFSET for the next draw..
691 OUT_RELOCW(ring, fd5_context(ctx)->blit_mem, 0x100, 0, 0);
692
693 emit->streamout_mask |= (1 << i);
694 }
695 }
696 }
697
698 if ((dirty & FD_DIRTY_BLEND)) {
699 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
700 uint32_t i;
701
702 for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
703 enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
704 bool is_int = util_format_is_pure_integer(format);
705 bool has_alpha = util_format_has_alpha(format);
706 uint32_t control = blend->rb_mrt[i].control;
707 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
708
709 if (is_int) {
710 control &= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
711 control |= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
712 }
713
714 if (has_alpha) {
715 blend_control |= blend->rb_mrt[i].blend_control_rgb;
716 } else {
717 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
718 control &= ~A5XX_RB_MRT_CONTROL_BLEND2;
719 }
720
721 OUT_PKT4(ring, REG_A5XX_RB_MRT_CONTROL(i), 1);
722 OUT_RING(ring, control);
723
724 OUT_PKT4(ring, REG_A5XX_RB_MRT_BLEND_CONTROL(i), 1);
725 OUT_RING(ring, blend_control);
726 }
727
728 OUT_PKT4(ring, REG_A5XX_RB_BLEND_CNTL, 1);
729 OUT_RING(ring, blend->rb_blend_cntl |
730 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(0xffff));
731
732 OUT_PKT4(ring, REG_A5XX_SP_BLEND_CNTL, 1);
733 OUT_RING(ring, blend->sp_blend_cntl);
734 }
735
736 if (dirty & FD_DIRTY_BLEND_COLOR) {
737 struct pipe_blend_color *bcolor = &ctx->blend_color;
738
739 OUT_PKT4(ring, REG_A5XX_RB_BLEND_RED, 8);
740 OUT_RING(ring, A5XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
741 A5XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
742 A5XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
743 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[0]));
744 OUT_RING(ring, A5XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
745 A5XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
746 A5XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
747 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[1]));
748 OUT_RING(ring, A5XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
749 A5XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
750 A5XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
751 OUT_RING(ring, A5XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
752 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
753 A5XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
754 A5XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
755 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
756 }
757
758 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX) {
759 needs_border |= emit_textures(ctx, ring, SB4_VS_TEX,
760 &ctx->tex[PIPE_SHADER_VERTEX]);
761 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
762 OUT_RING(ring, ctx->tex[PIPE_SHADER_VERTEX].num_textures);
763 }
764
765 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX) {
766 needs_border |= emit_textures(ctx, ring, SB4_FS_TEX,
767 &ctx->tex[PIPE_SHADER_FRAGMENT]);
768 }
769
770 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
771 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_FRAGMENT].enabled_mask ?
772 ~0 : ctx->tex[PIPE_SHADER_FRAGMENT].num_textures);
773
774 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
775 OUT_RING(ring, 0);
776
777 if (needs_border)
778 emit_border_color(ctx, ring);
779
780 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_SSBO)
781 emit_ssbos(ctx, ring, SB4_SSBO, &ctx->shaderbuf[PIPE_SHADER_FRAGMENT]);
782
783 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_IMAGE)
784 fd5_emit_images(ctx, ring, PIPE_SHADER_FRAGMENT);
785 }
786
787 void
788 fd5_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
789 struct ir3_shader_variant *cp)
790 {
791 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
792
793 if (dirty & FD_DIRTY_SHADER_TEX) {
794 bool needs_border = false;
795 needs_border |= emit_textures(ctx, ring, SB4_CS_TEX,
796 &ctx->tex[PIPE_SHADER_COMPUTE]);
797
798 if (needs_border)
799 emit_border_color(ctx, ring);
800
801 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
802 OUT_RING(ring, 0);
803
804 OUT_PKT4(ring, REG_A5XX_TPL1_HS_TEX_COUNT, 1);
805 OUT_RING(ring, 0);
806
807 OUT_PKT4(ring, REG_A5XX_TPL1_DS_TEX_COUNT, 1);
808 OUT_RING(ring, 0);
809
810 OUT_PKT4(ring, REG_A5XX_TPL1_GS_TEX_COUNT, 1);
811 OUT_RING(ring, 0);
812
813 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
814 OUT_RING(ring, 0);
815 }
816
817 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
818 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_COMPUTE].enabled_mask ?
819 ~0 : ctx->tex[PIPE_SHADER_COMPUTE].num_textures);
820
821 if (dirty & FD_DIRTY_SHADER_SSBO)
822 emit_ssbos(ctx, ring, SB4_CS_SSBO, &ctx->shaderbuf[PIPE_SHADER_COMPUTE]);
823
824 if (dirty & FD_DIRTY_SHADER_IMAGE)
825 fd5_emit_images(ctx, ring, PIPE_SHADER_COMPUTE);
826 }
827
828 /* emit setup at begin of new cmdstream buffer (don't rely on previous
829 * state, there could have been a context switch between ioctls):
830 */
831 void
832 fd5_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
833 {
834 struct fd_context *ctx = batch->ctx;
835
836 fd5_set_render_mode(ctx, ring, BYPASS);
837 fd5_cache_flush(batch, ring);
838
839 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
840 OUT_RING(ring, 0xfffff);
841
842 /*
843 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
844 0000000500024048: 70d08003 00000000 001c5000 00000005
845 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
846 0000000500024058: 70d08003 00000010 001c7000 00000005
847
848 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
849 0000000500024068: 70268000
850 */
851
852 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
853 OUT_RING(ring, 0xffffffff);
854
855 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
856 OUT_RING(ring, 0x00000012);
857
858 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
859 OUT_RING(ring, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
860 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
861 OUT_RING(ring, A5XX_GRAS_SU_POINT_SIZE(0.5));
862
863 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
864 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
865
866 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL, 1);
867 OUT_RING(ring, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */
868
869 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG_MAX_CONST, 1);
870 OUT_RING(ring, 0); /* SP_VS_CONFIG_MAX_CONST */
871
872 OUT_PKT4(ring, REG_A5XX_SP_FS_CONFIG_MAX_CONST, 1);
873 OUT_RING(ring, 0); /* SP_FS_CONFIG_MAX_CONST */
874
875 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E292, 2);
876 OUT_RING(ring, 0x00000000); /* UNKNOWN_E292 */
877 OUT_RING(ring, 0x00000000); /* UNKNOWN_E293 */
878
879 OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1);
880 OUT_RING(ring, 0x00000044); /* RB_MODE_CNTL */
881
882 OUT_PKT4(ring, REG_A5XX_RB_DBG_ECO_CNTL, 1);
883 OUT_RING(ring, 0x00100000); /* RB_DBG_ECO_CNTL */
884
885 OUT_PKT4(ring, REG_A5XX_VFD_MODE_CNTL, 1);
886 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
887
888 OUT_PKT4(ring, REG_A5XX_PC_MODE_CNTL, 1);
889 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
890
891 OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1);
892 OUT_RING(ring, 0x0000001e); /* SP_MODE_CNTL */
893
894 OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
895 OUT_RING(ring, 0x40000800); /* SP_DBG_ECO_CNTL */
896
897 OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1);
898 OUT_RING(ring, 0x00000544); /* TPL1_MODE_CNTL */
899
900 OUT_PKT4(ring, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0, 2);
901 OUT_RING(ring, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */
902 OUT_RING(ring, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */
903
904 OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);
905 OUT_RING(ring, 0x00000400); /* VPC_DBG_ECO_CNTL */
906
907 OUT_PKT4(ring, REG_A5XX_HLSQ_MODE_CNTL, 1);
908 OUT_RING(ring, 0x00000001); /* HLSQ_MODE_CNTL */
909
910 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
911 OUT_RING(ring, 0x00000000); /* VPC_MODE_CNTL */
912
913 /* we don't use this yet.. probably best to disable.. */
914 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
915 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
916 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
917 CP_SET_DRAW_STATE__0_GROUP_ID(0));
918 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
919 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
920
921 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
922 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
923
924 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
925 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
926
927 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
928 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
929
930 OUT_PKT4(ring, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL, 1);
931 OUT_RING(ring, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */
932
933 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
934 OUT_RING(ring, A5XX_VPC_SO_OVERRIDE_SO_DISABLE);
935
936 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(0), 3);
937 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
938 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
939 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
940
941 OUT_PKT4(ring, REG_A5XX_VPC_SO_FLUSH_BASE_LO(0), 2);
942 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
943 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
944
945 OUT_PKT4(ring, REG_A5XX_PC_GS_PARAM, 1);
946 OUT_RING(ring, 0x00000000); /* PC_GS_PARAM */
947
948 OUT_PKT4(ring, REG_A5XX_PC_HS_PARAM, 1);
949 OUT_RING(ring, 0x00000000); /* PC_HS_PARAM */
950
951 OUT_PKT4(ring, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL, 1);
952 OUT_RING(ring, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */
953
954 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E001, 1);
955 OUT_RING(ring, 0x00000000); /* UNKNOWN_E001 */
956
957 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E004, 1);
958 OUT_RING(ring, 0x00000000); /* UNKNOWN_E004 */
959
960 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E093, 1);
961 OUT_RING(ring, 0x00000000); /* UNKNOWN_E093 */
962
963 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E29A, 1);
964 OUT_RING(ring, 0x00ffff00); /* UNKNOWN_E29A */
965
966 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUF_CNTL, 1);
967 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
968
969 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(0), 1);
970 OUT_RING(ring, 0x00000000); /* UNKNOWN_E2AB */
971
972 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E389, 1);
973 OUT_RING(ring, 0x00000000); /* UNKNOWN_E389 */
974
975 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E38D, 1);
976 OUT_RING(ring, 0x00000000); /* UNKNOWN_E38D */
977
978 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5AB, 1);
979 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5AB */
980
981 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5C2, 1);
982 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5C2 */
983
984 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(1), 3);
985 OUT_RING(ring, 0x00000000);
986 OUT_RING(ring, 0x00000000);
987 OUT_RING(ring, 0x00000000);
988
989 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(1), 6);
990 OUT_RING(ring, 0x00000000);
991 OUT_RING(ring, 0x00000000);
992 OUT_RING(ring, 0x00000000);
993 OUT_RING(ring, 0x00000000);
994 OUT_RING(ring, 0x00000000);
995 OUT_RING(ring, 0x00000000);
996
997 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(2), 6);
998 OUT_RING(ring, 0x00000000);
999 OUT_RING(ring, 0x00000000);
1000 OUT_RING(ring, 0x00000000);
1001 OUT_RING(ring, 0x00000000);
1002 OUT_RING(ring, 0x00000000);
1003 OUT_RING(ring, 0x00000000);
1004
1005 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(3), 3);
1006 OUT_RING(ring, 0x00000000);
1007 OUT_RING(ring, 0x00000000);
1008 OUT_RING(ring, 0x00000000);
1009
1010 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5DB, 1);
1011 OUT_RING(ring, 0x00000000);
1012
1013 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E600, 1);
1014 OUT_RING(ring, 0x00000000);
1015
1016 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E640, 1);
1017 OUT_RING(ring, 0x00000000);
1018
1019 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 4);
1020 OUT_RING(ring, 0x00000000);
1021 OUT_RING(ring, 0x00000000);
1022 OUT_RING(ring, 0x00000000);
1023 OUT_RING(ring, 0x00000000);
1024
1025 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 2);
1026 OUT_RING(ring, 0x00000000);
1027 OUT_RING(ring, 0x00000000);
1028
1029 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C0, 3);
1030 OUT_RING(ring, 0x00000000);
1031 OUT_RING(ring, 0x00000000);
1032 OUT_RING(ring, 0x00000000);
1033
1034 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C5, 3);
1035 OUT_RING(ring, 0x00000000);
1036 OUT_RING(ring, 0x00000000);
1037 OUT_RING(ring, 0x00000000);
1038
1039 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CA, 3);
1040 OUT_RING(ring, 0x00000000);
1041 OUT_RING(ring, 0x00000000);
1042 OUT_RING(ring, 0x00000000);
1043
1044 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CF, 3);
1045 OUT_RING(ring, 0x00000000);
1046 OUT_RING(ring, 0x00000000);
1047 OUT_RING(ring, 0x00000000);
1048
1049 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D4, 3);
1050 OUT_RING(ring, 0x00000000);
1051 OUT_RING(ring, 0x00000000);
1052 OUT_RING(ring, 0x00000000);
1053
1054 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D9, 3);
1055 OUT_RING(ring, 0x00000000);
1056 OUT_RING(ring, 0x00000000);
1057 OUT_RING(ring, 0x00000000);
1058
1059 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
1060 OUT_RING(ring, 0x00000000);
1061 }
1062
1063 static void
1064 fd5_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
1065 {
1066 __OUT_IB5(ring, target);
1067 }
1068
1069 void
1070 fd5_emit_init(struct pipe_context *pctx)
1071 {
1072 struct fd_context *ctx = fd_context(pctx);
1073 ctx->emit_const = fd5_emit_const;
1074 ctx->emit_const_bo = fd5_emit_const_bo;
1075 ctx->emit_ib = fd5_emit_ib;
1076 }