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freedreno/a5xx: provoking vertex
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd5_emit.h"
38 #include "fd5_blend.h"
39 #include "fd5_context.h"
40 #include "fd5_program.h"
41 #include "fd5_rasterizer.h"
42 #include "fd5_texture.h"
43 #include "fd5_format.h"
44 #include "fd5_zsa.h"
45
46 /* regid: base const register
47 * prsc or dwords: buffer containing constant values
48 * sizedwords: size of const value buffer
49 */
50 static void
51 fd5_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
52 uint32_t regid, uint32_t offset, uint32_t sizedwords,
53 const uint32_t *dwords, struct pipe_resource *prsc)
54 {
55 uint32_t i, sz;
56 enum a4xx_state_src src;
57
58 debug_assert((regid % 4) == 0);
59 debug_assert((sizedwords % 4) == 0);
60
61 if (prsc) {
62 sz = 0;
63 src = SS4_INDIRECT;
64 } else {
65 sz = sizedwords;
66 src = SS4_DIRECT;
67 }
68
69 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sz);
70 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
71 CP_LOAD_STATE4_0_STATE_SRC(src) |
72 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
73 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
74 if (prsc) {
75 struct fd_bo *bo = fd_resource(prsc)->bo;
76 OUT_RELOC(ring, bo, offset,
77 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
78 } else {
79 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
80 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
81 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
82 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
83 }
84 for (i = 0; i < sz; i++) {
85 OUT_RING(ring, dwords[i]);
86 }
87 }
88
89 static void
90 fd5_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
91 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
92 {
93 uint32_t anum = align(num, 2);
94 uint32_t i;
95
96 debug_assert((regid % 4) == 0);
97
98 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * anum));
99 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
100 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
101 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
102 CP_LOAD_STATE4_0_NUM_UNIT(anum/2));
103 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
104 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
105 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
106
107 for (i = 0; i < num; i++) {
108 if (prscs[i]) {
109 if (write) {
110 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
111 } else {
112 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
113 }
114 } else {
115 OUT_RING(ring, 0xbad00000 | (i << 16));
116 OUT_RING(ring, 0xbad00000 | (i << 16));
117 }
118 }
119
120 for (; i < anum; i++) {
121 OUT_RING(ring, 0xffffffff);
122 OUT_RING(ring, 0xffffffff);
123 }
124 }
125
126 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
127 * the same as a6xx then move this somewhere common ;-)
128 *
129 * Entry layout looks like (total size, 0x60 bytes):
130 *
131 * offset | description
132 * -------+-------------
133 * 0x00 | fp32[0]
134 * | fp32[1]
135 * | fp32[2]
136 * | fp32[3]
137 * 0x10 | uint16[0]
138 * | uint16[1]
139 * | uint16[2]
140 * | uint16[3]
141 * 0x18 | int16[0]
142 * | int16[1]
143 * | int16[2]
144 * | int16[3]
145 * 0x20 | fp16[0]
146 * | fp16[1]
147 * | fp16[2]
148 * | fp16[3]
149 * 0x28 | ?? maybe padding ??
150 * 0x30 | uint8[0]
151 * | uint8[1]
152 * | uint8[2]
153 * | uint8[3]
154 * 0x34 | int8[0]
155 * | int8[1]
156 * | int8[2]
157 * | int8[3]
158 * 0x38 | ?? maybe padding ??
159 *
160 * Some uncertainty, because not clear that this actually works properly
161 * with blob, so who knows..
162 */
163
164 struct PACKED bcolor_entry {
165 uint32_t fp32[4];
166 uint16_t ui16[4];
167 int16_t si16[4];
168 uint16_t fp16[4];
169 uint8_t __pad0[8];
170 uint8_t ui8[4];
171 int8_t si8[4];
172 uint8_t __pad1[40];
173 };
174
175 #define FD5_BORDER_COLOR_SIZE 0x60
176 #define FD5_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD5_BORDER_COLOR_SIZE)
177
178 static void
179 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
180 {
181 unsigned i, j;
182
183 for (i = 0; i < tex->num_samplers; i++) {
184 struct bcolor_entry *e = &entries[i];
185 struct pipe_sampler_state *sampler = tex->samplers[i];
186 union pipe_color_union *bc;
187
188 if (!sampler)
189 continue;
190
191 bc = &sampler->border_color;
192
193 /*
194 * XXX HACK ALERT XXX
195 *
196 * The border colors need to be swizzled in a particular
197 * format-dependent order. Even though samplers don't know about
198 * formats, we can assume that with a GL state tracker, there's a
199 * 1:1 correspondence between sampler and texture. Take advantage
200 * of that knowledge.
201 */
202 if ((i >= tex->num_textures) || !tex->textures[i])
203 continue;
204
205 const struct util_format_description *desc =
206 util_format_description(tex->textures[i]->format);
207
208 for (j = 0; j < 4; j++) {
209 int c = desc->swizzle[j];
210
211 if (c >= 4)
212 continue;
213
214 if (desc->channel[c].pure_integer) {
215 float f = bc->i[c];
216
217 e->fp32[j] = fui(f);
218 e->fp16[j] = util_float_to_half(f);
219 e->ui16[j] = bc->ui[c];
220 e->si16[j] = bc->i[c];
221 e->ui8[j] = bc->ui[c];
222 e->si8[j] = bc->i[c];
223 } else {
224 float f = bc->f[c];
225
226 e->fp32[j] = fui(f);
227 e->fp16[j] = util_float_to_half(f);
228 e->ui16[j] = f * 65535.0;
229 e->si16[j] = f * 32767.5;
230 e->ui8[j] = f * 255.0;
231 e->si8[j] = f * 128.0;
232 }
233 }
234
235 #ifdef DEBUG
236 memset(&e->__pad0, 0, sizeof(e->__pad0));
237 memset(&e->__pad1, 0, sizeof(e->__pad1));
238 #endif
239 }
240 }
241
242 static void
243 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
244 {
245 struct fd5_context *fd5_ctx = fd5_context(ctx);
246 struct bcolor_entry *entries;
247 unsigned off;
248 void *ptr;
249
250 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE);
251
252 u_upload_alloc(fd5_ctx->border_color_uploader,
253 0, FD5_BORDER_COLOR_UPLOAD_SIZE,
254 FD5_BORDER_COLOR_UPLOAD_SIZE, &off,
255 &fd5_ctx->border_color_buf,
256 &ptr);
257
258 entries = ptr;
259
260 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
261 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
262 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
263
264 OUT_PKT4(ring, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
265 OUT_RELOC(ring, fd_resource(fd5_ctx->border_color_buf)->bo, off, 0, 0);
266
267 u_upload_unmap(fd5_ctx->border_color_uploader);
268 }
269
270 static bool
271 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
272 enum a4xx_state_block sb, struct fd_texture_stateobj *tex)
273 {
274 bool needs_border = false;
275 unsigned bcolor_offset = (sb == SB4_FS_TEX) ? ctx->tex[PIPE_SHADER_VERTEX].num_samplers : 0;
276 unsigned i;
277
278 if (tex->num_samplers > 0) {
279 /* output sampler state: */
280 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (4 * tex->num_samplers));
281 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
282 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
283 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
284 CP_LOAD_STATE4_0_NUM_UNIT(tex->num_samplers));
285 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
286 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
287 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
288 for (i = 0; i < tex->num_samplers; i++) {
289 static const struct fd5_sampler_stateobj dummy_sampler = {};
290 const struct fd5_sampler_stateobj *sampler = tex->samplers[i] ?
291 fd5_sampler_stateobj(tex->samplers[i]) :
292 &dummy_sampler;
293 OUT_RING(ring, sampler->texsamp0);
294 OUT_RING(ring, sampler->texsamp1);
295 OUT_RING(ring, sampler->texsamp2 |
296 A5XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset));
297 OUT_RING(ring, sampler->texsamp3);
298
299 needs_border |= sampler->needs_border;
300 }
301 }
302
303 if (tex->num_textures > 0) {
304 unsigned num_textures = tex->num_textures;
305
306 /* emit texture state: */
307 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (12 * num_textures));
308 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
309 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
310 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
311 CP_LOAD_STATE4_0_NUM_UNIT(num_textures));
312 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
313 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
314 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
315 for (i = 0; i < tex->num_textures; i++) {
316 static const struct fd5_pipe_sampler_view dummy_view = {};
317 const struct fd5_pipe_sampler_view *view = tex->textures[i] ?
318 fd5_pipe_sampler_view(tex->textures[i]) :
319 &dummy_view;
320
321 OUT_RING(ring, view->texconst0);
322 OUT_RING(ring, view->texconst1);
323 OUT_RING(ring, view->texconst2);
324 OUT_RING(ring, view->texconst3);
325 if (view->base.texture) {
326 struct fd_resource *rsc = fd_resource(view->base.texture);
327 OUT_RELOC(ring, rsc->bo, view->offset,
328 (uint64_t)view->texconst5 << 32, 0);
329 } else {
330 OUT_RING(ring, 0x00000000);
331 OUT_RING(ring, view->texconst5);
332 }
333 OUT_RING(ring, view->texconst6);
334 OUT_RING(ring, view->texconst7);
335 OUT_RING(ring, view->texconst8);
336 OUT_RING(ring, view->texconst9);
337 OUT_RING(ring, view->texconst10);
338 OUT_RING(ring, view->texconst11);
339 }
340 }
341
342 return needs_border;
343 }
344
345 static void
346 emit_ssbos(struct fd_context *ctx, struct fd_ringbuffer *ring,
347 enum a4xx_state_block sb, struct fd_shaderbuf_stateobj *so)
348 {
349 unsigned count = util_last_bit(so->enabled_mask);
350
351 if (count == 0)
352 return;
353
354 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (4 * count));
355 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
356 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
357 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
358 CP_LOAD_STATE4_0_NUM_UNIT(count));
359 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(0) |
360 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
361 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
362 for (unsigned i = 0; i < count; i++) {
363 struct pipe_shader_buffer *buf = &so->sb[i];
364 if (buf->buffer) {
365 struct fd_resource *rsc = fd_resource(buf->buffer);
366 OUT_RELOCW(ring, rsc->bo, 0, 0, 0);
367 } else {
368 OUT_RING(ring, 0x00000000);
369 OUT_RING(ring, 0x00000000);
370 }
371 OUT_RING(ring, 0x00000000);
372 OUT_RING(ring, 0x00000000);
373 }
374
375 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * count));
376 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
377 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
378 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
379 CP_LOAD_STATE4_0_NUM_UNIT(count));
380 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(1) |
381 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
382 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
383 for (unsigned i = 0; i < count; i++) {
384 struct pipe_shader_buffer *buf = &so->sb[i];
385
386 // TODO maybe offset encoded somewhere here??
387 OUT_RING(ring, (buf->buffer_size << 16));
388 OUT_RING(ring, 0x00000000);
389 }
390
391 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * count));
392 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
393 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
394 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
395 CP_LOAD_STATE4_0_NUM_UNIT(count));
396 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(2) |
397 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
398 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
399 for (unsigned i = 0; i < count; i++) {
400 struct pipe_shader_buffer *buf = &so->sb[i];
401 if (buf->buffer) {
402 struct fd_resource *rsc = fd_resource(buf->buffer);
403 OUT_RELOCW(ring, rsc->bo, 0, 0, 0);
404 } else {
405 OUT_RING(ring, 0x00000000);
406 OUT_RING(ring, 0x00000000);
407 }
408 }
409 }
410
411 void
412 fd5_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd5_emit *emit)
413 {
414 int32_t i, j;
415 const struct fd_vertex_state *vtx = emit->vtx;
416 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
417
418 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
419 if (vp->inputs[i].sysval)
420 continue;
421 if (vp->inputs[i].compmask) {
422 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
423 const struct pipe_vertex_buffer *vb =
424 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
425 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
426 enum pipe_format pfmt = elem->src_format;
427 enum a5xx_vtx_fmt fmt = fd5_pipe2vtx(pfmt);
428 bool isint = util_format_is_pure_integer(pfmt);
429 uint32_t off = vb->buffer_offset + elem->src_offset;
430 uint32_t size = fd_bo_size(rsc->bo) - off;
431 debug_assert(fmt != ~0);
432
433 OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4);
434 OUT_RELOC(ring, rsc->bo, off, 0, 0);
435 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
436 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
437
438 OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2);
439 OUT_RING(ring, A5XX_VFD_DECODE_INSTR_IDX(j) |
440 A5XX_VFD_DECODE_INSTR_FORMAT(fmt) |
441 COND(elem->instance_divisor, A5XX_VFD_DECODE_INSTR_INSTANCED) |
442 A5XX_VFD_DECODE_INSTR_UNK30 |
443 COND(!isint, A5XX_VFD_DECODE_INSTR_FLOAT));
444 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
445
446 OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1);
447 OUT_RING(ring, A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
448 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
449
450 j++;
451 }
452 }
453
454 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1);
455 OUT_RING(ring, A5XX_VFD_CONTROL_0_VTXCNT(j));
456 }
457
458 void
459 fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
460 struct fd5_emit *emit)
461 {
462 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
463 const struct ir3_shader_variant *fp = fd5_emit_get_fp(emit);
464 const enum fd_dirty_3d_state dirty = emit->dirty;
465 bool needs_border = false;
466
467 emit_marker5(ring, 5);
468
469 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
470 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
471 unsigned char mrt_comp[A5XX_MAX_RENDER_TARGETS] = {0};
472
473 for (unsigned i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
474 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
475 }
476
477 OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1);
478 OUT_RING(ring, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
479 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
480 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
481 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
482 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
483 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
484 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
485 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
486 }
487
488 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
489 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
490 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
491 uint32_t rb_alpha_control = zsa->rb_alpha_control;
492
493 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
494 rb_alpha_control &= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST;
495
496 OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1);
497 OUT_RING(ring, rb_alpha_control);
498
499 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1);
500 OUT_RING(ring, zsa->rb_stencil_control);
501 }
502
503 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
504 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
505 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
506
507 OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 1);
508 OUT_RING(ring, zsa->rb_stencilrefmask |
509 A5XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
510 }
511
512 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
513 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
514 bool fragz = fp->has_kill | fp->writes_pos;
515
516 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_CNTL, 1);
517 OUT_RING(ring, zsa->rb_depth_cntl);
518
519 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_PLANE_CNTL, 1);
520 OUT_RING(ring, COND(fragz, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
521 COND(fragz && fp->frag_coord, A5XX_RB_DEPTH_PLANE_CNTL_UNK1));
522
523 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
524 OUT_RING(ring, COND(fragz, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
525 COND(fragz && fp->frag_coord, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1));
526 }
527
528 if (dirty & FD_DIRTY_SCISSOR) {
529 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
530
531 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
532 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
533 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
534 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
535 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
536
537 OUT_PKT4(ring, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
538 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
539 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
540 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
541 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
542
543 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
544 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
545 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
546 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
547 }
548
549 if (dirty & FD_DIRTY_VIEWPORT) {
550 fd_wfi(ctx->batch, ring);
551 OUT_PKT4(ring, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0, 6);
552 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
553 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
554 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
555 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
556 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
557 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
558 }
559
560 if (dirty & FD_DIRTY_PROG)
561 fd5_program_emit(ctx, ring, emit);
562
563 /* note: must come after program emit.. because there is some overlap
564 * in registers, ex. PC_PRIMITIVE_CNTL and we rely on some cached
565 * values from fd5_program_emit() to avoid having to re-emit the prog
566 * every time rast state changes.
567 */
568 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_RASTERIZER)) {
569 struct fd5_rasterizer_stateobj *rasterizer =
570 fd5_rasterizer_stateobj(ctx->rasterizer);
571 unsigned max_loc = fd5_context(ctx)->max_loc;
572
573 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
574 OUT_RING(ring, rasterizer->gras_su_cntl);
575
576 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
577 OUT_RING(ring, rasterizer->gras_su_point_minmax);
578 OUT_RING(ring, rasterizer->gras_su_point_size);
579
580 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
581 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
582 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
583 OUT_RING(ring, rasterizer->gras_su_poly_offset_clamp);
584
585 OUT_PKT4(ring, REG_A5XX_PC_PRIMITIVE_CNTL, 1);
586 OUT_RING(ring, rasterizer->pc_primitive_cntl |
587 A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(max_loc));
588 }
589
590 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER)) {
591 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
592 uint32_t posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
593 unsigned nr = pfb->nr_cbufs;
594
595 if (emit->key.binning_pass)
596 nr = 0;
597 else if (ctx->rasterizer->rasterizer_discard)
598 nr = 0;
599
600 OUT_PKT4(ring, REG_A5XX_RB_FS_OUTPUT_CNTL, 1);
601 OUT_RING(ring, A5XX_RB_FS_OUTPUT_CNTL_MRT(nr) |
602 COND(fp->writes_pos, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z));
603
604 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_CNTL, 1);
605 OUT_RING(ring, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr) |
606 A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid) |
607 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
608 }
609
610 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
611 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
612 if (!emit->key.binning_pass)
613 ir3_emit_fs_consts(fp, ring, ctx);
614
615 struct pipe_stream_output_info *info = &vp->shader->stream_output;
616 if (info->num_outputs) {
617 struct fd_streamout_stateobj *so = &ctx->streamout;
618
619 for (unsigned i = 0; i < so->num_targets; i++) {
620 struct pipe_stream_output_target *target = so->targets[i];
621
622 if (!target)
623 continue;
624
625 unsigned offset = (so->offsets[i] * info->stride[i] * 4) +
626 target->buffer_offset;
627
628 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(i), 3);
629 /* VPC_SO[i].BUFFER_BASE_LO: */
630 OUT_RELOCW(ring, fd_resource(target->buffer)->bo, 0, 0, 0);
631 OUT_RING(ring, target->buffer_size + offset);
632
633 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(i), 3);
634 OUT_RING(ring, offset);
635 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
636 // TODO just give hw a dummy addr for now.. we should
637 // be using this an then CP_MEM_TO_REG to set the
638 // VPC_SO[i].BUFFER_OFFSET for the next draw..
639 OUT_RELOCW(ring, fd5_context(ctx)->blit_mem, 0x100, 0, 0);
640
641 emit->streamout_mask |= (1 << i);
642 }
643 }
644 }
645
646 if ((dirty & FD_DIRTY_BLEND)) {
647 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
648 uint32_t i;
649
650 for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
651 enum pipe_format format = pipe_surface_format(
652 ctx->batch->framebuffer.cbufs[i]);
653 bool is_int = util_format_is_pure_integer(format);
654 bool has_alpha = util_format_has_alpha(format);
655 uint32_t control = blend->rb_mrt[i].control;
656 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
657
658 if (is_int) {
659 control &= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
660 // control |= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
661 }
662
663 if (has_alpha) {
664 blend_control |= blend->rb_mrt[i].blend_control_rgb;
665 } else {
666 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
667 control &= ~A5XX_RB_MRT_CONTROL_BLEND2;
668 }
669
670 OUT_PKT4(ring, REG_A5XX_RB_MRT_CONTROL(i), 1);
671 OUT_RING(ring, control);
672
673 OUT_PKT4(ring, REG_A5XX_RB_MRT_BLEND_CONTROL(i), 1);
674 OUT_RING(ring, blend_control);
675 }
676
677 OUT_PKT4(ring, REG_A5XX_RB_BLEND_CNTL, 1);
678 OUT_RING(ring, blend->rb_blend_cntl |
679 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(0xffff));
680
681 OUT_PKT4(ring, REG_A5XX_SP_BLEND_CNTL, 1);
682 OUT_RING(ring, 0x00000100);
683 }
684
685 if (dirty & FD_DIRTY_BLEND_COLOR) {
686 struct pipe_blend_color *bcolor = &ctx->blend_color;
687
688 OUT_PKT4(ring, REG_A5XX_RB_BLEND_RED, 8);
689 OUT_RING(ring, A5XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
690 A5XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
691 A5XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
692 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[0]));
693 OUT_RING(ring, A5XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
694 A5XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
695 A5XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
696 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[1]));
697 OUT_RING(ring, A5XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
698 A5XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
699 A5XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
700 OUT_RING(ring, A5XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
701 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
702 A5XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
703 A5XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
704 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
705 }
706
707 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX) {
708 needs_border |= emit_textures(ctx, ring, SB4_VS_TEX,
709 &ctx->tex[PIPE_SHADER_VERTEX]);
710 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
711 OUT_RING(ring, ctx->tex[PIPE_SHADER_VERTEX].num_textures);
712 }
713
714 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX) {
715 needs_border |= emit_textures(ctx, ring, SB4_FS_TEX,
716 &ctx->tex[PIPE_SHADER_FRAGMENT]);
717 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
718 OUT_RING(ring, ctx->tex[PIPE_SHADER_FRAGMENT].num_textures);
719 }
720
721 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
722 OUT_RING(ring, 0);
723
724 if (needs_border)
725 emit_border_color(ctx, ring);
726
727 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_SSBO)
728 emit_ssbos(ctx, ring, SB4_SSBO, &ctx->shaderbuf[PIPE_SHADER_FRAGMENT]);
729 }
730
731 void
732 fd5_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
733 struct ir3_shader_variant *cp)
734 {
735 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
736
737 if (dirty & FD_DIRTY_SHADER_TEX) {
738 bool needs_border = false;
739 needs_border |= emit_textures(ctx, ring, SB4_CS_TEX,
740 &ctx->tex[PIPE_SHADER_COMPUTE]);
741
742 if (needs_border)
743 emit_border_color(ctx, ring);
744
745 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
746 OUT_RING(ring, 0);
747
748 OUT_PKT4(ring, REG_A5XX_TPL1_HS_TEX_COUNT, 1);
749 OUT_RING(ring, 0);
750
751 OUT_PKT4(ring, REG_A5XX_TPL1_DS_TEX_COUNT, 1);
752 OUT_RING(ring, 0);
753
754 OUT_PKT4(ring, REG_A5XX_TPL1_GS_TEX_COUNT, 1);
755 OUT_RING(ring, 0);
756
757 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
758 OUT_RING(ring, 0);
759
760 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
761 OUT_RING(ring, ctx->tex[PIPE_SHADER_COMPUTE].num_textures);
762 }
763
764 if (dirty & FD_DIRTY_SHADER_SSBO)
765 emit_ssbos(ctx, ring, SB4_CS_SSBO, &ctx->shaderbuf[PIPE_SHADER_COMPUTE]);
766 }
767
768 /* emit setup at begin of new cmdstream buffer (don't rely on previous
769 * state, there could have been a context switch between ioctls):
770 */
771 void
772 fd5_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
773 {
774 struct fd_context *ctx = batch->ctx;
775
776 fd5_set_render_mode(ctx, ring, BYPASS);
777 fd5_cache_flush(batch, ring);
778
779 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
780 OUT_RING(ring, 0xfffff);
781
782 /*
783 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
784 0000000500024048: 70d08003 00000000 001c5000 00000005
785 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
786 0000000500024058: 70d08003 00000010 001c7000 00000005
787
788 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
789 0000000500024068: 70268000
790 */
791
792 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
793 OUT_RING(ring, 0xffffffff);
794
795 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
796 OUT_RING(ring, 0x00000012);
797
798 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
799 OUT_RING(ring, 0x00000000);
800
801 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
802 OUT_RING(ring, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
803 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
804 OUT_RING(ring, A5XX_GRAS_SU_POINT_SIZE(0.5));
805
806 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
807 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
808
809 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL, 1);
810 OUT_RING(ring, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */
811
812 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG_MAX_CONST, 1);
813 OUT_RING(ring, 0); /* SP_VS_CONFIG_MAX_CONST */
814
815 OUT_PKT4(ring, REG_A5XX_SP_FS_CONFIG_MAX_CONST, 1);
816 OUT_RING(ring, 0); /* SP_FS_CONFIG_MAX_CONST */
817
818 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E292, 2);
819 OUT_RING(ring, 0x00000000); /* UNKNOWN_E292 */
820 OUT_RING(ring, 0x00000000); /* UNKNOWN_E293 */
821
822 OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1);
823 OUT_RING(ring, 0x00000044); /* RB_MODE_CNTL */
824
825 OUT_PKT4(ring, REG_A5XX_RB_DBG_ECO_CNTL, 1);
826 OUT_RING(ring, 0x00100000); /* RB_DBG_ECO_CNTL */
827
828 OUT_PKT4(ring, REG_A5XX_VFD_MODE_CNTL, 1);
829 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
830
831 OUT_PKT4(ring, REG_A5XX_PC_MODE_CNTL, 1);
832 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
833
834 OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1);
835 OUT_RING(ring, 0x0000001e); /* SP_MODE_CNTL */
836
837 OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
838 OUT_RING(ring, 0x40000800); /* SP_DBG_ECO_CNTL */
839
840 OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1);
841 OUT_RING(ring, 0x00000544); /* TPL1_MODE_CNTL */
842
843 OUT_PKT4(ring, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0, 2);
844 OUT_RING(ring, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */
845 OUT_RING(ring, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */
846
847 OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);
848 OUT_RING(ring, 0x00000400); /* VPC_DBG_ECO_CNTL */
849
850 OUT_PKT4(ring, REG_A5XX_HLSQ_MODE_CNTL, 1);
851 OUT_RING(ring, 0x00000001); /* HLSQ_MODE_CNTL */
852
853 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
854 OUT_RING(ring, 0x00000000); /* VPC_MODE_CNTL */
855
856 /* we don't use this yet.. probably best to disable.. */
857 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
858 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
859 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
860 CP_SET_DRAW_STATE__0_GROUP_ID(0));
861 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
862 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
863
864 /* other regs not used (yet?) and always seem to have same value: */
865 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
866 OUT_RING(ring, 0x00000080); /* GRAS_CL_CNTL */
867
868 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
869 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
870
871 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
872 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
873
874 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
875 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
876
877 OUT_PKT4(ring, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL, 1);
878 OUT_RING(ring, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */
879
880 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
881 OUT_RING(ring, A5XX_VPC_SO_OVERRIDE_SO_DISABLE);
882
883 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(0), 3);
884 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
885 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
886 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
887
888 OUT_PKT4(ring, REG_A5XX_VPC_SO_FLUSH_BASE_LO(0), 2);
889 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
890 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
891
892 OUT_PKT4(ring, REG_A5XX_PC_GS_PARAM, 1);
893 OUT_RING(ring, 0x00000000); /* PC_GS_PARAM */
894
895 OUT_PKT4(ring, REG_A5XX_PC_HS_PARAM, 1);
896 OUT_RING(ring, 0x00000000); /* PC_HS_PARAM */
897
898 OUT_PKT4(ring, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL, 1);
899 OUT_RING(ring, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */
900
901 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E001, 1);
902 OUT_RING(ring, 0x00000000); /* UNKNOWN_E001 */
903
904 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E004, 1);
905 OUT_RING(ring, 0x00000000); /* UNKNOWN_E004 */
906
907 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E093, 1);
908 OUT_RING(ring, 0x00000000); /* UNKNOWN_E093 */
909
910 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E1C7, 1);
911 OUT_RING(ring, 0x00000000); /* UNKNOWN_E1C7 */
912
913 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E29A, 1);
914 OUT_RING(ring, 0x00ffff00); /* UNKNOWN_E29A */
915
916 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUF_CNTL, 1);
917 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
918
919 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(0), 1);
920 OUT_RING(ring, 0x00000000); /* UNKNOWN_E2AB */
921
922 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E389, 1);
923 OUT_RING(ring, 0x00000000); /* UNKNOWN_E389 */
924
925 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E38D, 1);
926 OUT_RING(ring, 0x00000000); /* UNKNOWN_E38D */
927
928 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5AB, 1);
929 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5AB */
930
931 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5C2, 1);
932 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5C2 */
933
934 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(1), 3);
935 OUT_RING(ring, 0x00000000);
936 OUT_RING(ring, 0x00000000);
937 OUT_RING(ring, 0x00000000);
938
939 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(1), 6);
940 OUT_RING(ring, 0x00000000);
941 OUT_RING(ring, 0x00000000);
942 OUT_RING(ring, 0x00000000);
943 OUT_RING(ring, 0x00000000);
944 OUT_RING(ring, 0x00000000);
945 OUT_RING(ring, 0x00000000);
946
947 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(2), 6);
948 OUT_RING(ring, 0x00000000);
949 OUT_RING(ring, 0x00000000);
950 OUT_RING(ring, 0x00000000);
951 OUT_RING(ring, 0x00000000);
952 OUT_RING(ring, 0x00000000);
953 OUT_RING(ring, 0x00000000);
954
955 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(3), 3);
956 OUT_RING(ring, 0x00000000);
957 OUT_RING(ring, 0x00000000);
958 OUT_RING(ring, 0x00000000);
959
960 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5DB, 1);
961 OUT_RING(ring, 0x00000000);
962
963 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E600, 1);
964 OUT_RING(ring, 0x00000000);
965
966 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E640, 1);
967 OUT_RING(ring, 0x00000000);
968
969 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 4);
970 OUT_RING(ring, 0x00000000);
971 OUT_RING(ring, 0x00000000);
972 OUT_RING(ring, 0x00000000);
973 OUT_RING(ring, 0x00000000);
974
975 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 2);
976 OUT_RING(ring, 0x00000000);
977 OUT_RING(ring, 0x00000000);
978
979 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C0, 3);
980 OUT_RING(ring, 0x00000000);
981 OUT_RING(ring, 0x00000000);
982 OUT_RING(ring, 0x00000000);
983
984 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C5, 3);
985 OUT_RING(ring, 0x00000000);
986 OUT_RING(ring, 0x00000000);
987 OUT_RING(ring, 0x00000000);
988
989 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CA, 3);
990 OUT_RING(ring, 0x00000000);
991 OUT_RING(ring, 0x00000000);
992 OUT_RING(ring, 0x00000000);
993
994 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CF, 3);
995 OUT_RING(ring, 0x00000000);
996 OUT_RING(ring, 0x00000000);
997 OUT_RING(ring, 0x00000000);
998
999 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D4, 3);
1000 OUT_RING(ring, 0x00000000);
1001 OUT_RING(ring, 0x00000000);
1002 OUT_RING(ring, 0x00000000);
1003
1004 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D9, 3);
1005 OUT_RING(ring, 0x00000000);
1006 OUT_RING(ring, 0x00000000);
1007 OUT_RING(ring, 0x00000000);
1008 }
1009
1010 static void
1011 fd5_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
1012 {
1013 __OUT_IB5(ring, target);
1014 }
1015
1016 void
1017 fd5_emit_init(struct pipe_context *pctx)
1018 {
1019 struct fd_context *ctx = fd_context(pctx);
1020 ctx->emit_const = fd5_emit_const;
1021 ctx->emit_const_bo = fd5_emit_const_bo;
1022 ctx->emit_ib = fd5_emit_ib;
1023 }