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freedreno/a5xx: fix discard
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd5_emit.h"
38 #include "fd5_blend.h"
39 #include "fd5_context.h"
40 #include "fd5_program.h"
41 #include "fd5_rasterizer.h"
42 #include "fd5_texture.h"
43 #include "fd5_format.h"
44 #include "fd5_zsa.h"
45
46 static const enum adreno_state_block sb[] = {
47 [SHADER_VERTEX] = SB_VERT_SHADER,
48 [SHADER_FRAGMENT] = SB_FRAG_SHADER,
49 };
50
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
54 */
55 static void
56 fd5_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
57 uint32_t regid, uint32_t offset, uint32_t sizedwords,
58 const uint32_t *dwords, struct pipe_resource *prsc)
59 {
60 uint32_t i, sz;
61 enum adreno_state_src src;
62
63 debug_assert((regid % 4) == 0);
64 debug_assert((sizedwords % 4) == 0);
65
66 if (prsc) {
67 sz = 0;
68 src = 0x2; // TODO ??
69 } else {
70 sz = sizedwords;
71 src = SS_DIRECT;
72 }
73
74 OUT_PKT7(ring, CP_LOAD_STATE, 3 + sz);
75 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
76 CP_LOAD_STATE_0_STATE_SRC(src) |
77 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
78 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/4));
79 if (prsc) {
80 struct fd_bo *bo = fd_resource(prsc)->bo;
81 OUT_RELOC(ring, bo, offset,
82 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
83 } else {
84 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
86 OUT_RING(ring, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
87 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
88 }
89 for (i = 0; i < sz; i++) {
90 OUT_RING(ring, dwords[i]);
91 }
92 }
93
94 static void
95 fd5_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
96 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
97 {
98 uint32_t i;
99
100 debug_assert((regid % 4) == 0);
101 debug_assert((num % 4) == 0);
102
103 OUT_PKT7(ring, CP_LOAD_STATE, 3 + num);
104 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
105 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
106 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
107 CP_LOAD_STATE_0_NUM_UNIT(num/4));
108 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
109 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
110 OUT_RING(ring, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
111
112 for (i = 0; i < num; i++) {
113 if (prscs[i]) {
114 if (write) {
115 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
116 } else {
117 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
118 }
119 } else {
120 OUT_RING(ring, 0xbad00000 | (i << 16));
121 }
122 }
123 }
124
125 static void
126 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
127 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
128 {
129 unsigned i;
130
131 if (tex->num_samplers > 0) {
132 /* output sampler state: */
133 OUT_PKT7(ring, CP_LOAD_STATE, 3 + (4 * tex->num_samplers));
134 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
135 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
136 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
137 CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
138 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
139 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
140 OUT_RING(ring, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
141 for (i = 0; i < tex->num_samplers; i++) {
142 static const struct fd5_sampler_stateobj dummy_sampler = {};
143 const struct fd5_sampler_stateobj *sampler = tex->samplers[i] ?
144 fd5_sampler_stateobj(tex->samplers[i]) :
145 &dummy_sampler;
146 OUT_RING(ring, sampler->texsamp0);
147 OUT_RING(ring, sampler->texsamp1);
148 OUT_RING(ring, sampler->texsamp2);
149 OUT_RING(ring, sampler->texsamp3);
150 }
151 }
152
153 if (tex->num_textures > 0) {
154 unsigned num_textures = tex->num_textures;
155
156 /* emit texture state: */
157 OUT_PKT7(ring, CP_LOAD_STATE, 3 + (12 * num_textures));
158 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
159 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
160 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
161 CP_LOAD_STATE_0_NUM_UNIT(num_textures));
162 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
163 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
164 OUT_RING(ring, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
165 for (i = 0; i < tex->num_textures; i++) {
166 static const struct fd5_pipe_sampler_view dummy_view = {};
167 const struct fd5_pipe_sampler_view *view = tex->textures[i] ?
168 fd5_pipe_sampler_view(tex->textures[i]) :
169 &dummy_view;
170
171 OUT_RING(ring, view->texconst0);
172 OUT_RING(ring, view->texconst1);
173 OUT_RING(ring, view->texconst2);
174 OUT_RING(ring, view->texconst3);
175 if (view->base.texture) {
176 struct fd_resource *rsc = fd_resource(view->base.texture);
177 OUT_RELOC(ring, rsc->bo, view->offset,
178 (uint64_t)view->texconst5 << 32, 0);
179 } else {
180 OUT_RING(ring, 0x00000000);
181 OUT_RING(ring, view->texconst5);
182 }
183 OUT_RING(ring, view->texconst6);
184 OUT_RING(ring, view->texconst7);
185 OUT_RING(ring, view->texconst8);
186 OUT_RING(ring, view->texconst9);
187 OUT_RING(ring, view->texconst10);
188 OUT_RING(ring, view->texconst11);
189 }
190 }
191 }
192
193 void
194 fd5_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd5_emit *emit)
195 {
196 int32_t i, j;
197 const struct fd_vertex_state *vtx = emit->vtx;
198 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
199
200 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
201 if (vp->inputs[i].sysval)
202 continue;
203 if (vp->inputs[i].compmask) {
204 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
205 const struct pipe_vertex_buffer *vb =
206 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
207 struct fd_resource *rsc = fd_resource(vb->buffer);
208 enum pipe_format pfmt = elem->src_format;
209 enum a5xx_vtx_fmt fmt = fd5_pipe2vtx(pfmt);
210 uint32_t off = vb->buffer_offset + elem->src_offset;
211 uint32_t size = fd_bo_size(rsc->bo) - off;
212 debug_assert(fmt != ~0);
213
214 OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4);
215 OUT_RELOC(ring, rsc->bo, off, 0, 0);
216 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
217 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
218
219 OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2);
220 OUT_RING(ring, A5XX_VFD_DECODE_INSTR_IDX(j) |
221 A5XX_VFD_DECODE_INSTR_FORMAT(fmt) |
222 A5XX_VFD_DECODE_INSTR_SWAP(fd5_pipe2swap(pfmt)));
223 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
224
225 OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1);
226 OUT_RING(ring, A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
227 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
228
229 j++;
230 }
231 }
232
233 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1);
234 OUT_RING(ring, A5XX_VFD_CONTROL_0_VTXCNT(j));
235 }
236
237 void
238 fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
239 struct fd5_emit *emit)
240 {
241 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
242 const struct ir3_shader_variant *fp = fd5_emit_get_fp(emit);
243 uint32_t dirty = emit->dirty;
244
245 emit_marker5(ring, 5);
246
247 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
248 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
249 unsigned char mrt_comp[A5XX_MAX_RENDER_TARGETS] = {0};
250
251 for (unsigned i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
252 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
253 }
254
255 OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1);
256 OUT_RING(ring, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
257 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
258 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
259 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
260 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
261 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
262 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
263 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
264 }
265
266 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
267 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
268 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
269 uint32_t rb_alpha_control = zsa->rb_alpha_control;
270
271 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
272 rb_alpha_control &= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST;
273
274 OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1);
275 OUT_RING(ring, rb_alpha_control);
276
277 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1);
278 OUT_RING(ring, zsa->rb_stencil_control);
279 }
280
281 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
282 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
283 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
284
285 OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 1);
286 OUT_RING(ring, zsa->rb_stencilrefmask |
287 A5XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
288 }
289
290 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
291 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
292 bool fragz = fp->has_kill | fp->writes_pos;
293
294 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_CNTL, 1);
295 OUT_RING(ring, zsa->rb_depth_cntl);
296
297 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_PLANE_CNTL, 1);
298 OUT_RING(ring, COND(fragz, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
299
300 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
301 OUT_RING(ring, zsa->gras_su_depth_plane_cntl |
302 COND(fragz, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_ALPHA_TEST_ENABLE));
303 }
304
305 if (dirty & FD_DIRTY_RASTERIZER) {
306 struct fd5_rasterizer_stateobj *rasterizer =
307 fd5_rasterizer_stateobj(ctx->rasterizer);
308
309 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
310 OUT_RING(ring, rasterizer->gras_su_cntl);
311
312 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
313 OUT_RING(ring, rasterizer->gras_su_point_minmax);
314 OUT_RING(ring, rasterizer->gras_su_point_size);
315
316 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
317 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
318 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
319 OUT_RING(ring, rasterizer->gras_su_poly_offset_clamp);
320 }
321
322 /* NOTE: since primitive_restart is not actually part of any
323 * state object, we need to make sure that we always emit
324 * PRIM_VTX_CNTL.. either that or be more clever and detect
325 * when it changes.
326 */
327 if (emit->info) {
328 struct fd5_rasterizer_stateobj *rast =
329 fd5_rasterizer_stateobj(ctx->rasterizer);
330 uint32_t val = rast->pc_prim_vtx_cntl;
331
332 val |= COND(vp->writes_psize, A5XX_PC_PRIM_VTX_CNTL_PSIZE);
333
334 OUT_PKT4(ring, REG_A5XX_PC_PRIM_VTX_CNTL, 1);
335 OUT_RING(ring, val);
336 }
337
338 if (dirty & FD_DIRTY_SCISSOR) {
339 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
340
341 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
342 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
343 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
344 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
345 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
346
347 OUT_PKT4(ring, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
348 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
349 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
350 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
351 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
352
353 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
354 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
355 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
356 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
357 }
358
359 if (dirty & FD_DIRTY_VIEWPORT) {
360 fd_wfi(ctx->batch, ring);
361 OUT_PKT4(ring, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0, 6);
362 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
363 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
364 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
365 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
366 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
367 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
368 }
369
370 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
371 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
372 unsigned n = pfb->nr_cbufs;
373 /* if we have depth/stencil, we need at least on MRT: */
374 if (pfb->zsbuf)
375 n = MAX2(1, n);
376 fd5_program_emit(ring, emit, n, pfb->cbufs);
377 }
378
379 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
380 ir3_emit_consts(vp, ring, ctx, emit->info, dirty);
381 if (!emit->key.binning_pass)
382 ir3_emit_consts(fp, ring, ctx, emit->info, dirty);
383 }
384
385 if ((dirty & FD_DIRTY_BLEND)) {
386 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
387 uint32_t i;
388
389 for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
390 enum pipe_format format = pipe_surface_format(
391 ctx->batch->framebuffer.cbufs[i]);
392 bool is_int = util_format_is_pure_integer(format);
393 bool has_alpha = util_format_has_alpha(format);
394 uint32_t control = blend->rb_mrt[i].control;
395 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
396
397 if (is_int) {
398 control &= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
399 // control |= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
400 }
401
402 if (has_alpha) {
403 blend_control |= blend->rb_mrt[i].blend_control_rgb;
404 } else {
405 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
406 control &= ~A5XX_RB_MRT_CONTROL_BLEND2;
407 }
408
409 OUT_PKT4(ring, REG_A5XX_RB_MRT_CONTROL(i), 1);
410 OUT_RING(ring, control);
411
412 OUT_PKT4(ring, REG_A5XX_RB_MRT_BLEND_CONTROL(i), 1);
413 OUT_RING(ring, blend_control);
414 }
415
416 OUT_PKT4(ring, REG_A5XX_RB_BLEND_CNTL, 1);
417 OUT_RING(ring, blend->rb_blend_cntl |
418 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(0xffff));
419
420 OUT_PKT4(ring, REG_A5XX_SP_BLEND_CNTL, 1);
421 OUT_RING(ring, 0x00000100);
422 }
423
424 if (dirty & FD_DIRTY_BLEND_COLOR) {
425 struct pipe_blend_color *bcolor = &ctx->blend_color;
426
427 OUT_PKT4(ring, REG_A5XX_RB_BLEND_RED, 8);
428 OUT_RING(ring, A5XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
429 A5XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
430 A5XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
431 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[0]));
432 OUT_RING(ring, A5XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
433 A5XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
434 A5XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
435 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[1]));
436 OUT_RING(ring, A5XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
437 A5XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
438 A5XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
439 OUT_RING(ring, A5XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
440 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
441 A5XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
442 A5XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
443 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
444 }
445
446 if (dirty & FD_DIRTY_VERTTEX) {
447 if (vp->has_samp) {
448 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
449 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
450 OUT_RING(ring, ctx->verttex.num_textures);
451 } else {
452 dirty &= ~FD_DIRTY_VERTTEX;
453 }
454 }
455
456 if (dirty & FD_DIRTY_FRAGTEX) {
457 if (fp->has_samp) {
458 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
459 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
460 OUT_RING(ring, ctx->fragtex.num_textures);
461 } else {
462 dirty &= ~FD_DIRTY_FRAGTEX;
463 }
464 }
465
466 ctx->dirty &= ~dirty;
467 }
468
469 /* emit setup at begin of new cmdstream buffer (don't rely on previous
470 * state, there could have been a context switch between ioctls):
471 */
472 void
473 fd5_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
474 {
475 struct fd_context *ctx = batch->ctx;
476
477 fd5_set_render_mode(ctx, ring, BYPASS);
478 fd5_cache_flush(batch, ring);
479
480 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
481 OUT_RING(ring, 0xfffff);
482
483 /*
484 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
485 0000000500024048: 70d08003 00000000 001c5000 00000005
486 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
487 0000000500024058: 70d08003 00000010 001c7000 00000005
488
489 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
490 0000000500024068: 70268000
491 */
492
493 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
494 OUT_RING(ring, 0xffffffff);
495
496 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
497 OUT_RING(ring, 0x00000012);
498
499 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
500 OUT_RING(ring, 0x00000000);
501
502 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
503 OUT_RING(ring, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
504 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
505 OUT_RING(ring, A5XX_GRAS_SU_POINT_SIZE(0.5));
506
507 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
508 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
509
510 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL, 1);
511 OUT_RING(ring, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */
512
513 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG_MAX_CONST, 1);
514 OUT_RING(ring, 0); /* SP_VS_CONFIG_MAX_CONST */
515
516 OUT_PKT4(ring, REG_A5XX_SP_FS_CONFIG_MAX_CONST, 1);
517 OUT_RING(ring, 0); /* SP_FS_CONFIG_MAX_CONST */
518
519 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E292, 2);
520 OUT_RING(ring, 0x00000000); /* UNKNOWN_E292 */
521 OUT_RING(ring, 0x00000000); /* UNKNOWN_E293 */
522
523 OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1);
524 OUT_RING(ring, 0x00000044); /* RB_MODE_CNTL */
525
526 OUT_PKT4(ring, REG_A5XX_RB_DBG_ECO_CNTL, 1);
527 OUT_RING(ring, 0x00100000); /* RB_DBG_ECO_CNTL */
528
529 OUT_PKT4(ring, REG_A5XX_VFD_MODE_CNTL, 1);
530 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
531
532 OUT_PKT4(ring, REG_A5XX_PC_MODE_CNTL, 1);
533 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
534
535 OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1);
536 OUT_RING(ring, 0x0000001e); /* SP_MODE_CNTL */
537
538 OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
539 OUT_RING(ring, 0x40000800); /* SP_DBG_ECO_CNTL */
540
541 OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1);
542 OUT_RING(ring, 0x00000544); /* TPL1_MODE_CNTL */
543
544 OUT_PKT4(ring, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0, 2);
545 OUT_RING(ring, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */
546 OUT_RING(ring, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */
547
548 OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);
549 OUT_RING(ring, 0x00000400); /* VPC_DBG_ECO_CNTL */
550
551 OUT_PKT4(ring, REG_A5XX_HLSQ_MODE_CNTL, 1);
552 OUT_RING(ring, 0x00000001); /* HLSQ_MODE_CNTL */
553
554 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
555 OUT_RING(ring, 0x00000000); /* VPC_MODE_CNTL */
556
557 /* we don't use this yet.. probably best to disable.. */
558 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
559 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
560 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
561 CP_SET_DRAW_STATE__0_GROUP_ID(0));
562 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
563 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
564
565 /* other regs not used (yet?) and always seem to have same value: */
566 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
567 OUT_RING(ring, 0x00000080); /* GRAS_CL_CNTL */
568
569 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
570 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
571
572 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
573 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
574
575 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
576 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
577
578 OUT_PKT4(ring, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL, 1);
579 OUT_RING(ring, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */
580
581 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
582 OUT_RING(ring, 0x00000001); /* VPC_SO_OVERRIDE */
583
584 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO_0, 3);
585 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
586 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
587 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
588
589 OUT_PKT4(ring, REG_A5XX_VPC_SO_FLUSH_BASE_LO_0, 2);
590 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
591 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
592
593 OUT_PKT4(ring, REG_A5XX_PC_GS_PARAM, 1);
594 OUT_RING(ring, 0x00000000); /* PC_GS_PARAM */
595
596 OUT_PKT4(ring, REG_A5XX_PC_HS_PARAM, 1);
597 OUT_RING(ring, 0x00000000); /* PC_HS_PARAM */
598
599 OUT_PKT4(ring, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL, 1);
600 OUT_RING(ring, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */
601
602 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E001, 1);
603 OUT_RING(ring, 0x00000000); /* UNKNOWN_E001 */
604
605 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E004, 1);
606 OUT_RING(ring, 0x00000000); /* UNKNOWN_E004 */
607
608 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E093, 1);
609 OUT_RING(ring, 0x00000000); /* UNKNOWN_E093 */
610
611 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E1C7, 1);
612 OUT_RING(ring, 0x00000000); /* UNKNOWN_E1C7 */
613
614 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E29A, 1);
615 OUT_RING(ring, 0x00ffff00); /* UNKNOWN_E29A */
616
617 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E2A1, 1);
618 OUT_RING(ring, 0x00000000); /* UNKNOWN_E2A1 */
619
620 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E2AB, 1);
621 OUT_RING(ring, 0x00000000); /* UNKNOWN_E2AB */
622
623 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E389, 1);
624 OUT_RING(ring, 0x00000000); /* UNKNOWN_E389 */
625
626 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E38D, 1);
627 OUT_RING(ring, 0x00000000); /* UNKNOWN_E38D */
628
629 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5AB, 1);
630 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5AB */
631
632 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5C2, 1);
633 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5C2 */
634
635 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E2AE, 3);
636 OUT_RING(ring, 0x00000000);
637 OUT_RING(ring, 0x00000000);
638 OUT_RING(ring, 0x00000000);
639
640 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E2B2, 6);
641 OUT_RING(ring, 0x00000000);
642 OUT_RING(ring, 0x00000000);
643 OUT_RING(ring, 0x00000000);
644 OUT_RING(ring, 0x00000000);
645 OUT_RING(ring, 0x00000000);
646 OUT_RING(ring, 0x00000000);
647
648 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E2B9, 6);
649 OUT_RING(ring, 0x00000000);
650 OUT_RING(ring, 0x00000000);
651 OUT_RING(ring, 0x00000000);
652 OUT_RING(ring, 0x00000000);
653 OUT_RING(ring, 0x00000000);
654 OUT_RING(ring, 0x00000000);
655
656 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E2C0, 3);
657 OUT_RING(ring, 0x00000000);
658 OUT_RING(ring, 0x00000000);
659 OUT_RING(ring, 0x00000000);
660
661 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5DB, 1);
662 OUT_RING(ring, 0x00000000);
663
664 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E600, 1);
665 OUT_RING(ring, 0x00000000);
666
667 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E640, 1);
668 OUT_RING(ring, 0x00000000);
669
670 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 4);
671 OUT_RING(ring, 0x00000000);
672 OUT_RING(ring, 0x00000000);
673 OUT_RING(ring, 0x00000000);
674 OUT_RING(ring, 0x00000000);
675
676 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 2);
677 OUT_RING(ring, 0x00000000);
678 OUT_RING(ring, 0x00000000);
679
680 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C0, 3);
681 OUT_RING(ring, 0x00000000);
682 OUT_RING(ring, 0x00000000);
683 OUT_RING(ring, 0x00000000);
684
685 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C5, 3);
686 OUT_RING(ring, 0x00000000);
687 OUT_RING(ring, 0x00000000);
688 OUT_RING(ring, 0x00000000);
689
690 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CA, 3);
691 OUT_RING(ring, 0x00000000);
692 OUT_RING(ring, 0x00000000);
693 OUT_RING(ring, 0x00000000);
694
695 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CF, 3);
696 OUT_RING(ring, 0x00000000);
697 OUT_RING(ring, 0x00000000);
698 OUT_RING(ring, 0x00000000);
699
700 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D4, 3);
701 OUT_RING(ring, 0x00000000);
702 OUT_RING(ring, 0x00000000);
703 OUT_RING(ring, 0x00000000);
704
705 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D9, 3);
706 OUT_RING(ring, 0x00000000);
707 OUT_RING(ring, 0x00000000);
708 OUT_RING(ring, 0x00000000);
709
710 // TODO hacks.. these should not be hardcoded:
711 OUT_PKT4(ring, REG_A5XX_GRAS_SC_CNTL, 1);
712 OUT_RING(ring, 0x00000008); /* GRAS_SC_CNTL */
713
714 fd_hw_query_enable(batch, ring);
715 }
716
717 static void
718 fd5_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
719 {
720 __OUT_IB5(ring, target);
721 }
722
723 void
724 fd5_emit_init(struct pipe_context *pctx)
725 {
726 struct fd_context *ctx = fd_context(pctx);
727 ctx->emit_const = fd5_emit_const;
728 ctx->emit_const_bo = fd5_emit_const_bo;
729 ctx->emit_ib = fd5_emit_ib;
730 }