2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/u_format.h"
32 #include "util/u_viewport.h"
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
38 #include "fd5_blend.h"
39 #include "fd5_context.h"
40 #include "fd5_program.h"
41 #include "fd5_rasterizer.h"
42 #include "fd5_texture.h"
43 #include "fd5_format.h"
46 static const enum adreno_state_block sb
[] = {
47 [SHADER_VERTEX
] = SB_VERT_SHADER
,
48 [SHADER_FRAGMENT
] = SB_FRAG_SHADER
,
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
56 fd5_emit_const(struct fd_ringbuffer
*ring
, enum shader_t type
,
57 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
58 const uint32_t *dwords
, struct pipe_resource
*prsc
)
61 enum adreno_state_src src
;
63 debug_assert((regid
% 4) == 0);
64 debug_assert((sizedwords
% 4) == 0);
74 OUT_PKT7(ring
, CP_LOAD_STATE
, 3 + sz
);
75 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/4) |
76 CP_LOAD_STATE_0_STATE_SRC(src
) |
77 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
78 CP_LOAD_STATE_0_NUM_UNIT(sizedwords
/4));
80 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
81 OUT_RELOC(ring
, bo
, offset
,
82 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
), 0);
84 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
86 OUT_RING(ring
, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
87 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
89 for (i
= 0; i
< sz
; i
++) {
90 OUT_RING(ring
, dwords
[i
]);
95 fd5_emit_const_bo(struct fd_ringbuffer
*ring
, enum shader_t type
, boolean write
,
96 uint32_t regid
, uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
)
98 uint32_t anum
= align(num
, 2);
101 debug_assert((regid
% 4) == 0);
103 OUT_PKT7(ring
, CP_LOAD_STATE
, 3 + (2 * anum
));
104 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/4) |
105 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
106 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
107 CP_LOAD_STATE_0_NUM_UNIT(anum
/2));
108 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
109 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
110 OUT_RING(ring
, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
112 for (i
= 0; i
< num
; i
++) {
115 OUT_RELOCW(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
117 OUT_RELOC(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
120 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
121 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
125 for (; i
< anum
; i
++) {
126 OUT_RING(ring
, 0xffffffff);
127 OUT_RING(ring
, 0xffffffff);
131 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
132 * the same as a6xx then move this somewhere common ;-)
134 * Entry layout looks like (total size, 0x60 bytes):
136 * offset | description
137 * -------+-------------
154 * 0x28 | ?? maybe padding ??
163 * 0x38 | ?? maybe padding ??
165 * Some uncertainty, because not clear that this actually works properly
166 * with blob, so who knows..
169 struct PACKED bcolor_entry
{
180 #define FD5_BORDER_COLOR_SIZE 0x60
181 #define FD5_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD5_BORDER_COLOR_SIZE)
182 #define FD5_BORDER_COLOR_OFFSET 8 /* TODO probably should be dynamic */
185 setup_border_colors(struct fd_texture_stateobj
*tex
, struct bcolor_entry
*entries
)
189 debug_assert(tex
->num_samplers
< FD5_BORDER_COLOR_OFFSET
); // TODO
191 for (i
= 0; i
< tex
->num_samplers
; i
++) {
192 struct bcolor_entry
*e
= &entries
[i
];
193 struct pipe_sampler_state
*sampler
= tex
->samplers
[i
];
194 union pipe_color_union
*bc
;
199 bc
= &sampler
->border_color
;
204 * The border colors need to be swizzled in a particular
205 * format-dependent order. Even though samplers don't know about
206 * formats, we can assume that with a GL state tracker, there's a
207 * 1:1 correspondence between sampler and texture. Take advantage
210 if ((i
>= tex
->num_textures
) || !tex
->textures
[i
])
213 const struct util_format_description
*desc
=
214 util_format_description(tex
->textures
[i
]->format
);
216 for (j
= 0; j
< 4; j
++) {
217 int c
= desc
->swizzle
[j
];
222 if (desc
->channel
[c
].pure_integer
) {
226 e
->fp16
[j
] = util_float_to_half(f
);
227 e
->ui16
[j
] = bc
->ui
[c
];
228 e
->si16
[j
] = bc
->i
[c
];
229 e
->ui8
[j
] = bc
->ui
[c
];
230 e
->si8
[j
] = bc
->i
[c
];
235 e
->fp16
[j
] = util_float_to_half(f
);
236 e
->ui16
[j
] = f
* 65535.0;
237 e
->si16
[j
] = f
* 32767.5;
238 e
->ui8
[j
] = f
* 255.0;
239 e
->si8
[j
] = f
* 128.0;
244 memset(&e
->__pad0
, 0, sizeof(e
->__pad0
));
245 memset(&e
->__pad1
, 0, sizeof(e
->__pad1
));
251 emit_border_color(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
)
253 struct fd5_context
*fd5_ctx
= fd5_context(ctx
);
254 struct bcolor_entry
*entries
;
258 STATIC_ASSERT(sizeof(struct bcolor_entry
) == FD5_BORDER_COLOR_SIZE
);
260 u_upload_alloc(fd5_ctx
->border_color_uploader
,
261 0, FD5_BORDER_COLOR_UPLOAD_SIZE
,
262 FD5_BORDER_COLOR_UPLOAD_SIZE
, &off
,
263 &fd5_ctx
->border_color_buf
,
268 setup_border_colors(&ctx
->verttex
, &entries
[0]);
269 setup_border_colors(&ctx
->fragtex
, &entries
[ctx
->verttex
.num_samplers
]);
271 OUT_PKT4(ring
, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO
, 2);
272 OUT_RELOC(ring
, fd_resource(fd5_ctx
->border_color_buf
)->bo
, off
, 0, 0);
274 u_upload_unmap(fd5_ctx
->border_color_uploader
);
278 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
279 enum adreno_state_block sb
, struct fd_texture_stateobj
*tex
)
281 bool needs_border
= false;
282 unsigned bcolor_offset
= (sb
== SB_FRAG_TEX
) ? ctx
->verttex
.num_samplers
: 0;
285 if (tex
->num_samplers
> 0) {
286 /* output sampler state: */
287 OUT_PKT7(ring
, CP_LOAD_STATE
, 3 + (4 * tex
->num_samplers
));
288 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
289 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
290 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
291 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_samplers
));
292 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
293 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
294 OUT_RING(ring
, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
295 for (i
= 0; i
< tex
->num_samplers
; i
++) {
296 static const struct fd5_sampler_stateobj dummy_sampler
= {};
297 const struct fd5_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
298 fd5_sampler_stateobj(tex
->samplers
[i
]) :
300 OUT_RING(ring
, sampler
->texsamp0
);
301 OUT_RING(ring
, sampler
->texsamp1
);
302 OUT_RING(ring
, sampler
->texsamp2
|
303 A5XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset
));
304 OUT_RING(ring
, sampler
->texsamp3
);
306 needs_border
|= sampler
->needs_border
;
310 if (tex
->num_textures
> 0) {
311 unsigned num_textures
= tex
->num_textures
;
313 /* emit texture state: */
314 OUT_PKT7(ring
, CP_LOAD_STATE
, 3 + (12 * num_textures
));
315 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
316 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
317 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
318 CP_LOAD_STATE_0_NUM_UNIT(num_textures
));
319 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
320 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
321 OUT_RING(ring
, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
322 for (i
= 0; i
< tex
->num_textures
; i
++) {
323 static const struct fd5_pipe_sampler_view dummy_view
= {};
324 const struct fd5_pipe_sampler_view
*view
= tex
->textures
[i
] ?
325 fd5_pipe_sampler_view(tex
->textures
[i
]) :
328 OUT_RING(ring
, view
->texconst0
);
329 OUT_RING(ring
, view
->texconst1
);
330 OUT_RING(ring
, view
->texconst2
);
331 OUT_RING(ring
, view
->texconst3
);
332 if (view
->base
.texture
) {
333 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
334 OUT_RELOC(ring
, rsc
->bo
, view
->offset
,
335 (uint64_t)view
->texconst5
<< 32, 0);
337 OUT_RING(ring
, 0x00000000);
338 OUT_RING(ring
, view
->texconst5
);
340 OUT_RING(ring
, view
->texconst6
);
341 OUT_RING(ring
, view
->texconst7
);
342 OUT_RING(ring
, view
->texconst8
);
343 OUT_RING(ring
, view
->texconst9
);
344 OUT_RING(ring
, view
->texconst10
);
345 OUT_RING(ring
, view
->texconst11
);
353 fd5_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd5_emit
*emit
)
356 const struct fd_vertex_state
*vtx
= emit
->vtx
;
357 const struct ir3_shader_variant
*vp
= fd5_emit_get_vp(emit
);
359 for (i
= 0, j
= 0; i
<= vp
->inputs_count
; i
++) {
360 if (vp
->inputs
[i
].sysval
)
362 if (vp
->inputs
[i
].compmask
) {
363 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
364 const struct pipe_vertex_buffer
*vb
=
365 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
366 struct fd_resource
*rsc
= fd_resource(vb
->buffer
);
367 enum pipe_format pfmt
= elem
->src_format
;
368 enum a5xx_vtx_fmt fmt
= fd5_pipe2vtx(pfmt
);
369 uint32_t off
= vb
->buffer_offset
+ elem
->src_offset
;
370 uint32_t size
= fd_bo_size(rsc
->bo
) - off
;
371 debug_assert(fmt
!= ~0);
373 OUT_PKT4(ring
, REG_A5XX_VFD_FETCH(j
), 4);
374 OUT_RELOC(ring
, rsc
->bo
, off
, 0, 0);
375 OUT_RING(ring
, size
); /* VFD_FETCH[j].SIZE */
376 OUT_RING(ring
, vb
->stride
); /* VFD_FETCH[j].STRIDE */
378 OUT_PKT4(ring
, REG_A5XX_VFD_DECODE(j
), 2);
379 OUT_RING(ring
, A5XX_VFD_DECODE_INSTR_IDX(j
) |
380 A5XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
382 OUT_RING(ring
, MAX2(1, elem
->instance_divisor
)); /* VFD_DECODE[j].STEP_RATE */
384 OUT_PKT4(ring
, REG_A5XX_VFD_DEST_CNTL(j
), 1);
385 OUT_RING(ring
, A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
386 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp
->inputs
[i
].regid
));
392 OUT_PKT4(ring
, REG_A5XX_VFD_CONTROL_0
, 1);
393 OUT_RING(ring
, A5XX_VFD_CONTROL_0_VTXCNT(j
));
397 fd5_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
398 struct fd5_emit
*emit
)
400 const struct ir3_shader_variant
*vp
= fd5_emit_get_vp(emit
);
401 const struct ir3_shader_variant
*fp
= fd5_emit_get_fp(emit
);
402 uint32_t dirty
= emit
->dirty
;
403 bool needs_border
= false;
405 emit_marker5(ring
, 5);
407 if ((dirty
& FD_DIRTY_FRAMEBUFFER
) && !emit
->key
.binning_pass
) {
408 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
409 unsigned char mrt_comp
[A5XX_MAX_RENDER_TARGETS
] = {0};
411 for (unsigned i
= 0; i
< A5XX_MAX_RENDER_TARGETS
; i
++) {
412 mrt_comp
[i
] = ((i
< pfb
->nr_cbufs
) && pfb
->cbufs
[i
]) ? 0xf : 0;
415 OUT_PKT4(ring
, REG_A5XX_RB_RENDER_COMPONENTS
, 1);
416 OUT_RING(ring
, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
417 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
418 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
419 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
420 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
421 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
422 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
423 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
426 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_FRAMEBUFFER
)) {
427 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
428 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
429 uint32_t rb_alpha_control
= zsa
->rb_alpha_control
;
431 if (util_format_is_pure_integer(pipe_surface_format(pfb
->cbufs
[0])))
432 rb_alpha_control
&= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST
;
434 OUT_PKT4(ring
, REG_A5XX_RB_ALPHA_CONTROL
, 1);
435 OUT_RING(ring
, rb_alpha_control
);
437 OUT_PKT4(ring
, REG_A5XX_RB_STENCIL_CONTROL
, 1);
438 OUT_RING(ring
, zsa
->rb_stencil_control
);
441 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
442 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
443 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
445 OUT_PKT4(ring
, REG_A5XX_RB_STENCILREFMASK
, 1);
446 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
447 A5XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
450 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
451 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
452 bool fragz
= fp
->has_kill
| fp
->writes_pos
;
454 OUT_PKT4(ring
, REG_A5XX_RB_DEPTH_CNTL
, 1);
455 OUT_RING(ring
, zsa
->rb_depth_cntl
);
457 OUT_PKT4(ring
, REG_A5XX_RB_DEPTH_PLANE_CNTL
, 1);
458 OUT_RING(ring
, COND(fragz
, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
));
460 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
461 OUT_RING(ring
, COND(fragz
, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
));
464 if (dirty
& FD_DIRTY_RASTERIZER
) {
465 struct fd5_rasterizer_stateobj
*rasterizer
=
466 fd5_rasterizer_stateobj(ctx
->rasterizer
);
468 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_CNTL
, 1);
469 OUT_RING(ring
, rasterizer
->gras_su_cntl
);
471 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_POINT_MINMAX
, 2);
472 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
473 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
475 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE
, 3);
476 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
477 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
478 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_clamp
);
481 /* NOTE: since primitive_restart is not actually part of any
482 * state object, we need to make sure that we always emit
483 * PRIM_VTX_CNTL.. either that or be more clever and detect
487 struct fd5_rasterizer_stateobj
*rast
=
488 fd5_rasterizer_stateobj(ctx
->rasterizer
);
489 uint32_t val
= rast
->pc_prim_vtx_cntl
;
491 val
|= COND(vp
->writes_psize
, A5XX_PC_PRIM_VTX_CNTL_PSIZE
);
493 OUT_PKT4(ring
, REG_A5XX_PC_PRIM_VTX_CNTL
, 1);
497 if (dirty
& FD_DIRTY_SCISSOR
) {
498 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
500 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0
, 2);
501 OUT_RING(ring
, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor
->minx
) |
502 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor
->miny
));
503 OUT_RING(ring
, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor
->maxx
- 1) |
504 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor
->maxy
- 1));
506 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0
, 2);
507 OUT_RING(ring
, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor
->minx
) |
508 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor
->miny
));
509 OUT_RING(ring
, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor
->maxx
- 1) |
510 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor
->maxy
- 1));
512 ctx
->batch
->max_scissor
.minx
= MIN2(ctx
->batch
->max_scissor
.minx
, scissor
->minx
);
513 ctx
->batch
->max_scissor
.miny
= MIN2(ctx
->batch
->max_scissor
.miny
, scissor
->miny
);
514 ctx
->batch
->max_scissor
.maxx
= MAX2(ctx
->batch
->max_scissor
.maxx
, scissor
->maxx
);
515 ctx
->batch
->max_scissor
.maxy
= MAX2(ctx
->batch
->max_scissor
.maxy
, scissor
->maxy
);
518 if (dirty
& FD_DIRTY_VIEWPORT
) {
519 fd_wfi(ctx
->batch
, ring
);
520 OUT_PKT4(ring
, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
521 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_XOFFSET_0(ctx
->viewport
.translate
[0]));
522 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_XSCALE_0(ctx
->viewport
.scale
[0]));
523 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_YOFFSET_0(ctx
->viewport
.translate
[1]));
524 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_YSCALE_0(ctx
->viewport
.scale
[1]));
525 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_ZOFFSET_0(ctx
->viewport
.translate
[2]));
526 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx
->viewport
.scale
[2]));
529 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_FRAMEBUFFER
)) {
530 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
531 unsigned n
= pfb
->nr_cbufs
;
532 /* if we have depth/stencil, we need at least on MRT: */
535 fd5_program_emit(ring
, emit
, n
, pfb
->cbufs
);
538 if (emit
->prog
== &ctx
->prog
) { /* evil hack to deal sanely with clear path */
539 ir3_emit_consts(vp
, ring
, ctx
, emit
->info
, dirty
);
540 if (!emit
->key
.binning_pass
)
541 ir3_emit_consts(fp
, ring
, ctx
, emit
->info
, dirty
);
544 if ((dirty
& FD_DIRTY_BLEND
)) {
545 struct fd5_blend_stateobj
*blend
= fd5_blend_stateobj(ctx
->blend
);
548 for (i
= 0; i
< A5XX_MAX_RENDER_TARGETS
; i
++) {
549 enum pipe_format format
= pipe_surface_format(
550 ctx
->batch
->framebuffer
.cbufs
[i
]);
551 bool is_int
= util_format_is_pure_integer(format
);
552 bool has_alpha
= util_format_has_alpha(format
);
553 uint32_t control
= blend
->rb_mrt
[i
].control
;
554 uint32_t blend_control
= blend
->rb_mrt
[i
].blend_control_alpha
;
557 control
&= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
558 // control |= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
562 blend_control
|= blend
->rb_mrt
[i
].blend_control_rgb
;
564 blend_control
|= blend
->rb_mrt
[i
].blend_control_no_alpha_rgb
;
565 control
&= ~A5XX_RB_MRT_CONTROL_BLEND2
;
568 OUT_PKT4(ring
, REG_A5XX_RB_MRT_CONTROL(i
), 1);
569 OUT_RING(ring
, control
);
571 OUT_PKT4(ring
, REG_A5XX_RB_MRT_BLEND_CONTROL(i
), 1);
572 OUT_RING(ring
, blend_control
);
575 OUT_PKT4(ring
, REG_A5XX_RB_BLEND_CNTL
, 1);
576 OUT_RING(ring
, blend
->rb_blend_cntl
|
577 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(0xffff));
579 OUT_PKT4(ring
, REG_A5XX_SP_BLEND_CNTL
, 1);
580 OUT_RING(ring
, 0x00000100);
583 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
584 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
586 OUT_PKT4(ring
, REG_A5XX_RB_BLEND_RED
, 8);
587 OUT_RING(ring
, A5XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]) |
588 A5XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 0xff) |
589 A5XX_RB_BLEND_RED_SINT(bcolor
->color
[0] * 0x7f));
590 OUT_RING(ring
, A5XX_RB_BLEND_RED_F32(bcolor
->color
[0]));
591 OUT_RING(ring
, A5XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]) |
592 A5XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 0xff) |
593 A5XX_RB_BLEND_GREEN_SINT(bcolor
->color
[1] * 0x7f));
594 OUT_RING(ring
, A5XX_RB_BLEND_RED_F32(bcolor
->color
[1]));
595 OUT_RING(ring
, A5XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]) |
596 A5XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 0xff) |
597 A5XX_RB_BLEND_BLUE_SINT(bcolor
->color
[2] * 0x7f));
598 OUT_RING(ring
, A5XX_RB_BLEND_BLUE_F32(bcolor
->color
[2]));
599 OUT_RING(ring
, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]) |
600 A5XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 0xff) |
601 A5XX_RB_BLEND_ALPHA_SINT(bcolor
->color
[3] * 0x7f));
602 OUT_RING(ring
, A5XX_RB_BLEND_ALPHA_F32(bcolor
->color
[3]));
605 if (dirty
& FD_DIRTY_VERTTEX
) {
607 needs_border
|= emit_textures(ctx
, ring
, SB_VERT_TEX
, &ctx
->verttex
);
608 OUT_PKT4(ring
, REG_A5XX_TPL1_VS_TEX_COUNT
, 1);
609 OUT_RING(ring
, ctx
->verttex
.num_textures
);
611 dirty
&= ~FD_DIRTY_VERTTEX
;
615 if (dirty
& FD_DIRTY_FRAGTEX
) {
617 needs_border
|= emit_textures(ctx
, ring
, SB_FRAG_TEX
, &ctx
->fragtex
);
618 OUT_PKT4(ring
, REG_A5XX_TPL1_FS_TEX_COUNT
, 1);
619 OUT_RING(ring
, ctx
->fragtex
.num_textures
);
621 dirty
&= ~FD_DIRTY_FRAGTEX
;
626 emit_border_color(ctx
, ring
);
628 ctx
->dirty
&= ~dirty
;
631 /* emit setup at begin of new cmdstream buffer (don't rely on previous
632 * state, there could have been a context switch between ioctls):
635 fd5_emit_restore(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
637 struct fd_context
*ctx
= batch
->ctx
;
639 fd5_set_render_mode(ctx
, ring
, BYPASS
);
640 fd5_cache_flush(batch
, ring
);
642 OUT_PKT4(ring
, REG_A5XX_HLSQ_UPDATE_CNTL
, 1);
643 OUT_RING(ring
, 0xfffff);
646 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
647 0000000500024048: 70d08003 00000000 001c5000 00000005
648 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
649 0000000500024058: 70d08003 00000010 001c7000 00000005
651 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
652 0000000500024068: 70268000
655 OUT_PKT4(ring
, REG_A5XX_PC_RESTART_INDEX
, 1);
656 OUT_RING(ring
, 0xffffffff);
658 OUT_PKT4(ring
, REG_A5XX_PC_RASTER_CNTL
, 1);
659 OUT_RING(ring
, 0x00000012);
661 OUT_PKT4(ring
, REG_A5XX_GRAS_LRZ_CNTL
, 1);
662 OUT_RING(ring
, 0x00000000);
664 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_POINT_MINMAX
, 2);
665 OUT_RING(ring
, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
666 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
667 OUT_RING(ring
, A5XX_GRAS_SU_POINT_SIZE(0.5));
669 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL
, 1);
670 OUT_RING(ring
, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
672 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL
, 1);
673 OUT_RING(ring
, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */
675 OUT_PKT4(ring
, REG_A5XX_SP_VS_CONFIG_MAX_CONST
, 1);
676 OUT_RING(ring
, 0); /* SP_VS_CONFIG_MAX_CONST */
678 OUT_PKT4(ring
, REG_A5XX_SP_FS_CONFIG_MAX_CONST
, 1);
679 OUT_RING(ring
, 0); /* SP_FS_CONFIG_MAX_CONST */
681 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E292
, 2);
682 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E292 */
683 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E293 */
685 OUT_PKT4(ring
, REG_A5XX_RB_MODE_CNTL
, 1);
686 OUT_RING(ring
, 0x00000044); /* RB_MODE_CNTL */
688 OUT_PKT4(ring
, REG_A5XX_RB_DBG_ECO_CNTL
, 1);
689 OUT_RING(ring
, 0x00100000); /* RB_DBG_ECO_CNTL */
691 OUT_PKT4(ring
, REG_A5XX_VFD_MODE_CNTL
, 1);
692 OUT_RING(ring
, 0x00000000); /* VFD_MODE_CNTL */
694 OUT_PKT4(ring
, REG_A5XX_PC_MODE_CNTL
, 1);
695 OUT_RING(ring
, 0x0000001f); /* PC_MODE_CNTL */
697 OUT_PKT4(ring
, REG_A5XX_SP_MODE_CNTL
, 1);
698 OUT_RING(ring
, 0x0000001e); /* SP_MODE_CNTL */
700 OUT_PKT4(ring
, REG_A5XX_SP_DBG_ECO_CNTL
, 1);
701 OUT_RING(ring
, 0x40000800); /* SP_DBG_ECO_CNTL */
703 OUT_PKT4(ring
, REG_A5XX_TPL1_MODE_CNTL
, 1);
704 OUT_RING(ring
, 0x00000544); /* TPL1_MODE_CNTL */
706 OUT_PKT4(ring
, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0
, 2);
707 OUT_RING(ring
, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */
708 OUT_RING(ring
, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */
710 OUT_PKT4(ring
, REG_A5XX_VPC_DBG_ECO_CNTL
, 1);
711 OUT_RING(ring
, 0x00000400); /* VPC_DBG_ECO_CNTL */
713 OUT_PKT4(ring
, REG_A5XX_HLSQ_MODE_CNTL
, 1);
714 OUT_RING(ring
, 0x00000001); /* HLSQ_MODE_CNTL */
716 OUT_PKT4(ring
, REG_A5XX_VPC_MODE_CNTL
, 1);
717 OUT_RING(ring
, 0x00000000); /* VPC_MODE_CNTL */
719 /* we don't use this yet.. probably best to disable.. */
720 OUT_PKT7(ring
, CP_SET_DRAW_STATE
, 3);
721 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
722 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
723 CP_SET_DRAW_STATE__0_GROUP_ID(0));
724 OUT_RING(ring
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
725 OUT_RING(ring
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
727 /* other regs not used (yet?) and always seem to have same value: */
728 OUT_PKT4(ring
, REG_A5XX_GRAS_CL_CNTL
, 1);
729 OUT_RING(ring
, 0x00000080); /* GRAS_CL_CNTL */
731 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL
, 1);
732 OUT_RING(ring
, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
734 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_BIN_CNTL
, 1);
735 OUT_RING(ring
, 0x00000000); /* GRAS_SC_BIN_CNTL */
737 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_BIN_CNTL
, 1);
738 OUT_RING(ring
, 0x00000000); /* GRAS_SC_BIN_CNTL */
740 OUT_PKT4(ring
, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL
, 1);
741 OUT_RING(ring
, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */
743 OUT_PKT4(ring
, REG_A5XX_VPC_SO_OVERRIDE
, 1);
744 OUT_RING(ring
, A5XX_VPC_SO_OVERRIDE_SO_DISABLE
);
746 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_BASE_LO(0), 3);
747 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
748 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
749 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
751 OUT_PKT4(ring
, REG_A5XX_VPC_SO_FLUSH_BASE_LO(0), 2);
752 OUT_RING(ring
, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
753 OUT_RING(ring
, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
755 OUT_PKT4(ring
, REG_A5XX_PC_GS_PARAM
, 1);
756 OUT_RING(ring
, 0x00000000); /* PC_GS_PARAM */
758 OUT_PKT4(ring
, REG_A5XX_PC_HS_PARAM
, 1);
759 OUT_RING(ring
, 0x00000000); /* PC_HS_PARAM */
761 OUT_PKT4(ring
, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL
, 1);
762 OUT_RING(ring
, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */
764 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E001
, 1);
765 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E001 */
767 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E004
, 1);
768 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E004 */
770 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E093
, 1);
771 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E093 */
773 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E1C7
, 1);
774 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E1C7 */
776 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E29A
, 1);
777 OUT_RING(ring
, 0x00ffff00); /* UNKNOWN_E29A */
779 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUF_CNTL
, 1);
780 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUF_CNTL */
782 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(0), 1);
783 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E2AB */
785 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E389
, 1);
786 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E389 */
788 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E38D
, 1);
789 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E38D */
791 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E5AB
, 1);
792 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E5AB */
794 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E5C2
, 1);
795 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E5C2 */
797 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_BASE_LO(1), 3);
798 OUT_RING(ring
, 0x00000000);
799 OUT_RING(ring
, 0x00000000);
800 OUT_RING(ring
, 0x00000000);
802 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(1), 6);
803 OUT_RING(ring
, 0x00000000);
804 OUT_RING(ring
, 0x00000000);
805 OUT_RING(ring
, 0x00000000);
806 OUT_RING(ring
, 0x00000000);
807 OUT_RING(ring
, 0x00000000);
808 OUT_RING(ring
, 0x00000000);
810 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(2), 6);
811 OUT_RING(ring
, 0x00000000);
812 OUT_RING(ring
, 0x00000000);
813 OUT_RING(ring
, 0x00000000);
814 OUT_RING(ring
, 0x00000000);
815 OUT_RING(ring
, 0x00000000);
816 OUT_RING(ring
, 0x00000000);
818 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(3), 3);
819 OUT_RING(ring
, 0x00000000);
820 OUT_RING(ring
, 0x00000000);
821 OUT_RING(ring
, 0x00000000);
823 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E5DB
, 1);
824 OUT_RING(ring
, 0x00000000);
826 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E600
, 1);
827 OUT_RING(ring
, 0x00000000);
829 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E640
, 1);
830 OUT_RING(ring
, 0x00000000);
832 OUT_PKT4(ring
, REG_A5XX_TPL1_VS_TEX_COUNT
, 4);
833 OUT_RING(ring
, 0x00000000);
834 OUT_RING(ring
, 0x00000000);
835 OUT_RING(ring
, 0x00000000);
836 OUT_RING(ring
, 0x00000000);
838 OUT_PKT4(ring
, REG_A5XX_TPL1_FS_TEX_COUNT
, 2);
839 OUT_RING(ring
, 0x00000000);
840 OUT_RING(ring
, 0x00000000);
842 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7C0
, 3);
843 OUT_RING(ring
, 0x00000000);
844 OUT_RING(ring
, 0x00000000);
845 OUT_RING(ring
, 0x00000000);
847 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7C5
, 3);
848 OUT_RING(ring
, 0x00000000);
849 OUT_RING(ring
, 0x00000000);
850 OUT_RING(ring
, 0x00000000);
852 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7CA
, 3);
853 OUT_RING(ring
, 0x00000000);
854 OUT_RING(ring
, 0x00000000);
855 OUT_RING(ring
, 0x00000000);
857 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7CF
, 3);
858 OUT_RING(ring
, 0x00000000);
859 OUT_RING(ring
, 0x00000000);
860 OUT_RING(ring
, 0x00000000);
862 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7D4
, 3);
863 OUT_RING(ring
, 0x00000000);
864 OUT_RING(ring
, 0x00000000);
865 OUT_RING(ring
, 0x00000000);
867 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7D9
, 3);
868 OUT_RING(ring
, 0x00000000);
869 OUT_RING(ring
, 0x00000000);
870 OUT_RING(ring
, 0x00000000);
872 // TODO hacks.. these should not be hardcoded:
873 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_CNTL
, 1);
874 OUT_RING(ring
, 0x00000008); /* GRAS_SC_CNTL */
876 fd_hw_query_enable(batch
, ring
);
880 fd5_emit_ib(struct fd_ringbuffer
*ring
, struct fd_ringbuffer
*target
)
882 __OUT_IB5(ring
, target
);
886 fd5_emit_init(struct pipe_context
*pctx
)
888 struct fd_context
*ctx
= fd_context(pctx
);
889 ctx
->emit_const
= fd5_emit_const
;
890 ctx
->emit_const_bo
= fd5_emit_const_bo
;
891 ctx
->emit_ib
= fd5_emit_ib
;