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a5xx: fix integer texture border colors
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd5_emit.h"
38 #include "fd5_blend.h"
39 #include "fd5_context.h"
40 #include "fd5_program.h"
41 #include "fd5_rasterizer.h"
42 #include "fd5_texture.h"
43 #include "fd5_format.h"
44 #include "fd5_zsa.h"
45
46 /* regid: base const register
47 * prsc or dwords: buffer containing constant values
48 * sizedwords: size of const value buffer
49 */
50 static void
51 fd5_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
52 uint32_t regid, uint32_t offset, uint32_t sizedwords,
53 const uint32_t *dwords, struct pipe_resource *prsc)
54 {
55 uint32_t i, sz;
56 enum a4xx_state_src src;
57
58 debug_assert((regid % 4) == 0);
59 debug_assert((sizedwords % 4) == 0);
60
61 if (prsc) {
62 sz = 0;
63 src = SS4_INDIRECT;
64 } else {
65 sz = sizedwords;
66 src = SS4_DIRECT;
67 }
68
69 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sz);
70 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
71 CP_LOAD_STATE4_0_STATE_SRC(src) |
72 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
73 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
74 if (prsc) {
75 struct fd_bo *bo = fd_resource(prsc)->bo;
76 OUT_RELOC(ring, bo, offset,
77 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
78 } else {
79 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
80 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
81 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
82 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
83 }
84 for (i = 0; i < sz; i++) {
85 OUT_RING(ring, dwords[i]);
86 }
87 }
88
89 static void
90 fd5_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
91 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
92 {
93 uint32_t anum = align(num, 2);
94 uint32_t i;
95
96 debug_assert((regid % 4) == 0);
97
98 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * anum));
99 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
100 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
101 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
102 CP_LOAD_STATE4_0_NUM_UNIT(anum/2));
103 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
104 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
105 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
106
107 for (i = 0; i < num; i++) {
108 if (prscs[i]) {
109 if (write) {
110 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
111 } else {
112 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
113 }
114 } else {
115 OUT_RING(ring, 0xbad00000 | (i << 16));
116 OUT_RING(ring, 0xbad00000 | (i << 16));
117 }
118 }
119
120 for (; i < anum; i++) {
121 OUT_RING(ring, 0xffffffff);
122 OUT_RING(ring, 0xffffffff);
123 }
124 }
125
126 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
127 * the same as a6xx then move this somewhere common ;-)
128 *
129 * Entry layout looks like (total size, 0x60 bytes):
130 *
131 * offset | description
132 * -------+-------------
133 * 0x00 | fp32[0]
134 * | fp32[1]
135 * | fp32[2]
136 * | fp32[3]
137 * 0x10 | uint16[0]
138 * | uint16[1]
139 * | uint16[2]
140 * | uint16[3]
141 * 0x18 | int16[0]
142 * | int16[1]
143 * | int16[2]
144 * | int16[3]
145 * 0x20 | fp16[0]
146 * | fp16[1]
147 * | fp16[2]
148 * | fp16[3]
149 * 0x28 | ?? maybe padding ??
150 * 0x30 | uint8[0]
151 * | uint8[1]
152 * | uint8[2]
153 * | uint8[3]
154 * 0x34 | int8[0]
155 * | int8[1]
156 * | int8[2]
157 * | int8[3]
158 * 0x38 | ?? maybe padding ??
159 *
160 * Some uncertainty, because not clear that this actually works properly
161 * with blob, so who knows..
162 */
163
164 struct PACKED bcolor_entry {
165 uint32_t fp32[4];
166 uint16_t ui16[4];
167 int16_t si16[4];
168 uint16_t fp16[4];
169 uint8_t __pad0[8];
170 uint8_t ui8[4];
171 int8_t si8[4];
172 uint8_t __pad1[40];
173 };
174
175 #define FD5_BORDER_COLOR_SIZE 0x60
176 #define FD5_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD5_BORDER_COLOR_SIZE)
177
178 static void
179 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
180 {
181 unsigned i, j;
182
183 for (i = 0; i < tex->num_samplers; i++) {
184 struct bcolor_entry *e = &entries[i];
185 struct pipe_sampler_state *sampler = tex->samplers[i];
186 union pipe_color_union *bc;
187
188 if (!sampler)
189 continue;
190
191 bc = &sampler->border_color;
192
193 /*
194 * XXX HACK ALERT XXX
195 *
196 * The border colors need to be swizzled in a particular
197 * format-dependent order. Even though samplers don't know about
198 * formats, we can assume that with a GL state tracker, there's a
199 * 1:1 correspondence between sampler and texture. Take advantage
200 * of that knowledge.
201 */
202 if ((i >= tex->num_textures) || !tex->textures[i])
203 continue;
204
205 const struct util_format_description *desc =
206 util_format_description(tex->textures[i]->format);
207
208 for (j = 0; j < 4; j++) {
209 int c = desc->swizzle[j];
210
211 if (c >= 4)
212 continue;
213
214 if (desc->channel[c].pure_integer) {
215 e->fp32[j] = bc->ui[c];
216 e->fp16[j] = bc->ui[c];
217 e->ui16[j] = bc->ui[c];
218 e->si16[j] = bc->i[c];
219 e->ui8[j] = bc->ui[c];
220 e->si8[j] = bc->i[c];
221 } else {
222 float f = bc->f[c];
223
224 e->fp32[j] = fui(f);
225 e->fp16[j] = util_float_to_half(f);
226 e->ui16[j] = f * 65535.0;
227 e->si16[j] = f * 32767.5;
228 e->ui8[j] = f * 255.0;
229 e->si8[j] = f * 128.0;
230 }
231 }
232
233 #ifdef DEBUG
234 memset(&e->__pad0, 0, sizeof(e->__pad0));
235 memset(&e->__pad1, 0, sizeof(e->__pad1));
236 #endif
237 }
238 }
239
240 static void
241 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
242 {
243 struct fd5_context *fd5_ctx = fd5_context(ctx);
244 struct bcolor_entry *entries;
245 unsigned off;
246 void *ptr;
247
248 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE);
249
250 u_upload_alloc(fd5_ctx->border_color_uploader,
251 0, FD5_BORDER_COLOR_UPLOAD_SIZE,
252 FD5_BORDER_COLOR_UPLOAD_SIZE, &off,
253 &fd5_ctx->border_color_buf,
254 &ptr);
255
256 entries = ptr;
257
258 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
259 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
260 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
261
262 OUT_PKT4(ring, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
263 OUT_RELOC(ring, fd_resource(fd5_ctx->border_color_buf)->bo, off, 0, 0);
264
265 u_upload_unmap(fd5_ctx->border_color_uploader);
266 }
267
268 static bool
269 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
270 enum a4xx_state_block sb, struct fd_texture_stateobj *tex)
271 {
272 bool needs_border = false;
273 unsigned bcolor_offset = (sb == SB4_FS_TEX) ? ctx->tex[PIPE_SHADER_VERTEX].num_samplers : 0;
274 unsigned i;
275
276 if (tex->num_samplers > 0) {
277 /* output sampler state: */
278 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (4 * tex->num_samplers));
279 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
280 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
281 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
282 CP_LOAD_STATE4_0_NUM_UNIT(tex->num_samplers));
283 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
284 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
285 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
286 for (i = 0; i < tex->num_samplers; i++) {
287 static const struct fd5_sampler_stateobj dummy_sampler = {};
288 const struct fd5_sampler_stateobj *sampler = tex->samplers[i] ?
289 fd5_sampler_stateobj(tex->samplers[i]) :
290 &dummy_sampler;
291 OUT_RING(ring, sampler->texsamp0);
292 OUT_RING(ring, sampler->texsamp1);
293 OUT_RING(ring, sampler->texsamp2 |
294 A5XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset));
295 OUT_RING(ring, sampler->texsamp3);
296
297 needs_border |= sampler->needs_border;
298 }
299 }
300
301 if (tex->num_textures > 0) {
302 unsigned num_textures = tex->num_textures;
303
304 /* emit texture state: */
305 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (12 * num_textures));
306 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
307 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
308 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
309 CP_LOAD_STATE4_0_NUM_UNIT(num_textures));
310 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
311 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
312 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
313 for (i = 0; i < tex->num_textures; i++) {
314 static const struct fd5_pipe_sampler_view dummy_view = {};
315 const struct fd5_pipe_sampler_view *view = tex->textures[i] ?
316 fd5_pipe_sampler_view(tex->textures[i]) :
317 &dummy_view;
318
319 OUT_RING(ring, view->texconst0);
320 OUT_RING(ring, view->texconst1);
321 OUT_RING(ring, view->texconst2);
322 OUT_RING(ring, view->texconst3);
323 if (view->base.texture) {
324 struct fd_resource *rsc = fd_resource(view->base.texture);
325 OUT_RELOC(ring, rsc->bo, view->offset,
326 (uint64_t)view->texconst5 << 32, 0);
327 } else {
328 OUT_RING(ring, 0x00000000);
329 OUT_RING(ring, view->texconst5);
330 }
331 OUT_RING(ring, view->texconst6);
332 OUT_RING(ring, view->texconst7);
333 OUT_RING(ring, view->texconst8);
334 OUT_RING(ring, view->texconst9);
335 OUT_RING(ring, view->texconst10);
336 OUT_RING(ring, view->texconst11);
337 }
338 }
339
340 return needs_border;
341 }
342
343 static void
344 emit_ssbos(struct fd_context *ctx, struct fd_ringbuffer *ring,
345 enum a4xx_state_block sb, struct fd_shaderbuf_stateobj *so)
346 {
347 unsigned count = util_last_bit(so->enabled_mask);
348
349 if (count == 0)
350 return;
351
352 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (4 * count));
353 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
354 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
355 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
356 CP_LOAD_STATE4_0_NUM_UNIT(count));
357 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(0) |
358 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
359 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
360 for (unsigned i = 0; i < count; i++) {
361 struct pipe_shader_buffer *buf = &so->sb[i];
362 if (buf->buffer) {
363 struct fd_resource *rsc = fd_resource(buf->buffer);
364 OUT_RELOCW(ring, rsc->bo, 0, 0, 0);
365 } else {
366 OUT_RING(ring, 0x00000000);
367 OUT_RING(ring, 0x00000000);
368 }
369 OUT_RING(ring, 0x00000000);
370 OUT_RING(ring, 0x00000000);
371 }
372
373 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * count));
374 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
375 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
376 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
377 CP_LOAD_STATE4_0_NUM_UNIT(count));
378 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(1) |
379 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
380 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
381 for (unsigned i = 0; i < count; i++) {
382 struct pipe_shader_buffer *buf = &so->sb[i];
383
384 // TODO maybe offset encoded somewhere here??
385 OUT_RING(ring, (buf->buffer_size << 16));
386 OUT_RING(ring, 0x00000000);
387 }
388
389 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * count));
390 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
391 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
392 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
393 CP_LOAD_STATE4_0_NUM_UNIT(count));
394 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(2) |
395 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
396 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
397 for (unsigned i = 0; i < count; i++) {
398 struct pipe_shader_buffer *buf = &so->sb[i];
399 if (buf->buffer) {
400 struct fd_resource *rsc = fd_resource(buf->buffer);
401 OUT_RELOCW(ring, rsc->bo, 0, 0, 0);
402 } else {
403 OUT_RING(ring, 0x00000000);
404 OUT_RING(ring, 0x00000000);
405 }
406 }
407 }
408
409 void
410 fd5_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd5_emit *emit)
411 {
412 int32_t i, j;
413 const struct fd_vertex_state *vtx = emit->vtx;
414 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
415
416 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
417 if (vp->inputs[i].sysval)
418 continue;
419 if (vp->inputs[i].compmask) {
420 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
421 const struct pipe_vertex_buffer *vb =
422 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
423 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
424 enum pipe_format pfmt = elem->src_format;
425 enum a5xx_vtx_fmt fmt = fd5_pipe2vtx(pfmt);
426 bool isint = util_format_is_pure_integer(pfmt);
427 uint32_t off = vb->buffer_offset + elem->src_offset;
428 uint32_t size = fd_bo_size(rsc->bo) - off;
429 debug_assert(fmt != ~0);
430
431 OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4);
432 OUT_RELOC(ring, rsc->bo, off, 0, 0);
433 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
434 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
435
436 OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2);
437 OUT_RING(ring, A5XX_VFD_DECODE_INSTR_IDX(j) |
438 A5XX_VFD_DECODE_INSTR_FORMAT(fmt) |
439 COND(elem->instance_divisor, A5XX_VFD_DECODE_INSTR_INSTANCED) |
440 A5XX_VFD_DECODE_INSTR_SWAP(fd5_pipe2swap(pfmt)) |
441 A5XX_VFD_DECODE_INSTR_UNK30 |
442 COND(!isint, A5XX_VFD_DECODE_INSTR_FLOAT));
443 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
444
445 OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1);
446 OUT_RING(ring, A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
447 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
448
449 j++;
450 }
451 }
452
453 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1);
454 OUT_RING(ring, A5XX_VFD_CONTROL_0_VTXCNT(j));
455 }
456
457 void
458 fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
459 struct fd5_emit *emit)
460 {
461 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
462 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
463 const struct ir3_shader_variant *fp = fd5_emit_get_fp(emit);
464 const enum fd_dirty_3d_state dirty = emit->dirty;
465 bool needs_border = false;
466
467 emit_marker5(ring, 5);
468
469 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
470 unsigned char mrt_comp[A5XX_MAX_RENDER_TARGETS] = {0};
471
472 for (unsigned i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
473 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
474 }
475
476 OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1);
477 OUT_RING(ring, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
478 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
479 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
480 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
481 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
482 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
483 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
484 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
485 }
486
487 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
488 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
489 uint32_t rb_alpha_control = zsa->rb_alpha_control;
490
491 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
492 rb_alpha_control &= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST;
493
494 OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1);
495 OUT_RING(ring, rb_alpha_control);
496
497 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1);
498 OUT_RING(ring, zsa->rb_stencil_control);
499 }
500
501 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG)) {
502 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
503 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
504
505 if (pfb->zsbuf) {
506 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
507 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
508
509 if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid)
510 gras_lrz_cntl = 0;
511 else if (emit->key.binning_pass && blend->lrz_write && zsa->lrz_write)
512 gras_lrz_cntl |= A5XX_GRAS_LRZ_CNTL_LRZ_WRITE;
513
514 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
515 OUT_RING(ring, gras_lrz_cntl);
516 }
517 }
518
519 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
520 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
521 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
522
523 OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 2);
524 OUT_RING(ring, zsa->rb_stencilrefmask |
525 A5XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
526 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
527 A5XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
528 }
529
530 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
531 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
532 bool fragz = fp->has_kill | fp->writes_pos;
533
534 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_CNTL, 1);
535 OUT_RING(ring, zsa->rb_depth_cntl);
536
537 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_PLANE_CNTL, 1);
538 OUT_RING(ring, COND(fragz, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
539 COND(fragz && fp->frag_coord, A5XX_RB_DEPTH_PLANE_CNTL_UNK1));
540
541 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
542 OUT_RING(ring, COND(fragz, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
543 COND(fragz && fp->frag_coord, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1));
544 }
545
546 if (dirty & FD_DIRTY_SCISSOR) {
547 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
548
549 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
550 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
551 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
552 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
553 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
554
555 OUT_PKT4(ring, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
556 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
557 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
558 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
559 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
560
561 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
562 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
563 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
564 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
565 }
566
567 if (dirty & FD_DIRTY_VIEWPORT) {
568 fd_wfi(ctx->batch, ring);
569 OUT_PKT4(ring, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0, 6);
570 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
571 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
572 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
573 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
574 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
575 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
576 }
577
578 if (dirty & FD_DIRTY_PROG)
579 fd5_program_emit(ctx, ring, emit);
580
581 if (dirty & FD_DIRTY_RASTERIZER) {
582 struct fd5_rasterizer_stateobj *rasterizer =
583 fd5_rasterizer_stateobj(ctx->rasterizer);
584
585 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
586 OUT_RING(ring, rasterizer->gras_su_cntl);
587
588 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
589 OUT_RING(ring, rasterizer->gras_su_point_minmax);
590 OUT_RING(ring, rasterizer->gras_su_point_size);
591
592 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
593 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
594 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
595 OUT_RING(ring, rasterizer->gras_su_poly_offset_clamp);
596
597 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
598 OUT_RING(ring, rasterizer->pc_raster_cntl);
599
600 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
601 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
602 }
603
604 /* note: must come after program emit.. because there is some overlap
605 * in registers, ex. PC_PRIMITIVE_CNTL and we rely on some cached
606 * values from fd5_program_emit() to avoid having to re-emit the prog
607 * every time rast state changes.
608 *
609 * Since the primitive restart state is not part of a tracked object, we
610 * re-emit this register every time.
611 */
612 if (emit->info && ctx->rasterizer) {
613 struct fd5_rasterizer_stateobj *rasterizer =
614 fd5_rasterizer_stateobj(ctx->rasterizer);
615 unsigned max_loc = fd5_context(ctx)->max_loc;
616
617 OUT_PKT4(ring, REG_A5XX_PC_PRIMITIVE_CNTL, 1);
618 OUT_RING(ring, rasterizer->pc_primitive_cntl |
619 A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(max_loc) |
620 COND(emit->info->primitive_restart && emit->info->index_size,
621 A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART));
622 }
623
624 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER)) {
625 uint32_t posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
626 unsigned nr = pfb->nr_cbufs;
627
628 if (emit->key.binning_pass)
629 nr = 0;
630 else if (ctx->rasterizer->rasterizer_discard)
631 nr = 0;
632
633 OUT_PKT4(ring, REG_A5XX_RB_FS_OUTPUT_CNTL, 1);
634 OUT_RING(ring, A5XX_RB_FS_OUTPUT_CNTL_MRT(nr) |
635 COND(fp->writes_pos, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z));
636
637 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_CNTL, 1);
638 OUT_RING(ring, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr) |
639 A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid) |
640 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
641 }
642
643 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
644 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
645 if (!emit->key.binning_pass)
646 ir3_emit_fs_consts(fp, ring, ctx);
647
648 struct pipe_stream_output_info *info = &vp->shader->stream_output;
649 if (info->num_outputs) {
650 struct fd_streamout_stateobj *so = &ctx->streamout;
651
652 for (unsigned i = 0; i < so->num_targets; i++) {
653 struct pipe_stream_output_target *target = so->targets[i];
654
655 if (!target)
656 continue;
657
658 unsigned offset = (so->offsets[i] * info->stride[i] * 4) +
659 target->buffer_offset;
660
661 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(i), 3);
662 /* VPC_SO[i].BUFFER_BASE_LO: */
663 OUT_RELOCW(ring, fd_resource(target->buffer)->bo, 0, 0, 0);
664 OUT_RING(ring, target->buffer_size + offset);
665
666 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(i), 3);
667 OUT_RING(ring, offset);
668 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
669 // TODO just give hw a dummy addr for now.. we should
670 // be using this an then CP_MEM_TO_REG to set the
671 // VPC_SO[i].BUFFER_OFFSET for the next draw..
672 OUT_RELOCW(ring, fd5_context(ctx)->blit_mem, 0x100, 0, 0);
673
674 emit->streamout_mask |= (1 << i);
675 }
676 }
677 }
678
679 if ((dirty & FD_DIRTY_BLEND)) {
680 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
681 uint32_t i;
682
683 for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
684 enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
685 bool is_int = util_format_is_pure_integer(format);
686 bool has_alpha = util_format_has_alpha(format);
687 uint32_t control = blend->rb_mrt[i].control;
688 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
689
690 if (is_int) {
691 control &= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
692 control |= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
693 }
694
695 if (has_alpha) {
696 blend_control |= blend->rb_mrt[i].blend_control_rgb;
697 } else {
698 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
699 control &= ~A5XX_RB_MRT_CONTROL_BLEND2;
700 }
701
702 OUT_PKT4(ring, REG_A5XX_RB_MRT_CONTROL(i), 1);
703 OUT_RING(ring, control);
704
705 OUT_PKT4(ring, REG_A5XX_RB_MRT_BLEND_CONTROL(i), 1);
706 OUT_RING(ring, blend_control);
707 }
708
709 OUT_PKT4(ring, REG_A5XX_RB_BLEND_CNTL, 1);
710 OUT_RING(ring, blend->rb_blend_cntl |
711 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(0xffff));
712
713 OUT_PKT4(ring, REG_A5XX_SP_BLEND_CNTL, 1);
714 OUT_RING(ring, blend->sp_blend_cntl);
715 }
716
717 if (dirty & FD_DIRTY_BLEND_COLOR) {
718 struct pipe_blend_color *bcolor = &ctx->blend_color;
719
720 OUT_PKT4(ring, REG_A5XX_RB_BLEND_RED, 8);
721 OUT_RING(ring, A5XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
722 A5XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
723 A5XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
724 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[0]));
725 OUT_RING(ring, A5XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
726 A5XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
727 A5XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
728 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[1]));
729 OUT_RING(ring, A5XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
730 A5XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
731 A5XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
732 OUT_RING(ring, A5XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
733 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
734 A5XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
735 A5XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
736 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
737 }
738
739 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX) {
740 needs_border |= emit_textures(ctx, ring, SB4_VS_TEX,
741 &ctx->tex[PIPE_SHADER_VERTEX]);
742 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
743 OUT_RING(ring, ctx->tex[PIPE_SHADER_VERTEX].num_textures);
744 }
745
746 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX) {
747 needs_border |= emit_textures(ctx, ring, SB4_FS_TEX,
748 &ctx->tex[PIPE_SHADER_FRAGMENT]);
749 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
750 OUT_RING(ring, ctx->tex[PIPE_SHADER_FRAGMENT].num_textures);
751 }
752
753 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
754 OUT_RING(ring, 0);
755
756 if (needs_border)
757 emit_border_color(ctx, ring);
758
759 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_SSBO)
760 emit_ssbos(ctx, ring, SB4_SSBO, &ctx->shaderbuf[PIPE_SHADER_FRAGMENT]);
761 }
762
763 void
764 fd5_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
765 struct ir3_shader_variant *cp)
766 {
767 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
768
769 if (dirty & FD_DIRTY_SHADER_TEX) {
770 bool needs_border = false;
771 needs_border |= emit_textures(ctx, ring, SB4_CS_TEX,
772 &ctx->tex[PIPE_SHADER_COMPUTE]);
773
774 if (needs_border)
775 emit_border_color(ctx, ring);
776
777 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
778 OUT_RING(ring, 0);
779
780 OUT_PKT4(ring, REG_A5XX_TPL1_HS_TEX_COUNT, 1);
781 OUT_RING(ring, 0);
782
783 OUT_PKT4(ring, REG_A5XX_TPL1_DS_TEX_COUNT, 1);
784 OUT_RING(ring, 0);
785
786 OUT_PKT4(ring, REG_A5XX_TPL1_GS_TEX_COUNT, 1);
787 OUT_RING(ring, 0);
788
789 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
790 OUT_RING(ring, 0);
791
792 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
793 OUT_RING(ring, ctx->tex[PIPE_SHADER_COMPUTE].num_textures);
794 }
795
796 if (dirty & FD_DIRTY_SHADER_SSBO)
797 emit_ssbos(ctx, ring, SB4_CS_SSBO, &ctx->shaderbuf[PIPE_SHADER_COMPUTE]);
798 }
799
800 /* emit setup at begin of new cmdstream buffer (don't rely on previous
801 * state, there could have been a context switch between ioctls):
802 */
803 void
804 fd5_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
805 {
806 struct fd_context *ctx = batch->ctx;
807
808 fd5_set_render_mode(ctx, ring, BYPASS);
809 fd5_cache_flush(batch, ring);
810
811 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
812 OUT_RING(ring, 0xfffff);
813
814 /*
815 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
816 0000000500024048: 70d08003 00000000 001c5000 00000005
817 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
818 0000000500024058: 70d08003 00000010 001c7000 00000005
819
820 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
821 0000000500024068: 70268000
822 */
823
824 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
825 OUT_RING(ring, 0xffffffff);
826
827 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
828 OUT_RING(ring, 0x00000012);
829
830 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
831 OUT_RING(ring, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
832 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
833 OUT_RING(ring, A5XX_GRAS_SU_POINT_SIZE(0.5));
834
835 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
836 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
837
838 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL, 1);
839 OUT_RING(ring, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */
840
841 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG_MAX_CONST, 1);
842 OUT_RING(ring, 0); /* SP_VS_CONFIG_MAX_CONST */
843
844 OUT_PKT4(ring, REG_A5XX_SP_FS_CONFIG_MAX_CONST, 1);
845 OUT_RING(ring, 0); /* SP_FS_CONFIG_MAX_CONST */
846
847 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E292, 2);
848 OUT_RING(ring, 0x00000000); /* UNKNOWN_E292 */
849 OUT_RING(ring, 0x00000000); /* UNKNOWN_E293 */
850
851 OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1);
852 OUT_RING(ring, 0x00000044); /* RB_MODE_CNTL */
853
854 OUT_PKT4(ring, REG_A5XX_RB_DBG_ECO_CNTL, 1);
855 OUT_RING(ring, 0x00100000); /* RB_DBG_ECO_CNTL */
856
857 OUT_PKT4(ring, REG_A5XX_VFD_MODE_CNTL, 1);
858 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
859
860 OUT_PKT4(ring, REG_A5XX_PC_MODE_CNTL, 1);
861 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
862
863 OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1);
864 OUT_RING(ring, 0x0000001e); /* SP_MODE_CNTL */
865
866 OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
867 OUT_RING(ring, 0x40000800); /* SP_DBG_ECO_CNTL */
868
869 OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1);
870 OUT_RING(ring, 0x00000544); /* TPL1_MODE_CNTL */
871
872 OUT_PKT4(ring, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0, 2);
873 OUT_RING(ring, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */
874 OUT_RING(ring, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */
875
876 OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);
877 OUT_RING(ring, 0x00000400); /* VPC_DBG_ECO_CNTL */
878
879 OUT_PKT4(ring, REG_A5XX_HLSQ_MODE_CNTL, 1);
880 OUT_RING(ring, 0x00000001); /* HLSQ_MODE_CNTL */
881
882 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
883 OUT_RING(ring, 0x00000000); /* VPC_MODE_CNTL */
884
885 /* we don't use this yet.. probably best to disable.. */
886 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
887 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
888 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
889 CP_SET_DRAW_STATE__0_GROUP_ID(0));
890 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
891 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
892
893 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
894 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
895
896 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
897 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
898
899 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
900 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
901
902 OUT_PKT4(ring, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL, 1);
903 OUT_RING(ring, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */
904
905 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
906 OUT_RING(ring, A5XX_VPC_SO_OVERRIDE_SO_DISABLE);
907
908 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(0), 3);
909 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
910 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
911 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
912
913 OUT_PKT4(ring, REG_A5XX_VPC_SO_FLUSH_BASE_LO(0), 2);
914 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
915 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
916
917 OUT_PKT4(ring, REG_A5XX_PC_GS_PARAM, 1);
918 OUT_RING(ring, 0x00000000); /* PC_GS_PARAM */
919
920 OUT_PKT4(ring, REG_A5XX_PC_HS_PARAM, 1);
921 OUT_RING(ring, 0x00000000); /* PC_HS_PARAM */
922
923 OUT_PKT4(ring, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL, 1);
924 OUT_RING(ring, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */
925
926 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E001, 1);
927 OUT_RING(ring, 0x00000000); /* UNKNOWN_E001 */
928
929 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E004, 1);
930 OUT_RING(ring, 0x00000000); /* UNKNOWN_E004 */
931
932 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E093, 1);
933 OUT_RING(ring, 0x00000000); /* UNKNOWN_E093 */
934
935 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E29A, 1);
936 OUT_RING(ring, 0x00ffff00); /* UNKNOWN_E29A */
937
938 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUF_CNTL, 1);
939 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
940
941 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(0), 1);
942 OUT_RING(ring, 0x00000000); /* UNKNOWN_E2AB */
943
944 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E389, 1);
945 OUT_RING(ring, 0x00000000); /* UNKNOWN_E389 */
946
947 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E38D, 1);
948 OUT_RING(ring, 0x00000000); /* UNKNOWN_E38D */
949
950 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5AB, 1);
951 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5AB */
952
953 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5C2, 1);
954 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5C2 */
955
956 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(1), 3);
957 OUT_RING(ring, 0x00000000);
958 OUT_RING(ring, 0x00000000);
959 OUT_RING(ring, 0x00000000);
960
961 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(1), 6);
962 OUT_RING(ring, 0x00000000);
963 OUT_RING(ring, 0x00000000);
964 OUT_RING(ring, 0x00000000);
965 OUT_RING(ring, 0x00000000);
966 OUT_RING(ring, 0x00000000);
967 OUT_RING(ring, 0x00000000);
968
969 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(2), 6);
970 OUT_RING(ring, 0x00000000);
971 OUT_RING(ring, 0x00000000);
972 OUT_RING(ring, 0x00000000);
973 OUT_RING(ring, 0x00000000);
974 OUT_RING(ring, 0x00000000);
975 OUT_RING(ring, 0x00000000);
976
977 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(3), 3);
978 OUT_RING(ring, 0x00000000);
979 OUT_RING(ring, 0x00000000);
980 OUT_RING(ring, 0x00000000);
981
982 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5DB, 1);
983 OUT_RING(ring, 0x00000000);
984
985 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E600, 1);
986 OUT_RING(ring, 0x00000000);
987
988 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E640, 1);
989 OUT_RING(ring, 0x00000000);
990
991 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 4);
992 OUT_RING(ring, 0x00000000);
993 OUT_RING(ring, 0x00000000);
994 OUT_RING(ring, 0x00000000);
995 OUT_RING(ring, 0x00000000);
996
997 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 2);
998 OUT_RING(ring, 0x00000000);
999 OUT_RING(ring, 0x00000000);
1000
1001 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C0, 3);
1002 OUT_RING(ring, 0x00000000);
1003 OUT_RING(ring, 0x00000000);
1004 OUT_RING(ring, 0x00000000);
1005
1006 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C5, 3);
1007 OUT_RING(ring, 0x00000000);
1008 OUT_RING(ring, 0x00000000);
1009 OUT_RING(ring, 0x00000000);
1010
1011 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CA, 3);
1012 OUT_RING(ring, 0x00000000);
1013 OUT_RING(ring, 0x00000000);
1014 OUT_RING(ring, 0x00000000);
1015
1016 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CF, 3);
1017 OUT_RING(ring, 0x00000000);
1018 OUT_RING(ring, 0x00000000);
1019 OUT_RING(ring, 0x00000000);
1020
1021 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D4, 3);
1022 OUT_RING(ring, 0x00000000);
1023 OUT_RING(ring, 0x00000000);
1024 OUT_RING(ring, 0x00000000);
1025
1026 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D9, 3);
1027 OUT_RING(ring, 0x00000000);
1028 OUT_RING(ring, 0x00000000);
1029 OUT_RING(ring, 0x00000000);
1030 }
1031
1032 static void
1033 fd5_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
1034 {
1035 __OUT_IB5(ring, target);
1036 }
1037
1038 void
1039 fd5_emit_init(struct pipe_context *pctx)
1040 {
1041 struct fd_context *ctx = fd_context(pctx);
1042 ctx->emit_const = fd5_emit_const;
1043 ctx->emit_const_bo = fd5_emit_const_bo;
1044 ctx->emit_ib = fd5_emit_ib;
1045 }