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gallium: decrease the size of pipe_vertex_buffer - 24 -> 16 bytes
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd5_emit.h"
38 #include "fd5_blend.h"
39 #include "fd5_context.h"
40 #include "fd5_program.h"
41 #include "fd5_rasterizer.h"
42 #include "fd5_texture.h"
43 #include "fd5_format.h"
44 #include "fd5_zsa.h"
45
46 /* regid: base const register
47 * prsc or dwords: buffer containing constant values
48 * sizedwords: size of const value buffer
49 */
50 static void
51 fd5_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
52 uint32_t regid, uint32_t offset, uint32_t sizedwords,
53 const uint32_t *dwords, struct pipe_resource *prsc)
54 {
55 uint32_t i, sz;
56 enum a4xx_state_src src;
57
58 debug_assert((regid % 4) == 0);
59 debug_assert((sizedwords % 4) == 0);
60
61 if (prsc) {
62 sz = 0;
63 src = SS4_INDIRECT;
64 } else {
65 sz = sizedwords;
66 src = SS4_DIRECT;
67 }
68
69 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sz);
70 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
71 CP_LOAD_STATE4_0_STATE_SRC(src) |
72 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
73 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
74 if (prsc) {
75 struct fd_bo *bo = fd_resource(prsc)->bo;
76 OUT_RELOC(ring, bo, offset,
77 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
78 } else {
79 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
80 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
81 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
82 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
83 }
84 for (i = 0; i < sz; i++) {
85 OUT_RING(ring, dwords[i]);
86 }
87 }
88
89 static void
90 fd5_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
91 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
92 {
93 uint32_t anum = align(num, 2);
94 uint32_t i;
95
96 debug_assert((regid % 4) == 0);
97
98 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * anum));
99 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
100 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
101 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
102 CP_LOAD_STATE4_0_NUM_UNIT(anum/2));
103 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
104 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
105 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
106
107 for (i = 0; i < num; i++) {
108 if (prscs[i]) {
109 if (write) {
110 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
111 } else {
112 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
113 }
114 } else {
115 OUT_RING(ring, 0xbad00000 | (i << 16));
116 OUT_RING(ring, 0xbad00000 | (i << 16));
117 }
118 }
119
120 for (; i < anum; i++) {
121 OUT_RING(ring, 0xffffffff);
122 OUT_RING(ring, 0xffffffff);
123 }
124 }
125
126 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
127 * the same as a6xx then move this somewhere common ;-)
128 *
129 * Entry layout looks like (total size, 0x60 bytes):
130 *
131 * offset | description
132 * -------+-------------
133 * 0x00 | fp32[0]
134 * | fp32[1]
135 * | fp32[2]
136 * | fp32[3]
137 * 0x10 | uint16[0]
138 * | uint16[1]
139 * | uint16[2]
140 * | uint16[3]
141 * 0x18 | int16[0]
142 * | int16[1]
143 * | int16[2]
144 * | int16[3]
145 * 0x20 | fp16[0]
146 * | fp16[1]
147 * | fp16[2]
148 * | fp16[3]
149 * 0x28 | ?? maybe padding ??
150 * 0x30 | uint8[0]
151 * | uint8[1]
152 * | uint8[2]
153 * | uint8[3]
154 * 0x34 | int8[0]
155 * | int8[1]
156 * | int8[2]
157 * | int8[3]
158 * 0x38 | ?? maybe padding ??
159 *
160 * Some uncertainty, because not clear that this actually works properly
161 * with blob, so who knows..
162 */
163
164 struct PACKED bcolor_entry {
165 uint32_t fp32[4];
166 uint16_t ui16[4];
167 int16_t si16[4];
168 uint16_t fp16[4];
169 uint8_t __pad0[8];
170 uint8_t ui8[4];
171 int8_t si8[4];
172 uint8_t __pad1[40];
173 };
174
175 #define FD5_BORDER_COLOR_SIZE 0x60
176 #define FD5_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD5_BORDER_COLOR_SIZE)
177 #define FD5_BORDER_COLOR_OFFSET 8 /* TODO probably should be dynamic */
178
179 static void
180 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
181 {
182 unsigned i, j;
183
184 debug_assert(tex->num_samplers < FD5_BORDER_COLOR_OFFSET); // TODO
185
186 for (i = 0; i < tex->num_samplers; i++) {
187 struct bcolor_entry *e = &entries[i];
188 struct pipe_sampler_state *sampler = tex->samplers[i];
189 union pipe_color_union *bc;
190
191 if (!sampler)
192 continue;
193
194 bc = &sampler->border_color;
195
196 /*
197 * XXX HACK ALERT XXX
198 *
199 * The border colors need to be swizzled in a particular
200 * format-dependent order. Even though samplers don't know about
201 * formats, we can assume that with a GL state tracker, there's a
202 * 1:1 correspondence between sampler and texture. Take advantage
203 * of that knowledge.
204 */
205 if ((i >= tex->num_textures) || !tex->textures[i])
206 continue;
207
208 const struct util_format_description *desc =
209 util_format_description(tex->textures[i]->format);
210
211 for (j = 0; j < 4; j++) {
212 int c = desc->swizzle[j];
213
214 if (c >= 4)
215 continue;
216
217 if (desc->channel[c].pure_integer) {
218 float f = bc->i[c];
219
220 e->fp32[j] = fui(f);
221 e->fp16[j] = util_float_to_half(f);
222 e->ui16[j] = bc->ui[c];
223 e->si16[j] = bc->i[c];
224 e->ui8[j] = bc->ui[c];
225 e->si8[j] = bc->i[c];
226 } else {
227 float f = bc->f[c];
228
229 e->fp32[j] = fui(f);
230 e->fp16[j] = util_float_to_half(f);
231 e->ui16[j] = f * 65535.0;
232 e->si16[j] = f * 32767.5;
233 e->ui8[j] = f * 255.0;
234 e->si8[j] = f * 128.0;
235 }
236 }
237
238 #ifdef DEBUG
239 memset(&e->__pad0, 0, sizeof(e->__pad0));
240 memset(&e->__pad1, 0, sizeof(e->__pad1));
241 #endif
242 }
243 }
244
245 static void
246 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
247 {
248 struct fd5_context *fd5_ctx = fd5_context(ctx);
249 struct bcolor_entry *entries;
250 unsigned off;
251 void *ptr;
252
253 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE);
254
255 u_upload_alloc(fd5_ctx->border_color_uploader,
256 0, FD5_BORDER_COLOR_UPLOAD_SIZE,
257 FD5_BORDER_COLOR_UPLOAD_SIZE, &off,
258 &fd5_ctx->border_color_buf,
259 &ptr);
260
261 entries = ptr;
262
263 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
264 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
265 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
266
267 OUT_PKT4(ring, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
268 OUT_RELOC(ring, fd_resource(fd5_ctx->border_color_buf)->bo, off, 0, 0);
269
270 u_upload_unmap(fd5_ctx->border_color_uploader);
271 }
272
273 static bool
274 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
275 enum a4xx_state_block sb, struct fd_texture_stateobj *tex)
276 {
277 bool needs_border = false;
278 unsigned bcolor_offset = (sb == SB4_FS_TEX) ? ctx->tex[PIPE_SHADER_VERTEX].num_samplers : 0;
279 unsigned i;
280
281 if (tex->num_samplers > 0) {
282 /* output sampler state: */
283 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (4 * tex->num_samplers));
284 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
285 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
286 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
287 CP_LOAD_STATE4_0_NUM_UNIT(tex->num_samplers));
288 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
289 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
290 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
291 for (i = 0; i < tex->num_samplers; i++) {
292 static const struct fd5_sampler_stateobj dummy_sampler = {};
293 const struct fd5_sampler_stateobj *sampler = tex->samplers[i] ?
294 fd5_sampler_stateobj(tex->samplers[i]) :
295 &dummy_sampler;
296 OUT_RING(ring, sampler->texsamp0);
297 OUT_RING(ring, sampler->texsamp1);
298 OUT_RING(ring, sampler->texsamp2 |
299 A5XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset));
300 OUT_RING(ring, sampler->texsamp3);
301
302 needs_border |= sampler->needs_border;
303 }
304 }
305
306 if (tex->num_textures > 0) {
307 unsigned num_textures = tex->num_textures;
308
309 /* emit texture state: */
310 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (12 * num_textures));
311 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
312 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
313 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
314 CP_LOAD_STATE4_0_NUM_UNIT(num_textures));
315 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
316 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
317 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
318 for (i = 0; i < tex->num_textures; i++) {
319 static const struct fd5_pipe_sampler_view dummy_view = {};
320 const struct fd5_pipe_sampler_view *view = tex->textures[i] ?
321 fd5_pipe_sampler_view(tex->textures[i]) :
322 &dummy_view;
323
324 OUT_RING(ring, view->texconst0);
325 OUT_RING(ring, view->texconst1);
326 OUT_RING(ring, view->texconst2);
327 OUT_RING(ring, view->texconst3);
328 if (view->base.texture) {
329 struct fd_resource *rsc = fd_resource(view->base.texture);
330 OUT_RELOC(ring, rsc->bo, view->offset,
331 (uint64_t)view->texconst5 << 32, 0);
332 } else {
333 OUT_RING(ring, 0x00000000);
334 OUT_RING(ring, view->texconst5);
335 }
336 OUT_RING(ring, view->texconst6);
337 OUT_RING(ring, view->texconst7);
338 OUT_RING(ring, view->texconst8);
339 OUT_RING(ring, view->texconst9);
340 OUT_RING(ring, view->texconst10);
341 OUT_RING(ring, view->texconst11);
342 }
343 }
344
345 return needs_border;
346 }
347
348 static void
349 emit_ssbos(struct fd_context *ctx, struct fd_ringbuffer *ring,
350 enum a4xx_state_block sb, struct fd_shaderbuf_stateobj *so)
351 {
352 unsigned count = util_last_bit(so->enabled_mask);
353
354 if (count == 0)
355 return;
356
357 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (4 * count));
358 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
359 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
360 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
361 CP_LOAD_STATE4_0_NUM_UNIT(count));
362 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(0) |
363 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
364 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
365 for (unsigned i = 0; i < count; i++) {
366 struct pipe_shader_buffer *buf = &so->sb[i];
367 if (buf->buffer) {
368 struct fd_resource *rsc = fd_resource(buf->buffer);
369 OUT_RELOCW(ring, rsc->bo, 0, 0, 0);
370 } else {
371 OUT_RING(ring, 0x00000000);
372 OUT_RING(ring, 0x00000000);
373 }
374 OUT_RING(ring, 0x00000000);
375 OUT_RING(ring, 0x00000000);
376 }
377
378 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * count));
379 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
380 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
381 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
382 CP_LOAD_STATE4_0_NUM_UNIT(count));
383 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(1) |
384 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
385 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
386 for (unsigned i = 0; i < count; i++) {
387 struct pipe_shader_buffer *buf = &so->sb[i];
388
389 // TODO maybe offset encoded somewhere here??
390 OUT_RING(ring, (buf->buffer_size << 16));
391 OUT_RING(ring, 0x00000000);
392 }
393
394 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * count));
395 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
396 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
397 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
398 CP_LOAD_STATE4_0_NUM_UNIT(count));
399 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(2) |
400 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
401 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
402 for (unsigned i = 0; i < count; i++) {
403 struct pipe_shader_buffer *buf = &so->sb[i];
404 if (buf->buffer) {
405 struct fd_resource *rsc = fd_resource(buf->buffer);
406 OUT_RELOCW(ring, rsc->bo, 0, 0, 0);
407 } else {
408 OUT_RING(ring, 0x00000000);
409 OUT_RING(ring, 0x00000000);
410 }
411 }
412 }
413
414 void
415 fd5_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd5_emit *emit)
416 {
417 int32_t i, j;
418 const struct fd_vertex_state *vtx = emit->vtx;
419 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
420
421 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
422 if (vp->inputs[i].sysval)
423 continue;
424 if (vp->inputs[i].compmask) {
425 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
426 const struct pipe_vertex_buffer *vb =
427 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
428 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
429 enum pipe_format pfmt = elem->src_format;
430 enum a5xx_vtx_fmt fmt = fd5_pipe2vtx(pfmt);
431 bool isint = util_format_is_pure_integer(pfmt);
432 uint32_t off = vb->buffer_offset + elem->src_offset;
433 uint32_t size = fd_bo_size(rsc->bo) - off;
434 debug_assert(fmt != ~0);
435
436 OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4);
437 OUT_RELOC(ring, rsc->bo, off, 0, 0);
438 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
439 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
440
441 OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2);
442 OUT_RING(ring, A5XX_VFD_DECODE_INSTR_IDX(j) |
443 A5XX_VFD_DECODE_INSTR_FORMAT(fmt) |
444 COND(elem->instance_divisor, A5XX_VFD_DECODE_INSTR_INSTANCED) |
445 A5XX_VFD_DECODE_INSTR_UNK30 |
446 COND(!isint, A5XX_VFD_DECODE_INSTR_FLOAT));
447 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
448
449 OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1);
450 OUT_RING(ring, A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
451 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
452
453 j++;
454 }
455 }
456
457 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1);
458 OUT_RING(ring, A5XX_VFD_CONTROL_0_VTXCNT(j));
459 }
460
461 void
462 fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
463 struct fd5_emit *emit)
464 {
465 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
466 const struct ir3_shader_variant *fp = fd5_emit_get_fp(emit);
467 const enum fd_dirty_3d_state dirty = emit->dirty;
468 bool needs_border = false;
469
470 emit_marker5(ring, 5);
471
472 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
473 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
474 unsigned char mrt_comp[A5XX_MAX_RENDER_TARGETS] = {0};
475
476 for (unsigned i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
477 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
478 }
479
480 OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1);
481 OUT_RING(ring, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
482 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
483 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
484 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
485 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
486 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
487 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
488 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
489 }
490
491 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
492 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
493 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
494 uint32_t rb_alpha_control = zsa->rb_alpha_control;
495
496 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
497 rb_alpha_control &= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST;
498
499 OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1);
500 OUT_RING(ring, rb_alpha_control);
501
502 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1);
503 OUT_RING(ring, zsa->rb_stencil_control);
504 }
505
506 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
507 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
508 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
509
510 OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 1);
511 OUT_RING(ring, zsa->rb_stencilrefmask |
512 A5XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
513 }
514
515 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
516 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
517 bool fragz = fp->has_kill | fp->writes_pos;
518
519 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_CNTL, 1);
520 OUT_RING(ring, zsa->rb_depth_cntl);
521
522 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_PLANE_CNTL, 1);
523 OUT_RING(ring, COND(fragz, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
524 COND(fragz && fp->frag_coord, A5XX_RB_DEPTH_PLANE_CNTL_UNK1));
525
526 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
527 OUT_RING(ring, COND(fragz, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
528 COND(fragz && fp->frag_coord, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1));
529 }
530
531 if (dirty & FD_DIRTY_RASTERIZER) {
532 struct fd5_rasterizer_stateobj *rasterizer =
533 fd5_rasterizer_stateobj(ctx->rasterizer);
534
535 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
536 OUT_RING(ring, rasterizer->gras_su_cntl);
537
538 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
539 OUT_RING(ring, rasterizer->gras_su_point_minmax);
540 OUT_RING(ring, rasterizer->gras_su_point_size);
541
542 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
543 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
544 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
545 OUT_RING(ring, rasterizer->gras_su_poly_offset_clamp);
546 }
547
548 /* NOTE: since primitive_restart is not actually part of any
549 * state object, we need to make sure that we always emit
550 * PRIM_VTX_CNTL.. either that or be more clever and detect
551 * when it changes.
552 */
553 if (emit->info) {
554 struct fd5_rasterizer_stateobj *rast =
555 fd5_rasterizer_stateobj(ctx->rasterizer);
556 uint32_t val = rast->pc_prim_vtx_cntl;
557
558 val |= COND(vp->writes_psize, A5XX_PC_PRIM_VTX_CNTL_PSIZE);
559
560 OUT_PKT4(ring, REG_A5XX_PC_PRIM_VTX_CNTL, 1);
561 OUT_RING(ring, val);
562 }
563
564 if (dirty & FD_DIRTY_SCISSOR) {
565 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
566
567 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
568 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
569 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
570 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
571 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
572
573 OUT_PKT4(ring, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
574 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
575 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
576 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
577 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
578
579 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
580 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
581 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
582 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
583 }
584
585 if (dirty & FD_DIRTY_VIEWPORT) {
586 fd_wfi(ctx->batch, ring);
587 OUT_PKT4(ring, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0, 6);
588 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
589 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
590 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
591 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
592 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
593 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
594 }
595
596 if (dirty & FD_DIRTY_PROG)
597 fd5_program_emit(ring, emit);
598
599 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER)) {
600 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
601 uint32_t posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
602 unsigned nr = pfb->nr_cbufs;
603
604 if (emit->key.binning_pass)
605 nr = 0;
606 else if (ctx->rasterizer->rasterizer_discard)
607 nr = 0;
608
609 OUT_PKT4(ring, REG_A5XX_RB_FS_OUTPUT_CNTL, 1);
610 OUT_RING(ring, A5XX_RB_FS_OUTPUT_CNTL_MRT(nr) |
611 COND(fp->writes_pos, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z));
612
613 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_CNTL, 1);
614 OUT_RING(ring, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr) |
615 A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid) |
616 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
617 }
618
619 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
620 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
621 if (!emit->key.binning_pass)
622 ir3_emit_fs_consts(fp, ring, ctx);
623
624 struct pipe_stream_output_info *info = &vp->shader->stream_output;
625 if (info->num_outputs) {
626 struct fd_streamout_stateobj *so = &ctx->streamout;
627
628 for (unsigned i = 0; i < so->num_targets; i++) {
629 struct pipe_stream_output_target *target = so->targets[i];
630
631 if (!target)
632 continue;
633
634 unsigned offset = (so->offsets[i] * info->stride[i] * 4) +
635 target->buffer_offset;
636
637 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(i), 3);
638 /* VPC_SO[i].BUFFER_BASE_LO: */
639 OUT_RELOCW(ring, fd_resource(target->buffer)->bo, 0, 0, 0);
640 OUT_RING(ring, target->buffer_size + offset);
641
642 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(i), 3);
643 OUT_RING(ring, offset);
644 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
645 // TODO just give hw a dummy addr for now.. we should
646 // be using this an then CP_MEM_TO_REG to set the
647 // VPC_SO[i].BUFFER_OFFSET for the next draw..
648 OUT_RELOCW(ring, fd5_context(ctx)->blit_mem, 0x100, 0, 0);
649
650 emit->streamout_mask |= (1 << i);
651 }
652 }
653 }
654
655 if ((dirty & FD_DIRTY_BLEND)) {
656 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
657 uint32_t i;
658
659 for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
660 enum pipe_format format = pipe_surface_format(
661 ctx->batch->framebuffer.cbufs[i]);
662 bool is_int = util_format_is_pure_integer(format);
663 bool has_alpha = util_format_has_alpha(format);
664 uint32_t control = blend->rb_mrt[i].control;
665 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
666
667 if (is_int) {
668 control &= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
669 // control |= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
670 }
671
672 if (has_alpha) {
673 blend_control |= blend->rb_mrt[i].blend_control_rgb;
674 } else {
675 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
676 control &= ~A5XX_RB_MRT_CONTROL_BLEND2;
677 }
678
679 OUT_PKT4(ring, REG_A5XX_RB_MRT_CONTROL(i), 1);
680 OUT_RING(ring, control);
681
682 OUT_PKT4(ring, REG_A5XX_RB_MRT_BLEND_CONTROL(i), 1);
683 OUT_RING(ring, blend_control);
684 }
685
686 OUT_PKT4(ring, REG_A5XX_RB_BLEND_CNTL, 1);
687 OUT_RING(ring, blend->rb_blend_cntl |
688 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(0xffff));
689
690 OUT_PKT4(ring, REG_A5XX_SP_BLEND_CNTL, 1);
691 OUT_RING(ring, 0x00000100);
692 }
693
694 if (dirty & FD_DIRTY_BLEND_COLOR) {
695 struct pipe_blend_color *bcolor = &ctx->blend_color;
696
697 OUT_PKT4(ring, REG_A5XX_RB_BLEND_RED, 8);
698 OUT_RING(ring, A5XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
699 A5XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
700 A5XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
701 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[0]));
702 OUT_RING(ring, A5XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
703 A5XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
704 A5XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
705 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[1]));
706 OUT_RING(ring, A5XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
707 A5XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
708 A5XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
709 OUT_RING(ring, A5XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
710 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
711 A5XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
712 A5XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
713 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
714 }
715
716 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX) {
717 needs_border |= emit_textures(ctx, ring, SB4_VS_TEX,
718 &ctx->tex[PIPE_SHADER_VERTEX]);
719 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
720 OUT_RING(ring, ctx->tex[PIPE_SHADER_VERTEX].num_textures);
721 }
722
723 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX) {
724 needs_border |= emit_textures(ctx, ring, SB4_FS_TEX,
725 &ctx->tex[PIPE_SHADER_FRAGMENT]);
726 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
727 OUT_RING(ring, ctx->tex[PIPE_SHADER_FRAGMENT].num_textures);
728 }
729
730 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
731 OUT_RING(ring, 0);
732
733 if (needs_border)
734 emit_border_color(ctx, ring);
735
736 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_SSBO)
737 emit_ssbos(ctx, ring, SB4_SSBO, &ctx->shaderbuf[PIPE_SHADER_FRAGMENT]);
738 }
739
740 void
741 fd5_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
742 struct ir3_shader_variant *cp)
743 {
744 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
745
746 if (dirty & FD_DIRTY_SHADER_TEX) {
747 bool needs_border = false;
748 needs_border |= emit_textures(ctx, ring, SB4_CS_TEX,
749 &ctx->tex[PIPE_SHADER_COMPUTE]);
750
751 if (needs_border)
752 emit_border_color(ctx, ring);
753
754 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
755 OUT_RING(ring, 0);
756
757 OUT_PKT4(ring, REG_A5XX_TPL1_HS_TEX_COUNT, 1);
758 OUT_RING(ring, 0);
759
760 OUT_PKT4(ring, REG_A5XX_TPL1_DS_TEX_COUNT, 1);
761 OUT_RING(ring, 0);
762
763 OUT_PKT4(ring, REG_A5XX_TPL1_GS_TEX_COUNT, 1);
764 OUT_RING(ring, 0);
765
766 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
767 OUT_RING(ring, 0);
768
769 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
770 OUT_RING(ring, ctx->tex[PIPE_SHADER_COMPUTE].num_textures);
771 }
772
773 if (dirty & FD_DIRTY_SHADER_SSBO)
774 emit_ssbos(ctx, ring, SB4_CS_SSBO, &ctx->shaderbuf[PIPE_SHADER_COMPUTE]);
775 }
776
777 /* emit setup at begin of new cmdstream buffer (don't rely on previous
778 * state, there could have been a context switch between ioctls):
779 */
780 void
781 fd5_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
782 {
783 struct fd_context *ctx = batch->ctx;
784
785 fd5_set_render_mode(ctx, ring, BYPASS);
786 fd5_cache_flush(batch, ring);
787
788 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
789 OUT_RING(ring, 0xfffff);
790
791 /*
792 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
793 0000000500024048: 70d08003 00000000 001c5000 00000005
794 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
795 0000000500024058: 70d08003 00000010 001c7000 00000005
796
797 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
798 0000000500024068: 70268000
799 */
800
801 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
802 OUT_RING(ring, 0xffffffff);
803
804 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
805 OUT_RING(ring, 0x00000012);
806
807 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
808 OUT_RING(ring, 0x00000000);
809
810 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
811 OUT_RING(ring, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
812 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
813 OUT_RING(ring, A5XX_GRAS_SU_POINT_SIZE(0.5));
814
815 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
816 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
817
818 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL, 1);
819 OUT_RING(ring, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */
820
821 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG_MAX_CONST, 1);
822 OUT_RING(ring, 0); /* SP_VS_CONFIG_MAX_CONST */
823
824 OUT_PKT4(ring, REG_A5XX_SP_FS_CONFIG_MAX_CONST, 1);
825 OUT_RING(ring, 0); /* SP_FS_CONFIG_MAX_CONST */
826
827 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E292, 2);
828 OUT_RING(ring, 0x00000000); /* UNKNOWN_E292 */
829 OUT_RING(ring, 0x00000000); /* UNKNOWN_E293 */
830
831 OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1);
832 OUT_RING(ring, 0x00000044); /* RB_MODE_CNTL */
833
834 OUT_PKT4(ring, REG_A5XX_RB_DBG_ECO_CNTL, 1);
835 OUT_RING(ring, 0x00100000); /* RB_DBG_ECO_CNTL */
836
837 OUT_PKT4(ring, REG_A5XX_VFD_MODE_CNTL, 1);
838 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
839
840 OUT_PKT4(ring, REG_A5XX_PC_MODE_CNTL, 1);
841 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
842
843 OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1);
844 OUT_RING(ring, 0x0000001e); /* SP_MODE_CNTL */
845
846 OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
847 OUT_RING(ring, 0x40000800); /* SP_DBG_ECO_CNTL */
848
849 OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1);
850 OUT_RING(ring, 0x00000544); /* TPL1_MODE_CNTL */
851
852 OUT_PKT4(ring, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0, 2);
853 OUT_RING(ring, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */
854 OUT_RING(ring, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */
855
856 OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);
857 OUT_RING(ring, 0x00000400); /* VPC_DBG_ECO_CNTL */
858
859 OUT_PKT4(ring, REG_A5XX_HLSQ_MODE_CNTL, 1);
860 OUT_RING(ring, 0x00000001); /* HLSQ_MODE_CNTL */
861
862 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
863 OUT_RING(ring, 0x00000000); /* VPC_MODE_CNTL */
864
865 /* we don't use this yet.. probably best to disable.. */
866 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
867 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
868 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
869 CP_SET_DRAW_STATE__0_GROUP_ID(0));
870 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
871 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
872
873 /* other regs not used (yet?) and always seem to have same value: */
874 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
875 OUT_RING(ring, 0x00000080); /* GRAS_CL_CNTL */
876
877 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
878 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
879
880 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
881 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
882
883 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
884 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
885
886 OUT_PKT4(ring, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL, 1);
887 OUT_RING(ring, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */
888
889 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
890 OUT_RING(ring, A5XX_VPC_SO_OVERRIDE_SO_DISABLE);
891
892 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(0), 3);
893 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
894 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
895 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
896
897 OUT_PKT4(ring, REG_A5XX_VPC_SO_FLUSH_BASE_LO(0), 2);
898 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
899 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
900
901 OUT_PKT4(ring, REG_A5XX_PC_GS_PARAM, 1);
902 OUT_RING(ring, 0x00000000); /* PC_GS_PARAM */
903
904 OUT_PKT4(ring, REG_A5XX_PC_HS_PARAM, 1);
905 OUT_RING(ring, 0x00000000); /* PC_HS_PARAM */
906
907 OUT_PKT4(ring, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL, 1);
908 OUT_RING(ring, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */
909
910 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E001, 1);
911 OUT_RING(ring, 0x00000000); /* UNKNOWN_E001 */
912
913 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E004, 1);
914 OUT_RING(ring, 0x00000000); /* UNKNOWN_E004 */
915
916 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E093, 1);
917 OUT_RING(ring, 0x00000000); /* UNKNOWN_E093 */
918
919 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E1C7, 1);
920 OUT_RING(ring, 0x00000000); /* UNKNOWN_E1C7 */
921
922 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E29A, 1);
923 OUT_RING(ring, 0x00ffff00); /* UNKNOWN_E29A */
924
925 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUF_CNTL, 1);
926 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
927
928 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(0), 1);
929 OUT_RING(ring, 0x00000000); /* UNKNOWN_E2AB */
930
931 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E389, 1);
932 OUT_RING(ring, 0x00000000); /* UNKNOWN_E389 */
933
934 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E38D, 1);
935 OUT_RING(ring, 0x00000000); /* UNKNOWN_E38D */
936
937 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5AB, 1);
938 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5AB */
939
940 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5C2, 1);
941 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5C2 */
942
943 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(1), 3);
944 OUT_RING(ring, 0x00000000);
945 OUT_RING(ring, 0x00000000);
946 OUT_RING(ring, 0x00000000);
947
948 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(1), 6);
949 OUT_RING(ring, 0x00000000);
950 OUT_RING(ring, 0x00000000);
951 OUT_RING(ring, 0x00000000);
952 OUT_RING(ring, 0x00000000);
953 OUT_RING(ring, 0x00000000);
954 OUT_RING(ring, 0x00000000);
955
956 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(2), 6);
957 OUT_RING(ring, 0x00000000);
958 OUT_RING(ring, 0x00000000);
959 OUT_RING(ring, 0x00000000);
960 OUT_RING(ring, 0x00000000);
961 OUT_RING(ring, 0x00000000);
962 OUT_RING(ring, 0x00000000);
963
964 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(3), 3);
965 OUT_RING(ring, 0x00000000);
966 OUT_RING(ring, 0x00000000);
967 OUT_RING(ring, 0x00000000);
968
969 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5DB, 1);
970 OUT_RING(ring, 0x00000000);
971
972 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E600, 1);
973 OUT_RING(ring, 0x00000000);
974
975 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E640, 1);
976 OUT_RING(ring, 0x00000000);
977
978 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 4);
979 OUT_RING(ring, 0x00000000);
980 OUT_RING(ring, 0x00000000);
981 OUT_RING(ring, 0x00000000);
982 OUT_RING(ring, 0x00000000);
983
984 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 2);
985 OUT_RING(ring, 0x00000000);
986 OUT_RING(ring, 0x00000000);
987
988 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C0, 3);
989 OUT_RING(ring, 0x00000000);
990 OUT_RING(ring, 0x00000000);
991 OUT_RING(ring, 0x00000000);
992
993 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C5, 3);
994 OUT_RING(ring, 0x00000000);
995 OUT_RING(ring, 0x00000000);
996 OUT_RING(ring, 0x00000000);
997
998 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CA, 3);
999 OUT_RING(ring, 0x00000000);
1000 OUT_RING(ring, 0x00000000);
1001 OUT_RING(ring, 0x00000000);
1002
1003 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CF, 3);
1004 OUT_RING(ring, 0x00000000);
1005 OUT_RING(ring, 0x00000000);
1006 OUT_RING(ring, 0x00000000);
1007
1008 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D4, 3);
1009 OUT_RING(ring, 0x00000000);
1010 OUT_RING(ring, 0x00000000);
1011 OUT_RING(ring, 0x00000000);
1012
1013 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D9, 3);
1014 OUT_RING(ring, 0x00000000);
1015 OUT_RING(ring, 0x00000000);
1016 OUT_RING(ring, 0x00000000);
1017
1018 // TODO hacks.. these should not be hardcoded:
1019 OUT_PKT4(ring, REG_A5XX_GRAS_SC_CNTL, 1);
1020 OUT_RING(ring, 0x00000008); /* GRAS_SC_CNTL */
1021 }
1022
1023 static void
1024 fd5_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
1025 {
1026 __OUT_IB5(ring, target);
1027 }
1028
1029 void
1030 fd5_emit_init(struct pipe_context *pctx)
1031 {
1032 struct fd_context *ctx = fd_context(pctx);
1033 ctx->emit_const = fd5_emit_const;
1034 ctx->emit_const_bo = fd5_emit_const_bo;
1035 ctx->emit_ib = fd5_emit_ib;
1036 }