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freedreno: shader_t -> gl_shader_stage
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd5_emit.h"
38 #include "fd5_blend.h"
39 #include "fd5_blitter.h"
40 #include "fd5_context.h"
41 #include "fd5_image.h"
42 #include "fd5_program.h"
43 #include "fd5_rasterizer.h"
44 #include "fd5_texture.h"
45 #include "fd5_screen.h"
46 #include "fd5_format.h"
47 #include "fd5_zsa.h"
48
49 /* regid: base const register
50 * prsc or dwords: buffer containing constant values
51 * sizedwords: size of const value buffer
52 */
53 static void
54 fd5_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
55 uint32_t regid, uint32_t offset, uint32_t sizedwords,
56 const uint32_t *dwords, struct pipe_resource *prsc)
57 {
58 uint32_t i, sz;
59 enum a4xx_state_src src;
60
61 debug_assert((regid % 4) == 0);
62 debug_assert((sizedwords % 4) == 0);
63
64 if (prsc) {
65 sz = 0;
66 src = SS4_INDIRECT;
67 } else {
68 sz = sizedwords;
69 src = SS4_DIRECT;
70 }
71
72 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sz);
73 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
74 CP_LOAD_STATE4_0_STATE_SRC(src) |
75 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
76 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
77 if (prsc) {
78 struct fd_bo *bo = fd_resource(prsc)->bo;
79 OUT_RELOC(ring, bo, offset,
80 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
81 } else {
82 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
83 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
84 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
85 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
86 }
87 for (i = 0; i < sz; i++) {
88 OUT_RING(ring, dwords[i]);
89 }
90 }
91
92 static void
93 fd5_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
94 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
95 {
96 uint32_t anum = align(num, 2);
97 uint32_t i;
98
99 debug_assert((regid % 4) == 0);
100
101 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * anum));
102 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
103 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
104 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
105 CP_LOAD_STATE4_0_NUM_UNIT(anum/2));
106 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
107 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
108 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
109
110 for (i = 0; i < num; i++) {
111 if (prscs[i]) {
112 if (write) {
113 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
114 } else {
115 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
116 }
117 } else {
118 OUT_RING(ring, 0xbad00000 | (i << 16));
119 OUT_RING(ring, 0xbad00000 | (i << 16));
120 }
121 }
122
123 for (; i < anum; i++) {
124 OUT_RING(ring, 0xffffffff);
125 OUT_RING(ring, 0xffffffff);
126 }
127 }
128
129 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
130 * the same as a6xx then move this somewhere common ;-)
131 *
132 * Entry layout looks like (total size, 0x60 bytes):
133 */
134
135 struct PACKED bcolor_entry {
136 uint32_t fp32[4];
137 uint16_t ui16[4];
138 int16_t si16[4];
139
140 uint16_t fp16[4];
141 uint16_t rgb565;
142 uint16_t rgb5a1;
143 uint16_t rgba4;
144 uint8_t __pad0[2];
145 uint8_t ui8[4];
146 int8_t si8[4];
147 uint32_t rgb10a2;
148 uint32_t z24; /* also s8? */
149
150 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
151 uint8_t __pad1[24];
152 };
153
154 #define FD5_BORDER_COLOR_SIZE 0x60
155 #define FD5_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD5_BORDER_COLOR_SIZE)
156
157 static void
158 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
159 {
160 unsigned i, j;
161 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE);
162
163 for (i = 0; i < tex->num_samplers; i++) {
164 struct bcolor_entry *e = &entries[i];
165 struct pipe_sampler_state *sampler = tex->samplers[i];
166 union pipe_color_union *bc;
167
168 if (!sampler)
169 continue;
170
171 bc = &sampler->border_color;
172
173 /*
174 * XXX HACK ALERT XXX
175 *
176 * The border colors need to be swizzled in a particular
177 * format-dependent order. Even though samplers don't know about
178 * formats, we can assume that with a GL state tracker, there's a
179 * 1:1 correspondence between sampler and texture. Take advantage
180 * of that knowledge.
181 */
182 if ((i >= tex->num_textures) || !tex->textures[i])
183 continue;
184
185 enum pipe_format format = tex->textures[i]->format;
186 const struct util_format_description *desc =
187 util_format_description(format);
188
189 e->rgb565 = 0;
190 e->rgb5a1 = 0;
191 e->rgba4 = 0;
192 e->rgb10a2 = 0;
193 e->z24 = 0;
194
195 for (j = 0; j < 4; j++) {
196 int c = desc->swizzle[j];
197 int cd = c;
198
199 /*
200 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the
201 * stencil border color value in bc->ui[0] but according
202 * to desc->swizzle and desc->channel, the .x component
203 * is NONE and the stencil value is in the y component.
204 * Meanwhile the hardware wants this in the .x componetn.
205 */
206 if ((format == PIPE_FORMAT_X24S8_UINT) ||
207 (format == PIPE_FORMAT_X32_S8X24_UINT)) {
208 if (j == 0) {
209 c = 1;
210 cd = 0;
211 } else {
212 continue;
213 }
214 }
215
216 if (c >= 4)
217 continue;
218
219 if (desc->channel[c].pure_integer) {
220 uint16_t clamped;
221 switch (desc->channel[c].size) {
222 case 2:
223 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
224 clamped = CLAMP(bc->ui[j], 0, 0x3);
225 break;
226 case 8:
227 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
228 clamped = CLAMP(bc->i[j], -128, 127);
229 else
230 clamped = CLAMP(bc->ui[j], 0, 255);
231 break;
232 case 10:
233 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
234 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
235 break;
236 case 16:
237 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
238 clamped = CLAMP(bc->i[j], -32768, 32767);
239 else
240 clamped = CLAMP(bc->ui[j], 0, 65535);
241 break;
242 default:
243 assert(!"Unexpected bit size");
244 case 32:
245 clamped = 0;
246 break;
247 }
248 e->fp32[cd] = bc->ui[j];
249 e->fp16[cd] = clamped;
250 } else {
251 float f = bc->f[j];
252 float f_u = CLAMP(f, 0, 1);
253 float f_s = CLAMP(f, -1, 1);
254
255 e->fp32[c] = fui(f);
256 e->fp16[c] = util_float_to_half(f);
257 e->srgb[c] = util_float_to_half(f_u);
258 e->ui16[c] = f_u * 0xffff;
259 e->si16[c] = f_s * 0x7fff;
260 e->ui8[c] = f_u * 0xff;
261 e->si8[c] = f_s * 0x7f;
262 if (c == 1)
263 e->rgb565 |= (int)(f_u * 0x3f) << 5;
264 else if (c < 3)
265 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
266 if (c == 3)
267 e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
268 else
269 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
270 if (c == 3)
271 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
272 else
273 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
274 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
275 if (c == 0)
276 e->z24 = f_u * 0xffffff;
277 }
278 }
279
280 #ifdef DEBUG
281 memset(&e->__pad0, 0, sizeof(e->__pad0));
282 memset(&e->__pad1, 0, sizeof(e->__pad1));
283 #endif
284 }
285 }
286
287 static void
288 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
289 {
290 struct fd5_context *fd5_ctx = fd5_context(ctx);
291 struct bcolor_entry *entries;
292 unsigned off;
293 void *ptr;
294
295 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE);
296
297 u_upload_alloc(fd5_ctx->border_color_uploader,
298 0, FD5_BORDER_COLOR_UPLOAD_SIZE,
299 FD5_BORDER_COLOR_UPLOAD_SIZE, &off,
300 &fd5_ctx->border_color_buf,
301 &ptr);
302
303 entries = ptr;
304
305 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
306 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
307 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
308
309 OUT_PKT4(ring, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
310 OUT_RELOC(ring, fd_resource(fd5_ctx->border_color_buf)->bo, off, 0, 0);
311
312 u_upload_unmap(fd5_ctx->border_color_uploader);
313 }
314
315 static bool
316 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
317 enum a4xx_state_block sb, struct fd_texture_stateobj *tex)
318 {
319 bool needs_border = false;
320 unsigned bcolor_offset = (sb == SB4_FS_TEX) ? ctx->tex[PIPE_SHADER_VERTEX].num_samplers : 0;
321 unsigned i;
322
323 if (tex->num_samplers > 0) {
324 /* output sampler state: */
325 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (4 * tex->num_samplers));
326 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
327 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
328 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
329 CP_LOAD_STATE4_0_NUM_UNIT(tex->num_samplers));
330 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
331 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
332 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
333 for (i = 0; i < tex->num_samplers; i++) {
334 static const struct fd5_sampler_stateobj dummy_sampler = {};
335 const struct fd5_sampler_stateobj *sampler = tex->samplers[i] ?
336 fd5_sampler_stateobj(tex->samplers[i]) :
337 &dummy_sampler;
338 OUT_RING(ring, sampler->texsamp0);
339 OUT_RING(ring, sampler->texsamp1);
340 OUT_RING(ring, sampler->texsamp2 |
341 A5XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset));
342 OUT_RING(ring, sampler->texsamp3);
343
344 needs_border |= sampler->needs_border;
345 }
346 }
347
348 if (tex->num_textures > 0) {
349 unsigned num_textures = tex->num_textures;
350
351 /* emit texture state: */
352 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (12 * num_textures));
353 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
354 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
355 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
356 CP_LOAD_STATE4_0_NUM_UNIT(num_textures));
357 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
358 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
359 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
360 for (i = 0; i < tex->num_textures; i++) {
361 static const struct fd5_pipe_sampler_view dummy_view = {};
362 const struct fd5_pipe_sampler_view *view = tex->textures[i] ?
363 fd5_pipe_sampler_view(tex->textures[i]) :
364 &dummy_view;
365 enum a5xx_tile_mode tile_mode = TILE5_LINEAR;
366
367 if (view->base.texture)
368 tile_mode = fd_resource(view->base.texture)->tile_mode;
369
370 OUT_RING(ring, view->texconst0 |
371 A5XX_TEX_CONST_0_TILE_MODE(tile_mode));
372 OUT_RING(ring, view->texconst1);
373 OUT_RING(ring, view->texconst2);
374 OUT_RING(ring, view->texconst3);
375 if (view->base.texture) {
376 struct fd_resource *rsc = fd_resource(view->base.texture);
377 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
378 rsc = rsc->stencil;
379 OUT_RELOC(ring, rsc->bo, view->offset,
380 (uint64_t)view->texconst5 << 32, 0);
381 } else {
382 OUT_RING(ring, 0x00000000);
383 OUT_RING(ring, view->texconst5);
384 }
385 OUT_RING(ring, view->texconst6);
386 OUT_RING(ring, view->texconst7);
387 OUT_RING(ring, view->texconst8);
388 OUT_RING(ring, view->texconst9);
389 OUT_RING(ring, view->texconst10);
390 OUT_RING(ring, view->texconst11);
391 }
392 }
393
394 return needs_border;
395 }
396
397 static void
398 emit_ssbos(struct fd_context *ctx, struct fd_ringbuffer *ring,
399 enum a4xx_state_block sb, struct fd_shaderbuf_stateobj *so)
400 {
401 unsigned count = util_last_bit(so->enabled_mask);
402
403 if (count == 0)
404 return;
405
406 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (4 * count));
407 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
408 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
409 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
410 CP_LOAD_STATE4_0_NUM_UNIT(count));
411 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(0) |
412 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
413 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
414 for (unsigned i = 0; i < count; i++) {
415 OUT_RING(ring, 0x00000000);
416 OUT_RING(ring, 0x00000000);
417 OUT_RING(ring, 0x00000000);
418 OUT_RING(ring, 0x00000000);
419 }
420
421 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * count));
422 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
423 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
424 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
425 CP_LOAD_STATE4_0_NUM_UNIT(count));
426 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(1) |
427 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
428 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
429 for (unsigned i = 0; i < count; i++) {
430 struct pipe_shader_buffer *buf = &so->sb[i];
431 unsigned sz = buf->buffer_size;
432
433 /* width is in dwords, overflows into height: */
434 sz /= 4;
435
436 OUT_RING(ring, A5XX_SSBO_1_0_WIDTH(sz));
437 OUT_RING(ring, A5XX_SSBO_1_1_HEIGHT(sz >> 16));
438 }
439
440 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * count));
441 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
442 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
443 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
444 CP_LOAD_STATE4_0_NUM_UNIT(count));
445 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(2) |
446 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
447 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
448 for (unsigned i = 0; i < count; i++) {
449 struct pipe_shader_buffer *buf = &so->sb[i];
450 if (buf->buffer) {
451 struct fd_resource *rsc = fd_resource(buf->buffer);
452 OUT_RELOCW(ring, rsc->bo, buf->buffer_offset, 0, 0);
453 } else {
454 OUT_RING(ring, 0x00000000);
455 OUT_RING(ring, 0x00000000);
456 }
457 }
458 }
459
460 void
461 fd5_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd5_emit *emit)
462 {
463 int32_t i, j;
464 const struct fd_vertex_state *vtx = emit->vtx;
465 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
466
467 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
468 if (vp->inputs[i].sysval)
469 continue;
470 if (vp->inputs[i].compmask) {
471 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
472 const struct pipe_vertex_buffer *vb =
473 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
474 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
475 enum pipe_format pfmt = elem->src_format;
476 enum a5xx_vtx_fmt fmt = fd5_pipe2vtx(pfmt);
477 bool isint = util_format_is_pure_integer(pfmt);
478 uint32_t off = vb->buffer_offset + elem->src_offset;
479 uint32_t size = fd_bo_size(rsc->bo) - off;
480 debug_assert(fmt != ~0);
481
482 #ifdef DEBUG
483 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
484 */
485 if (off > fd_bo_size(rsc->bo))
486 continue;
487 #endif
488
489 OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4);
490 OUT_RELOC(ring, rsc->bo, off, 0, 0);
491 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
492 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
493
494 OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2);
495 OUT_RING(ring, A5XX_VFD_DECODE_INSTR_IDX(j) |
496 A5XX_VFD_DECODE_INSTR_FORMAT(fmt) |
497 COND(elem->instance_divisor, A5XX_VFD_DECODE_INSTR_INSTANCED) |
498 A5XX_VFD_DECODE_INSTR_SWAP(fd5_pipe2swap(pfmt)) |
499 A5XX_VFD_DECODE_INSTR_UNK30 |
500 COND(!isint, A5XX_VFD_DECODE_INSTR_FLOAT));
501 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
502
503 OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1);
504 OUT_RING(ring, A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
505 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
506
507 j++;
508 }
509 }
510
511 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1);
512 OUT_RING(ring, A5XX_VFD_CONTROL_0_VTXCNT(j));
513 }
514
515 void
516 fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
517 struct fd5_emit *emit)
518 {
519 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
520 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
521 const struct ir3_shader_variant *fp = fd5_emit_get_fp(emit);
522 const enum fd_dirty_3d_state dirty = emit->dirty;
523 bool needs_border = false;
524
525 emit_marker5(ring, 5);
526
527 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->binning_pass) {
528 unsigned char mrt_comp[A5XX_MAX_RENDER_TARGETS] = {0};
529
530 for (unsigned i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
531 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
532 }
533
534 OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1);
535 OUT_RING(ring, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
536 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
537 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
538 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
539 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
540 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
541 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
542 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
543 }
544
545 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
546 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
547 uint32_t rb_alpha_control = zsa->rb_alpha_control;
548
549 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
550 rb_alpha_control &= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST;
551
552 OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1);
553 OUT_RING(ring, rb_alpha_control);
554
555 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1);
556 OUT_RING(ring, zsa->rb_stencil_control);
557 }
558
559 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG)) {
560 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
561 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
562
563 if (pfb->zsbuf) {
564 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
565 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
566
567 if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid)
568 gras_lrz_cntl = 0;
569 else if (emit->binning_pass && blend->lrz_write && zsa->lrz_write)
570 gras_lrz_cntl |= A5XX_GRAS_LRZ_CNTL_LRZ_WRITE;
571
572 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
573 OUT_RING(ring, gras_lrz_cntl);
574 }
575 }
576
577 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
578 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
579 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
580
581 OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 2);
582 OUT_RING(ring, zsa->rb_stencilrefmask |
583 A5XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
584 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
585 A5XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
586 }
587
588 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
589 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
590 bool fragz = fp->has_kill | fp->writes_pos;
591
592 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_CNTL, 1);
593 OUT_RING(ring, zsa->rb_depth_cntl);
594
595 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_PLANE_CNTL, 1);
596 OUT_RING(ring, COND(fragz, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
597 COND(fragz && fp->frag_coord, A5XX_RB_DEPTH_PLANE_CNTL_UNK1));
598
599 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
600 OUT_RING(ring, COND(fragz, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
601 COND(fragz && fp->frag_coord, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1));
602 }
603
604 /* NOTE: scissor enabled bit is part of rasterizer state: */
605 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
606 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
607
608 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
609 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
610 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
611 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
612 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
613
614 OUT_PKT4(ring, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
615 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
616 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
617 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
618 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
619
620 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
621 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
622 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
623 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
624 }
625
626 if (dirty & FD_DIRTY_VIEWPORT) {
627 fd_wfi(ctx->batch, ring);
628 OUT_PKT4(ring, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0, 6);
629 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
630 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
631 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
632 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
633 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
634 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
635 }
636
637 if (dirty & FD_DIRTY_PROG)
638 fd5_program_emit(ctx, ring, emit);
639
640 if (dirty & FD_DIRTY_RASTERIZER) {
641 struct fd5_rasterizer_stateobj *rasterizer =
642 fd5_rasterizer_stateobj(ctx->rasterizer);
643
644 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
645 OUT_RING(ring, rasterizer->gras_su_cntl |
646 COND(pfb->samples > 1, A5XX_GRAS_SU_CNTL_MSAA_ENABLE));
647
648 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
649 OUT_RING(ring, rasterizer->gras_su_point_minmax);
650 OUT_RING(ring, rasterizer->gras_su_point_size);
651
652 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
653 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
654 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
655 OUT_RING(ring, rasterizer->gras_su_poly_offset_clamp);
656
657 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
658 OUT_RING(ring, rasterizer->pc_raster_cntl);
659
660 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
661 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
662 }
663
664 /* note: must come after program emit.. because there is some overlap
665 * in registers, ex. PC_PRIMITIVE_CNTL and we rely on some cached
666 * values from fd5_program_emit() to avoid having to re-emit the prog
667 * every time rast state changes.
668 *
669 * Since the primitive restart state is not part of a tracked object, we
670 * re-emit this register every time.
671 */
672 if (emit->info && ctx->rasterizer) {
673 struct fd5_rasterizer_stateobj *rasterizer =
674 fd5_rasterizer_stateobj(ctx->rasterizer);
675 unsigned max_loc = fd5_context(ctx)->max_loc;
676
677 OUT_PKT4(ring, REG_A5XX_PC_PRIMITIVE_CNTL, 1);
678 OUT_RING(ring, rasterizer->pc_primitive_cntl |
679 A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(max_loc) |
680 COND(emit->info->primitive_restart && emit->info->index_size,
681 A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART));
682 }
683
684 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
685 uint32_t posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
686 unsigned nr = pfb->nr_cbufs;
687
688 if (emit->binning_pass)
689 nr = 0;
690 else if (ctx->rasterizer->rasterizer_discard)
691 nr = 0;
692
693 OUT_PKT4(ring, REG_A5XX_RB_FS_OUTPUT_CNTL, 1);
694 OUT_RING(ring, A5XX_RB_FS_OUTPUT_CNTL_MRT(nr) |
695 COND(fp->writes_pos, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z));
696
697 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_CNTL, 1);
698 OUT_RING(ring, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr) |
699 A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid) |
700 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
701 }
702
703 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
704 if (!emit->binning_pass)
705 ir3_emit_fs_consts(fp, ring, ctx);
706
707 struct pipe_stream_output_info *info = &vp->shader->stream_output;
708 if (info->num_outputs) {
709 struct fd_streamout_stateobj *so = &ctx->streamout;
710
711 for (unsigned i = 0; i < so->num_targets; i++) {
712 struct pipe_stream_output_target *target = so->targets[i];
713
714 if (!target)
715 continue;
716
717 unsigned offset = (so->offsets[i] * info->stride[i] * 4) +
718 target->buffer_offset;
719
720 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(i), 3);
721 /* VPC_SO[i].BUFFER_BASE_LO: */
722 OUT_RELOCW(ring, fd_resource(target->buffer)->bo, 0, 0, 0);
723 OUT_RING(ring, target->buffer_size + offset);
724
725 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(i), 3);
726 OUT_RING(ring, offset);
727 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
728 // TODO just give hw a dummy addr for now.. we should
729 // be using this an then CP_MEM_TO_REG to set the
730 // VPC_SO[i].BUFFER_OFFSET for the next draw..
731 OUT_RELOCW(ring, fd5_context(ctx)->blit_mem, 0x100, 0, 0);
732
733 emit->streamout_mask |= (1 << i);
734 }
735 }
736
737 if (dirty & FD_DIRTY_BLEND) {
738 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
739 uint32_t i;
740
741 for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
742 enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
743 bool is_int = util_format_is_pure_integer(format);
744 bool has_alpha = util_format_has_alpha(format);
745 uint32_t control = blend->rb_mrt[i].control;
746 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
747
748 if (is_int) {
749 control &= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
750 control |= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
751 }
752
753 if (has_alpha) {
754 blend_control |= blend->rb_mrt[i].blend_control_rgb;
755 } else {
756 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
757 control &= ~A5XX_RB_MRT_CONTROL_BLEND2;
758 }
759
760 OUT_PKT4(ring, REG_A5XX_RB_MRT_CONTROL(i), 1);
761 OUT_RING(ring, control);
762
763 OUT_PKT4(ring, REG_A5XX_RB_MRT_BLEND_CONTROL(i), 1);
764 OUT_RING(ring, blend_control);
765 }
766
767 OUT_PKT4(ring, REG_A5XX_SP_BLEND_CNTL, 1);
768 OUT_RING(ring, blend->sp_blend_cntl);
769 }
770
771 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK)) {
772 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
773
774 OUT_PKT4(ring, REG_A5XX_RB_BLEND_CNTL, 1);
775 OUT_RING(ring, blend->rb_blend_cntl |
776 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(ctx->sample_mask));
777 }
778
779 if (dirty & FD_DIRTY_BLEND_COLOR) {
780 struct pipe_blend_color *bcolor = &ctx->blend_color;
781
782 OUT_PKT4(ring, REG_A5XX_RB_BLEND_RED, 8);
783 OUT_RING(ring, A5XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
784 A5XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
785 A5XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
786 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[0]));
787 OUT_RING(ring, A5XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
788 A5XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
789 A5XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
790 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[1]));
791 OUT_RING(ring, A5XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
792 A5XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
793 A5XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
794 OUT_RING(ring, A5XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
795 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
796 A5XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
797 A5XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
798 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
799 }
800
801 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX) {
802 needs_border |= emit_textures(ctx, ring, SB4_VS_TEX,
803 &ctx->tex[PIPE_SHADER_VERTEX]);
804 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
805 OUT_RING(ring, ctx->tex[PIPE_SHADER_VERTEX].num_textures);
806 }
807
808 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX) {
809 needs_border |= emit_textures(ctx, ring, SB4_FS_TEX,
810 &ctx->tex[PIPE_SHADER_FRAGMENT]);
811 }
812
813 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
814 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_FRAGMENT].enabled_mask ?
815 ~0 : ctx->tex[PIPE_SHADER_FRAGMENT].num_textures);
816
817 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
818 OUT_RING(ring, 0);
819
820 if (needs_border)
821 emit_border_color(ctx, ring);
822
823 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_SSBO)
824 emit_ssbos(ctx, ring, SB4_SSBO, &ctx->shaderbuf[PIPE_SHADER_FRAGMENT]);
825
826 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_IMAGE)
827 fd5_emit_images(ctx, ring, PIPE_SHADER_FRAGMENT);
828 }
829
830 void
831 fd5_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
832 struct ir3_shader_variant *cp)
833 {
834 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
835
836 if (dirty & FD_DIRTY_SHADER_TEX) {
837 bool needs_border = false;
838 needs_border |= emit_textures(ctx, ring, SB4_CS_TEX,
839 &ctx->tex[PIPE_SHADER_COMPUTE]);
840
841 if (needs_border)
842 emit_border_color(ctx, ring);
843
844 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
845 OUT_RING(ring, 0);
846
847 OUT_PKT4(ring, REG_A5XX_TPL1_HS_TEX_COUNT, 1);
848 OUT_RING(ring, 0);
849
850 OUT_PKT4(ring, REG_A5XX_TPL1_DS_TEX_COUNT, 1);
851 OUT_RING(ring, 0);
852
853 OUT_PKT4(ring, REG_A5XX_TPL1_GS_TEX_COUNT, 1);
854 OUT_RING(ring, 0);
855
856 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
857 OUT_RING(ring, 0);
858 }
859
860 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
861 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_COMPUTE].enabled_mask ?
862 ~0 : ctx->tex[PIPE_SHADER_COMPUTE].num_textures);
863
864 if (dirty & FD_DIRTY_SHADER_SSBO)
865 emit_ssbos(ctx, ring, SB4_CS_SSBO, &ctx->shaderbuf[PIPE_SHADER_COMPUTE]);
866
867 if (dirty & FD_DIRTY_SHADER_IMAGE)
868 fd5_emit_images(ctx, ring, PIPE_SHADER_COMPUTE);
869 }
870
871 /* emit setup at begin of new cmdstream buffer (don't rely on previous
872 * state, there could have been a context switch between ioctls):
873 */
874 void
875 fd5_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
876 {
877 struct fd_context *ctx = batch->ctx;
878
879 fd5_set_render_mode(ctx, ring, BYPASS);
880 fd5_cache_flush(batch, ring);
881
882 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
883 OUT_RING(ring, 0xfffff);
884
885 /*
886 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
887 0000000500024048: 70d08003 00000000 001c5000 00000005
888 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
889 0000000500024058: 70d08003 00000010 001c7000 00000005
890
891 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
892 0000000500024068: 70268000
893 */
894
895 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
896 OUT_RING(ring, 0xffffffff);
897
898 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
899 OUT_RING(ring, 0x00000012);
900
901 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
902 OUT_RING(ring, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
903 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
904 OUT_RING(ring, A5XX_GRAS_SU_POINT_SIZE(0.5));
905
906 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
907 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
908
909 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL, 1);
910 OUT_RING(ring, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */
911
912 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG_MAX_CONST, 1);
913 OUT_RING(ring, 0); /* SP_VS_CONFIG_MAX_CONST */
914
915 OUT_PKT4(ring, REG_A5XX_SP_FS_CONFIG_MAX_CONST, 1);
916 OUT_RING(ring, 0); /* SP_FS_CONFIG_MAX_CONST */
917
918 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E292, 2);
919 OUT_RING(ring, 0x00000000); /* UNKNOWN_E292 */
920 OUT_RING(ring, 0x00000000); /* UNKNOWN_E293 */
921
922 OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1);
923 OUT_RING(ring, 0x00000044); /* RB_MODE_CNTL */
924
925 OUT_PKT4(ring, REG_A5XX_RB_DBG_ECO_CNTL, 1);
926 OUT_RING(ring, 0x00100000); /* RB_DBG_ECO_CNTL */
927
928 OUT_PKT4(ring, REG_A5XX_VFD_MODE_CNTL, 1);
929 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
930
931 OUT_PKT4(ring, REG_A5XX_PC_MODE_CNTL, 1);
932 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
933
934 OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1);
935 OUT_RING(ring, 0x0000001e); /* SP_MODE_CNTL */
936
937 OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
938 OUT_RING(ring, 0x40000800); /* SP_DBG_ECO_CNTL */
939
940 OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1);
941 OUT_RING(ring, 0x00000544); /* TPL1_MODE_CNTL */
942
943 OUT_PKT4(ring, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0, 2);
944 OUT_RING(ring, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */
945 OUT_RING(ring, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */
946
947 OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);
948 OUT_RING(ring, 0x00000400); /* VPC_DBG_ECO_CNTL */
949
950 OUT_PKT4(ring, REG_A5XX_HLSQ_MODE_CNTL, 1);
951 OUT_RING(ring, 0x00000001); /* HLSQ_MODE_CNTL */
952
953 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
954 OUT_RING(ring, 0x00000000); /* VPC_MODE_CNTL */
955
956 /* we don't use this yet.. probably best to disable.. */
957 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
958 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
959 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
960 CP_SET_DRAW_STATE__0_GROUP_ID(0));
961 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
962 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
963
964 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
965 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
966
967 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
968 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
969
970 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
971 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
972
973 OUT_PKT4(ring, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL, 1);
974 OUT_RING(ring, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */
975
976 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
977 OUT_RING(ring, A5XX_VPC_SO_OVERRIDE_SO_DISABLE);
978
979 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(0), 3);
980 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
981 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
982 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
983
984 OUT_PKT4(ring, REG_A5XX_VPC_SO_FLUSH_BASE_LO(0), 2);
985 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
986 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
987
988 OUT_PKT4(ring, REG_A5XX_PC_GS_PARAM, 1);
989 OUT_RING(ring, 0x00000000); /* PC_GS_PARAM */
990
991 OUT_PKT4(ring, REG_A5XX_PC_HS_PARAM, 1);
992 OUT_RING(ring, 0x00000000); /* PC_HS_PARAM */
993
994 OUT_PKT4(ring, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL, 1);
995 OUT_RING(ring, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */
996
997 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E001, 1);
998 OUT_RING(ring, 0x00000000); /* UNKNOWN_E001 */
999
1000 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E004, 1);
1001 OUT_RING(ring, 0x00000000); /* UNKNOWN_E004 */
1002
1003 OUT_PKT4(ring, REG_A5XX_GRAS_SU_LAYERED, 1);
1004 OUT_RING(ring, 0x00000000); /* GRAS_SU_LAYERED */
1005
1006 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E29A, 1);
1007 OUT_RING(ring, 0x00ffff00); /* UNKNOWN_E29A */
1008
1009 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUF_CNTL, 1);
1010 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
1011
1012 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(0), 1);
1013 OUT_RING(ring, 0x00000000); /* UNKNOWN_E2AB */
1014
1015 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E389, 1);
1016 OUT_RING(ring, 0x00000000); /* UNKNOWN_E389 */
1017
1018 OUT_PKT4(ring, REG_A5XX_PC_GS_LAYERED, 1);
1019 OUT_RING(ring, 0x00000000); /* PC_GS_LAYERED */
1020
1021 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5AB, 1);
1022 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5AB */
1023
1024 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5C2, 1);
1025 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5C2 */
1026
1027 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1028 OUT_RING(ring, 0x00000000);
1029 OUT_RING(ring, 0x00000000);
1030 OUT_RING(ring, 0x00000000);
1031
1032 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(1), 6);
1033 OUT_RING(ring, 0x00000000);
1034 OUT_RING(ring, 0x00000000);
1035 OUT_RING(ring, 0x00000000);
1036 OUT_RING(ring, 0x00000000);
1037 OUT_RING(ring, 0x00000000);
1038 OUT_RING(ring, 0x00000000);
1039
1040 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(2), 6);
1041 OUT_RING(ring, 0x00000000);
1042 OUT_RING(ring, 0x00000000);
1043 OUT_RING(ring, 0x00000000);
1044 OUT_RING(ring, 0x00000000);
1045 OUT_RING(ring, 0x00000000);
1046 OUT_RING(ring, 0x00000000);
1047
1048 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(3), 3);
1049 OUT_RING(ring, 0x00000000);
1050 OUT_RING(ring, 0x00000000);
1051 OUT_RING(ring, 0x00000000);
1052
1053 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5DB, 1);
1054 OUT_RING(ring, 0x00000000);
1055
1056 OUT_PKT4(ring, REG_A5XX_SP_HS_CTRL_REG0, 1);
1057 OUT_RING(ring, 0x00000000);
1058
1059 OUT_PKT4(ring, REG_A5XX_SP_GS_CTRL_REG0, 1);
1060 OUT_RING(ring, 0x00000000);
1061
1062 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 4);
1063 OUT_RING(ring, 0x00000000);
1064 OUT_RING(ring, 0x00000000);
1065 OUT_RING(ring, 0x00000000);
1066 OUT_RING(ring, 0x00000000);
1067
1068 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 2);
1069 OUT_RING(ring, 0x00000000);
1070 OUT_RING(ring, 0x00000000);
1071
1072 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C0, 3);
1073 OUT_RING(ring, 0x00000000);
1074 OUT_RING(ring, 0x00000000);
1075 OUT_RING(ring, 0x00000000);
1076
1077 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C5, 3);
1078 OUT_RING(ring, 0x00000000);
1079 OUT_RING(ring, 0x00000000);
1080 OUT_RING(ring, 0x00000000);
1081
1082 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CA, 3);
1083 OUT_RING(ring, 0x00000000);
1084 OUT_RING(ring, 0x00000000);
1085 OUT_RING(ring, 0x00000000);
1086
1087 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CF, 3);
1088 OUT_RING(ring, 0x00000000);
1089 OUT_RING(ring, 0x00000000);
1090 OUT_RING(ring, 0x00000000);
1091
1092 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D4, 3);
1093 OUT_RING(ring, 0x00000000);
1094 OUT_RING(ring, 0x00000000);
1095 OUT_RING(ring, 0x00000000);
1096
1097 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D9, 3);
1098 OUT_RING(ring, 0x00000000);
1099 OUT_RING(ring, 0x00000000);
1100 OUT_RING(ring, 0x00000000);
1101
1102 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
1103 OUT_RING(ring, 0x00000000);
1104 }
1105
1106 static void
1107 fd5_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
1108 {
1109 /* for debug after a lock up, write a unique counter value
1110 * to scratch6 for each IB, to make it easier to match up
1111 * register dumps to cmdstream. The combination of IB and
1112 * DRAW (scratch7) is enough to "triangulate" the particular
1113 * draw that caused lockup.
1114 */
1115 emit_marker5(ring, 6);
1116 __OUT_IB5(ring, target);
1117 emit_marker5(ring, 6);
1118 }
1119
1120 static void
1121 fd5_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
1122 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
1123 unsigned sizedwords)
1124 {
1125 struct fd_bo *src_bo = fd_resource(src)->bo;
1126 struct fd_bo *dst_bo = fd_resource(dst)->bo;
1127 unsigned i;
1128
1129 for (i = 0; i < sizedwords; i++) {
1130 OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
1131 OUT_RING(ring, 0x00000000);
1132 OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
1133 OUT_RELOC (ring, src_bo, src_off, 0, 0);
1134
1135 dst_off += 4;
1136 src_off += 4;
1137 }
1138 }
1139
1140 void
1141 fd5_emit_init(struct pipe_context *pctx)
1142 {
1143 struct fd_context *ctx = fd_context(pctx);
1144 ctx->emit_const = fd5_emit_const;
1145 ctx->emit_const_bo = fd5_emit_const_bo;
1146 ctx->emit_ib = fd5_emit_ib;
1147 ctx->mem_to_mem = fd5_mem_to_mem;
1148 }