2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/u_format.h"
32 #include "util/u_viewport.h"
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
38 #include "fd5_blend.h"
39 #include "fd5_context.h"
40 #include "fd5_program.h"
41 #include "fd5_rasterizer.h"
42 #include "fd5_texture.h"
43 #include "fd5_format.h"
46 /* regid: base const register
47 * prsc or dwords: buffer containing constant values
48 * sizedwords: size of const value buffer
51 fd5_emit_const(struct fd_ringbuffer
*ring
, enum shader_t type
,
52 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
53 const uint32_t *dwords
, struct pipe_resource
*prsc
)
56 enum a4xx_state_src src
;
58 debug_assert((regid
% 4) == 0);
59 debug_assert((sizedwords
% 4) == 0);
69 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + sz
);
70 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(regid
/4) |
71 CP_LOAD_STATE4_0_STATE_SRC(src
) |
72 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type
)) |
73 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords
/4));
75 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
76 OUT_RELOC(ring
, bo
, offset
,
77 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
), 0);
79 OUT_RING(ring
, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
80 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
));
81 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
82 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
84 for (i
= 0; i
< sz
; i
++) {
85 OUT_RING(ring
, dwords
[i
]);
90 fd5_emit_const_bo(struct fd_ringbuffer
*ring
, enum shader_t type
, boolean write
,
91 uint32_t regid
, uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
)
93 uint32_t anum
= align(num
, 2);
96 debug_assert((regid
% 4) == 0);
98 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + (2 * anum
));
99 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(regid
/4) |
100 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
101 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type
)) |
102 CP_LOAD_STATE4_0_NUM_UNIT(anum
/2));
103 OUT_RING(ring
, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
104 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
));
105 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
107 for (i
= 0; i
< num
; i
++) {
110 OUT_RELOCW(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
112 OUT_RELOC(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
115 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
116 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
120 for (; i
< anum
; i
++) {
121 OUT_RING(ring
, 0xffffffff);
122 OUT_RING(ring
, 0xffffffff);
126 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
127 * the same as a6xx then move this somewhere common ;-)
129 * Entry layout looks like (total size, 0x60 bytes):
131 * offset | description
132 * -------+-------------
149 * 0x28 | ?? maybe padding ??
158 * 0x38 | ?? maybe padding ??
160 * Some uncertainty, because not clear that this actually works properly
161 * with blob, so who knows..
164 struct PACKED bcolor_entry
{
175 #define FD5_BORDER_COLOR_SIZE 0x60
176 #define FD5_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD5_BORDER_COLOR_SIZE)
177 #define FD5_BORDER_COLOR_OFFSET 8 /* TODO probably should be dynamic */
180 setup_border_colors(struct fd_texture_stateobj
*tex
, struct bcolor_entry
*entries
)
184 debug_assert(tex
->num_samplers
< FD5_BORDER_COLOR_OFFSET
); // TODO
186 for (i
= 0; i
< tex
->num_samplers
; i
++) {
187 struct bcolor_entry
*e
= &entries
[i
];
188 struct pipe_sampler_state
*sampler
= tex
->samplers
[i
];
189 union pipe_color_union
*bc
;
194 bc
= &sampler
->border_color
;
199 * The border colors need to be swizzled in a particular
200 * format-dependent order. Even though samplers don't know about
201 * formats, we can assume that with a GL state tracker, there's a
202 * 1:1 correspondence between sampler and texture. Take advantage
205 if ((i
>= tex
->num_textures
) || !tex
->textures
[i
])
208 const struct util_format_description
*desc
=
209 util_format_description(tex
->textures
[i
]->format
);
211 for (j
= 0; j
< 4; j
++) {
212 int c
= desc
->swizzle
[j
];
217 if (desc
->channel
[c
].pure_integer
) {
221 e
->fp16
[j
] = util_float_to_half(f
);
222 e
->ui16
[j
] = bc
->ui
[c
];
223 e
->si16
[j
] = bc
->i
[c
];
224 e
->ui8
[j
] = bc
->ui
[c
];
225 e
->si8
[j
] = bc
->i
[c
];
230 e
->fp16
[j
] = util_float_to_half(f
);
231 e
->ui16
[j
] = f
* 65535.0;
232 e
->si16
[j
] = f
* 32767.5;
233 e
->ui8
[j
] = f
* 255.0;
234 e
->si8
[j
] = f
* 128.0;
239 memset(&e
->__pad0
, 0, sizeof(e
->__pad0
));
240 memset(&e
->__pad1
, 0, sizeof(e
->__pad1
));
246 emit_border_color(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
)
248 struct fd5_context
*fd5_ctx
= fd5_context(ctx
);
249 struct bcolor_entry
*entries
;
253 STATIC_ASSERT(sizeof(struct bcolor_entry
) == FD5_BORDER_COLOR_SIZE
);
255 u_upload_alloc(fd5_ctx
->border_color_uploader
,
256 0, FD5_BORDER_COLOR_UPLOAD_SIZE
,
257 FD5_BORDER_COLOR_UPLOAD_SIZE
, &off
,
258 &fd5_ctx
->border_color_buf
,
263 setup_border_colors(&ctx
->tex
[PIPE_SHADER_VERTEX
], &entries
[0]);
264 setup_border_colors(&ctx
->tex
[PIPE_SHADER_FRAGMENT
],
265 &entries
[ctx
->tex
[PIPE_SHADER_VERTEX
].num_samplers
]);
267 OUT_PKT4(ring
, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO
, 2);
268 OUT_RELOC(ring
, fd_resource(fd5_ctx
->border_color_buf
)->bo
, off
, 0, 0);
270 u_upload_unmap(fd5_ctx
->border_color_uploader
);
274 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
275 enum a4xx_state_block sb
, struct fd_texture_stateobj
*tex
)
277 bool needs_border
= false;
278 unsigned bcolor_offset
= (sb
== SB4_FS_TEX
) ? ctx
->tex
[PIPE_SHADER_VERTEX
].num_samplers
: 0;
281 if (tex
->num_samplers
> 0) {
282 /* output sampler state: */
283 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + (4 * tex
->num_samplers
));
284 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
285 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
286 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
287 CP_LOAD_STATE4_0_NUM_UNIT(tex
->num_samplers
));
288 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER
) |
289 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
290 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
291 for (i
= 0; i
< tex
->num_samplers
; i
++) {
292 static const struct fd5_sampler_stateobj dummy_sampler
= {};
293 const struct fd5_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
294 fd5_sampler_stateobj(tex
->samplers
[i
]) :
296 OUT_RING(ring
, sampler
->texsamp0
);
297 OUT_RING(ring
, sampler
->texsamp1
);
298 OUT_RING(ring
, sampler
->texsamp2
|
299 A5XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset
));
300 OUT_RING(ring
, sampler
->texsamp3
);
302 needs_border
|= sampler
->needs_border
;
306 if (tex
->num_textures
> 0) {
307 unsigned num_textures
= tex
->num_textures
;
309 /* emit texture state: */
310 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + (12 * num_textures
));
311 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
312 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
313 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
314 CP_LOAD_STATE4_0_NUM_UNIT(num_textures
));
315 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
) |
316 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
317 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
318 for (i
= 0; i
< tex
->num_textures
; i
++) {
319 static const struct fd5_pipe_sampler_view dummy_view
= {};
320 const struct fd5_pipe_sampler_view
*view
= tex
->textures
[i
] ?
321 fd5_pipe_sampler_view(tex
->textures
[i
]) :
324 OUT_RING(ring
, view
->texconst0
);
325 OUT_RING(ring
, view
->texconst1
);
326 OUT_RING(ring
, view
->texconst2
);
327 OUT_RING(ring
, view
->texconst3
);
328 if (view
->base
.texture
) {
329 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
330 OUT_RELOC(ring
, rsc
->bo
, view
->offset
,
331 (uint64_t)view
->texconst5
<< 32, 0);
333 OUT_RING(ring
, 0x00000000);
334 OUT_RING(ring
, view
->texconst5
);
336 OUT_RING(ring
, view
->texconst6
);
337 OUT_RING(ring
, view
->texconst7
);
338 OUT_RING(ring
, view
->texconst8
);
339 OUT_RING(ring
, view
->texconst9
);
340 OUT_RING(ring
, view
->texconst10
);
341 OUT_RING(ring
, view
->texconst11
);
349 fd5_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd5_emit
*emit
)
352 const struct fd_vertex_state
*vtx
= emit
->vtx
;
353 const struct ir3_shader_variant
*vp
= fd5_emit_get_vp(emit
);
355 for (i
= 0, j
= 0; i
<= vp
->inputs_count
; i
++) {
356 if (vp
->inputs
[i
].sysval
)
358 if (vp
->inputs
[i
].compmask
) {
359 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
360 const struct pipe_vertex_buffer
*vb
=
361 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
362 struct fd_resource
*rsc
= fd_resource(vb
->buffer
);
363 enum pipe_format pfmt
= elem
->src_format
;
364 enum a5xx_vtx_fmt fmt
= fd5_pipe2vtx(pfmt
);
365 bool isint
= util_format_is_pure_integer(pfmt
);
366 uint32_t off
= vb
->buffer_offset
+ elem
->src_offset
;
367 uint32_t size
= fd_bo_size(rsc
->bo
) - off
;
368 debug_assert(fmt
!= ~0);
370 OUT_PKT4(ring
, REG_A5XX_VFD_FETCH(j
), 4);
371 OUT_RELOC(ring
, rsc
->bo
, off
, 0, 0);
372 OUT_RING(ring
, size
); /* VFD_FETCH[j].SIZE */
373 OUT_RING(ring
, vb
->stride
); /* VFD_FETCH[j].STRIDE */
375 OUT_PKT4(ring
, REG_A5XX_VFD_DECODE(j
), 2);
376 OUT_RING(ring
, A5XX_VFD_DECODE_INSTR_IDX(j
) |
377 A5XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
378 COND(elem
->instance_divisor
, A5XX_VFD_DECODE_INSTR_INSTANCED
) |
379 A5XX_VFD_DECODE_INSTR_UNK30
|
380 COND(!isint
, A5XX_VFD_DECODE_INSTR_FLOAT
));
381 OUT_RING(ring
, MAX2(1, elem
->instance_divisor
)); /* VFD_DECODE[j].STEP_RATE */
383 OUT_PKT4(ring
, REG_A5XX_VFD_DEST_CNTL(j
), 1);
384 OUT_RING(ring
, A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
385 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp
->inputs
[i
].regid
));
391 OUT_PKT4(ring
, REG_A5XX_VFD_CONTROL_0
, 1);
392 OUT_RING(ring
, A5XX_VFD_CONTROL_0_VTXCNT(j
));
396 fd5_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
397 struct fd5_emit
*emit
)
399 const struct ir3_shader_variant
*vp
= fd5_emit_get_vp(emit
);
400 const struct ir3_shader_variant
*fp
= fd5_emit_get_fp(emit
);
401 const enum fd_dirty_3d_state dirty
= emit
->dirty
;
402 bool needs_border
= false;
404 emit_marker5(ring
, 5);
406 if ((dirty
& FD_DIRTY_FRAMEBUFFER
) && !emit
->key
.binning_pass
) {
407 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
408 unsigned char mrt_comp
[A5XX_MAX_RENDER_TARGETS
] = {0};
410 for (unsigned i
= 0; i
< A5XX_MAX_RENDER_TARGETS
; i
++) {
411 mrt_comp
[i
] = ((i
< pfb
->nr_cbufs
) && pfb
->cbufs
[i
]) ? 0xf : 0;
414 OUT_PKT4(ring
, REG_A5XX_RB_RENDER_COMPONENTS
, 1);
415 OUT_RING(ring
, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
416 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
417 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
418 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
419 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
420 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
421 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
422 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
425 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_FRAMEBUFFER
)) {
426 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
427 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
428 uint32_t rb_alpha_control
= zsa
->rb_alpha_control
;
430 if (util_format_is_pure_integer(pipe_surface_format(pfb
->cbufs
[0])))
431 rb_alpha_control
&= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST
;
433 OUT_PKT4(ring
, REG_A5XX_RB_ALPHA_CONTROL
, 1);
434 OUT_RING(ring
, rb_alpha_control
);
436 OUT_PKT4(ring
, REG_A5XX_RB_STENCIL_CONTROL
, 1);
437 OUT_RING(ring
, zsa
->rb_stencil_control
);
440 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
441 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
442 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
444 OUT_PKT4(ring
, REG_A5XX_RB_STENCILREFMASK
, 1);
445 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
446 A5XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
449 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
450 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
451 bool fragz
= fp
->has_kill
| fp
->writes_pos
;
453 OUT_PKT4(ring
, REG_A5XX_RB_DEPTH_CNTL
, 1);
454 OUT_RING(ring
, zsa
->rb_depth_cntl
);
456 OUT_PKT4(ring
, REG_A5XX_RB_DEPTH_PLANE_CNTL
, 1);
457 OUT_RING(ring
, COND(fragz
, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
) |
458 COND(fragz
&& fp
->frag_coord
, A5XX_RB_DEPTH_PLANE_CNTL_UNK1
));
460 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
461 OUT_RING(ring
, COND(fragz
, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
) |
462 COND(fragz
&& fp
->frag_coord
, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1
));
465 if (dirty
& FD_DIRTY_RASTERIZER
) {
466 struct fd5_rasterizer_stateobj
*rasterizer
=
467 fd5_rasterizer_stateobj(ctx
->rasterizer
);
469 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_CNTL
, 1);
470 OUT_RING(ring
, rasterizer
->gras_su_cntl
);
472 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_POINT_MINMAX
, 2);
473 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
474 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
476 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE
, 3);
477 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
478 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
479 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_clamp
);
482 /* NOTE: since primitive_restart is not actually part of any
483 * state object, we need to make sure that we always emit
484 * PRIM_VTX_CNTL.. either that or be more clever and detect
488 struct fd5_rasterizer_stateobj
*rast
=
489 fd5_rasterizer_stateobj(ctx
->rasterizer
);
490 uint32_t val
= rast
->pc_prim_vtx_cntl
;
492 val
|= COND(vp
->writes_psize
, A5XX_PC_PRIM_VTX_CNTL_PSIZE
);
494 OUT_PKT4(ring
, REG_A5XX_PC_PRIM_VTX_CNTL
, 1);
498 if (dirty
& FD_DIRTY_SCISSOR
) {
499 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
501 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0
, 2);
502 OUT_RING(ring
, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor
->minx
) |
503 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor
->miny
));
504 OUT_RING(ring
, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor
->maxx
- 1) |
505 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor
->maxy
- 1));
507 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0
, 2);
508 OUT_RING(ring
, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor
->minx
) |
509 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor
->miny
));
510 OUT_RING(ring
, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor
->maxx
- 1) |
511 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor
->maxy
- 1));
513 ctx
->batch
->max_scissor
.minx
= MIN2(ctx
->batch
->max_scissor
.minx
, scissor
->minx
);
514 ctx
->batch
->max_scissor
.miny
= MIN2(ctx
->batch
->max_scissor
.miny
, scissor
->miny
);
515 ctx
->batch
->max_scissor
.maxx
= MAX2(ctx
->batch
->max_scissor
.maxx
, scissor
->maxx
);
516 ctx
->batch
->max_scissor
.maxy
= MAX2(ctx
->batch
->max_scissor
.maxy
, scissor
->maxy
);
519 if (dirty
& FD_DIRTY_VIEWPORT
) {
520 fd_wfi(ctx
->batch
, ring
);
521 OUT_PKT4(ring
, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
522 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_XOFFSET_0(ctx
->viewport
.translate
[0]));
523 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_XSCALE_0(ctx
->viewport
.scale
[0]));
524 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_YOFFSET_0(ctx
->viewport
.translate
[1]));
525 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_YSCALE_0(ctx
->viewport
.scale
[1]));
526 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_ZOFFSET_0(ctx
->viewport
.translate
[2]));
527 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx
->viewport
.scale
[2]));
530 if (dirty
& FD_DIRTY_PROG
)
531 fd5_program_emit(ring
, emit
);
533 if (dirty
& (FD_DIRTY_FRAMEBUFFER
| FD_DIRTY_RASTERIZER
)) {
534 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
535 uint32_t posz_regid
= ir3_find_output_regid(fp
, FRAG_RESULT_DEPTH
);
536 unsigned nr
= pfb
->nr_cbufs
;
538 if (emit
->key
.binning_pass
)
540 else if (ctx
->rasterizer
->rasterizer_discard
)
543 OUT_PKT4(ring
, REG_A5XX_RB_FS_OUTPUT_CNTL
, 1);
544 OUT_RING(ring
, A5XX_RB_FS_OUTPUT_CNTL_MRT(nr
) |
545 COND(fp
->writes_pos
, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z
));
547 OUT_PKT4(ring
, REG_A5XX_SP_FS_OUTPUT_CNTL
, 1);
548 OUT_RING(ring
, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr
) |
549 A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid
) |
550 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
553 if (emit
->prog
== &ctx
->prog
) { /* evil hack to deal sanely with clear path */
554 ir3_emit_vs_consts(vp
, ring
, ctx
, emit
->info
);
555 if (!emit
->key
.binning_pass
)
556 ir3_emit_fs_consts(fp
, ring
, ctx
);
558 struct pipe_stream_output_info
*info
= &vp
->shader
->stream_output
;
559 if (info
->num_outputs
) {
560 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
562 for (unsigned i
= 0; i
< so
->num_targets
; i
++) {
563 struct pipe_stream_output_target
*target
= so
->targets
[i
];
568 unsigned offset
= (so
->offsets
[i
] * info
->stride
[i
] * 4) +
569 target
->buffer_offset
;
571 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_BASE_LO(i
), 3);
572 /* VPC_SO[i].BUFFER_BASE_LO: */
573 OUT_RELOCW(ring
, fd_resource(target
->buffer
)->bo
, 0, 0, 0);
574 OUT_RING(ring
, target
->buffer_size
+ offset
);
576 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(i
), 3);
577 OUT_RING(ring
, offset
);
578 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
579 // TODO just give hw a dummy addr for now.. we should
580 // be using this an then CP_MEM_TO_REG to set the
581 // VPC_SO[i].BUFFER_OFFSET for the next draw..
582 OUT_RELOCW(ring
, fd5_context(ctx
)->blit_mem
, 0x100, 0, 0);
584 emit
->streamout_mask
|= (1 << i
);
589 if ((dirty
& FD_DIRTY_BLEND
)) {
590 struct fd5_blend_stateobj
*blend
= fd5_blend_stateobj(ctx
->blend
);
593 for (i
= 0; i
< A5XX_MAX_RENDER_TARGETS
; i
++) {
594 enum pipe_format format
= pipe_surface_format(
595 ctx
->batch
->framebuffer
.cbufs
[i
]);
596 bool is_int
= util_format_is_pure_integer(format
);
597 bool has_alpha
= util_format_has_alpha(format
);
598 uint32_t control
= blend
->rb_mrt
[i
].control
;
599 uint32_t blend_control
= blend
->rb_mrt
[i
].blend_control_alpha
;
602 control
&= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
603 // control |= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
607 blend_control
|= blend
->rb_mrt
[i
].blend_control_rgb
;
609 blend_control
|= blend
->rb_mrt
[i
].blend_control_no_alpha_rgb
;
610 control
&= ~A5XX_RB_MRT_CONTROL_BLEND2
;
613 OUT_PKT4(ring
, REG_A5XX_RB_MRT_CONTROL(i
), 1);
614 OUT_RING(ring
, control
);
616 OUT_PKT4(ring
, REG_A5XX_RB_MRT_BLEND_CONTROL(i
), 1);
617 OUT_RING(ring
, blend_control
);
620 OUT_PKT4(ring
, REG_A5XX_RB_BLEND_CNTL
, 1);
621 OUT_RING(ring
, blend
->rb_blend_cntl
|
622 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(0xffff));
624 OUT_PKT4(ring
, REG_A5XX_SP_BLEND_CNTL
, 1);
625 OUT_RING(ring
, 0x00000100);
628 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
629 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
631 OUT_PKT4(ring
, REG_A5XX_RB_BLEND_RED
, 8);
632 OUT_RING(ring
, A5XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]) |
633 A5XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 0xff) |
634 A5XX_RB_BLEND_RED_SINT(bcolor
->color
[0] * 0x7f));
635 OUT_RING(ring
, A5XX_RB_BLEND_RED_F32(bcolor
->color
[0]));
636 OUT_RING(ring
, A5XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]) |
637 A5XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 0xff) |
638 A5XX_RB_BLEND_GREEN_SINT(bcolor
->color
[1] * 0x7f));
639 OUT_RING(ring
, A5XX_RB_BLEND_RED_F32(bcolor
->color
[1]));
640 OUT_RING(ring
, A5XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]) |
641 A5XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 0xff) |
642 A5XX_RB_BLEND_BLUE_SINT(bcolor
->color
[2] * 0x7f));
643 OUT_RING(ring
, A5XX_RB_BLEND_BLUE_F32(bcolor
->color
[2]));
644 OUT_RING(ring
, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]) |
645 A5XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 0xff) |
646 A5XX_RB_BLEND_ALPHA_SINT(bcolor
->color
[3] * 0x7f));
647 OUT_RING(ring
, A5XX_RB_BLEND_ALPHA_F32(bcolor
->color
[3]));
650 if (ctx
->dirty_shader
[PIPE_SHADER_VERTEX
] & FD_DIRTY_SHADER_TEX
) {
651 needs_border
|= emit_textures(ctx
, ring
, SB4_VS_TEX
,
652 &ctx
->tex
[PIPE_SHADER_VERTEX
]);
653 OUT_PKT4(ring
, REG_A5XX_TPL1_VS_TEX_COUNT
, 1);
654 OUT_RING(ring
, ctx
->tex
[PIPE_SHADER_VERTEX
].num_textures
);
657 if (ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] & FD_DIRTY_SHADER_TEX
) {
658 needs_border
|= emit_textures(ctx
, ring
, SB4_FS_TEX
,
659 &ctx
->tex
[PIPE_SHADER_FRAGMENT
]);
660 OUT_PKT4(ring
, REG_A5XX_TPL1_FS_TEX_COUNT
, 1);
661 OUT_RING(ring
, ctx
->tex
[PIPE_SHADER_FRAGMENT
].num_textures
);
665 emit_border_color(ctx
, ring
);
668 /* emit setup at begin of new cmdstream buffer (don't rely on previous
669 * state, there could have been a context switch between ioctls):
672 fd5_emit_restore(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
674 struct fd_context
*ctx
= batch
->ctx
;
676 fd5_set_render_mode(ctx
, ring
, BYPASS
);
677 fd5_cache_flush(batch
, ring
);
679 OUT_PKT4(ring
, REG_A5XX_HLSQ_UPDATE_CNTL
, 1);
680 OUT_RING(ring
, 0xfffff);
683 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
684 0000000500024048: 70d08003 00000000 001c5000 00000005
685 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
686 0000000500024058: 70d08003 00000010 001c7000 00000005
688 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
689 0000000500024068: 70268000
692 OUT_PKT4(ring
, REG_A5XX_PC_RESTART_INDEX
, 1);
693 OUT_RING(ring
, 0xffffffff);
695 OUT_PKT4(ring
, REG_A5XX_PC_RASTER_CNTL
, 1);
696 OUT_RING(ring
, 0x00000012);
698 OUT_PKT4(ring
, REG_A5XX_GRAS_LRZ_CNTL
, 1);
699 OUT_RING(ring
, 0x00000000);
701 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_POINT_MINMAX
, 2);
702 OUT_RING(ring
, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
703 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
704 OUT_RING(ring
, A5XX_GRAS_SU_POINT_SIZE(0.5));
706 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL
, 1);
707 OUT_RING(ring
, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
709 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL
, 1);
710 OUT_RING(ring
, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */
712 OUT_PKT4(ring
, REG_A5XX_SP_VS_CONFIG_MAX_CONST
, 1);
713 OUT_RING(ring
, 0); /* SP_VS_CONFIG_MAX_CONST */
715 OUT_PKT4(ring
, REG_A5XX_SP_FS_CONFIG_MAX_CONST
, 1);
716 OUT_RING(ring
, 0); /* SP_FS_CONFIG_MAX_CONST */
718 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E292
, 2);
719 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E292 */
720 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E293 */
722 OUT_PKT4(ring
, REG_A5XX_RB_MODE_CNTL
, 1);
723 OUT_RING(ring
, 0x00000044); /* RB_MODE_CNTL */
725 OUT_PKT4(ring
, REG_A5XX_RB_DBG_ECO_CNTL
, 1);
726 OUT_RING(ring
, 0x00100000); /* RB_DBG_ECO_CNTL */
728 OUT_PKT4(ring
, REG_A5XX_VFD_MODE_CNTL
, 1);
729 OUT_RING(ring
, 0x00000000); /* VFD_MODE_CNTL */
731 OUT_PKT4(ring
, REG_A5XX_PC_MODE_CNTL
, 1);
732 OUT_RING(ring
, 0x0000001f); /* PC_MODE_CNTL */
734 OUT_PKT4(ring
, REG_A5XX_SP_MODE_CNTL
, 1);
735 OUT_RING(ring
, 0x0000001e); /* SP_MODE_CNTL */
737 OUT_PKT4(ring
, REG_A5XX_SP_DBG_ECO_CNTL
, 1);
738 OUT_RING(ring
, 0x40000800); /* SP_DBG_ECO_CNTL */
740 OUT_PKT4(ring
, REG_A5XX_TPL1_MODE_CNTL
, 1);
741 OUT_RING(ring
, 0x00000544); /* TPL1_MODE_CNTL */
743 OUT_PKT4(ring
, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0
, 2);
744 OUT_RING(ring
, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */
745 OUT_RING(ring
, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */
747 OUT_PKT4(ring
, REG_A5XX_VPC_DBG_ECO_CNTL
, 1);
748 OUT_RING(ring
, 0x00000400); /* VPC_DBG_ECO_CNTL */
750 OUT_PKT4(ring
, REG_A5XX_HLSQ_MODE_CNTL
, 1);
751 OUT_RING(ring
, 0x00000001); /* HLSQ_MODE_CNTL */
753 OUT_PKT4(ring
, REG_A5XX_VPC_MODE_CNTL
, 1);
754 OUT_RING(ring
, 0x00000000); /* VPC_MODE_CNTL */
756 /* we don't use this yet.. probably best to disable.. */
757 OUT_PKT7(ring
, CP_SET_DRAW_STATE
, 3);
758 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
759 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
760 CP_SET_DRAW_STATE__0_GROUP_ID(0));
761 OUT_RING(ring
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
762 OUT_RING(ring
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
764 /* other regs not used (yet?) and always seem to have same value: */
765 OUT_PKT4(ring
, REG_A5XX_GRAS_CL_CNTL
, 1);
766 OUT_RING(ring
, 0x00000080); /* GRAS_CL_CNTL */
768 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL
, 1);
769 OUT_RING(ring
, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
771 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_BIN_CNTL
, 1);
772 OUT_RING(ring
, 0x00000000); /* GRAS_SC_BIN_CNTL */
774 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_BIN_CNTL
, 1);
775 OUT_RING(ring
, 0x00000000); /* GRAS_SC_BIN_CNTL */
777 OUT_PKT4(ring
, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL
, 1);
778 OUT_RING(ring
, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */
780 OUT_PKT4(ring
, REG_A5XX_VPC_SO_OVERRIDE
, 1);
781 OUT_RING(ring
, A5XX_VPC_SO_OVERRIDE_SO_DISABLE
);
783 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_BASE_LO(0), 3);
784 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
785 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
786 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
788 OUT_PKT4(ring
, REG_A5XX_VPC_SO_FLUSH_BASE_LO(0), 2);
789 OUT_RING(ring
, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
790 OUT_RING(ring
, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
792 OUT_PKT4(ring
, REG_A5XX_PC_GS_PARAM
, 1);
793 OUT_RING(ring
, 0x00000000); /* PC_GS_PARAM */
795 OUT_PKT4(ring
, REG_A5XX_PC_HS_PARAM
, 1);
796 OUT_RING(ring
, 0x00000000); /* PC_HS_PARAM */
798 OUT_PKT4(ring
, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL
, 1);
799 OUT_RING(ring
, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */
801 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E001
, 1);
802 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E001 */
804 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E004
, 1);
805 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E004 */
807 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E093
, 1);
808 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E093 */
810 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E1C7
, 1);
811 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E1C7 */
813 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E29A
, 1);
814 OUT_RING(ring
, 0x00ffff00); /* UNKNOWN_E29A */
816 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUF_CNTL
, 1);
817 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUF_CNTL */
819 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(0), 1);
820 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E2AB */
822 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E389
, 1);
823 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E389 */
825 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E38D
, 1);
826 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E38D */
828 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E5AB
, 1);
829 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E5AB */
831 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E5C2
, 1);
832 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E5C2 */
834 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_BASE_LO(1), 3);
835 OUT_RING(ring
, 0x00000000);
836 OUT_RING(ring
, 0x00000000);
837 OUT_RING(ring
, 0x00000000);
839 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(1), 6);
840 OUT_RING(ring
, 0x00000000);
841 OUT_RING(ring
, 0x00000000);
842 OUT_RING(ring
, 0x00000000);
843 OUT_RING(ring
, 0x00000000);
844 OUT_RING(ring
, 0x00000000);
845 OUT_RING(ring
, 0x00000000);
847 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(2), 6);
848 OUT_RING(ring
, 0x00000000);
849 OUT_RING(ring
, 0x00000000);
850 OUT_RING(ring
, 0x00000000);
851 OUT_RING(ring
, 0x00000000);
852 OUT_RING(ring
, 0x00000000);
853 OUT_RING(ring
, 0x00000000);
855 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(3), 3);
856 OUT_RING(ring
, 0x00000000);
857 OUT_RING(ring
, 0x00000000);
858 OUT_RING(ring
, 0x00000000);
860 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E5DB
, 1);
861 OUT_RING(ring
, 0x00000000);
863 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E600
, 1);
864 OUT_RING(ring
, 0x00000000);
866 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E640
, 1);
867 OUT_RING(ring
, 0x00000000);
869 OUT_PKT4(ring
, REG_A5XX_TPL1_VS_TEX_COUNT
, 4);
870 OUT_RING(ring
, 0x00000000);
871 OUT_RING(ring
, 0x00000000);
872 OUT_RING(ring
, 0x00000000);
873 OUT_RING(ring
, 0x00000000);
875 OUT_PKT4(ring
, REG_A5XX_TPL1_FS_TEX_COUNT
, 2);
876 OUT_RING(ring
, 0x00000000);
877 OUT_RING(ring
, 0x00000000);
879 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7C0
, 3);
880 OUT_RING(ring
, 0x00000000);
881 OUT_RING(ring
, 0x00000000);
882 OUT_RING(ring
, 0x00000000);
884 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7C5
, 3);
885 OUT_RING(ring
, 0x00000000);
886 OUT_RING(ring
, 0x00000000);
887 OUT_RING(ring
, 0x00000000);
889 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7CA
, 3);
890 OUT_RING(ring
, 0x00000000);
891 OUT_RING(ring
, 0x00000000);
892 OUT_RING(ring
, 0x00000000);
894 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7CF
, 3);
895 OUT_RING(ring
, 0x00000000);
896 OUT_RING(ring
, 0x00000000);
897 OUT_RING(ring
, 0x00000000);
899 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7D4
, 3);
900 OUT_RING(ring
, 0x00000000);
901 OUT_RING(ring
, 0x00000000);
902 OUT_RING(ring
, 0x00000000);
904 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7D9
, 3);
905 OUT_RING(ring
, 0x00000000);
906 OUT_RING(ring
, 0x00000000);
907 OUT_RING(ring
, 0x00000000);
909 // TODO hacks.. these should not be hardcoded:
910 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_CNTL
, 1);
911 OUT_RING(ring
, 0x00000008); /* GRAS_SC_CNTL */
915 fd5_emit_ib(struct fd_ringbuffer
*ring
, struct fd_ringbuffer
*target
)
917 __OUT_IB5(ring
, target
);
921 fd5_emit_init(struct pipe_context
*pctx
)
923 struct fd_context
*ctx
= fd_context(pctx
);
924 ctx
->emit_const
= fd5_emit_const
;
925 ctx
->emit_const_bo
= fd5_emit_const_bo
;
926 ctx
->emit_ib
= fd5_emit_ib
;