2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/u_format.h"
32 #include "util/u_viewport.h"
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
38 #include "fd5_blend.h"
39 #include "fd5_context.h"
40 #include "fd5_image.h"
41 #include "fd5_program.h"
42 #include "fd5_rasterizer.h"
43 #include "fd5_texture.h"
44 #include "fd5_format.h"
47 /* regid: base const register
48 * prsc or dwords: buffer containing constant values
49 * sizedwords: size of const value buffer
52 fd5_emit_const(struct fd_ringbuffer
*ring
, enum shader_t type
,
53 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
54 const uint32_t *dwords
, struct pipe_resource
*prsc
)
57 enum a4xx_state_src src
;
59 debug_assert((regid
% 4) == 0);
60 debug_assert((sizedwords
% 4) == 0);
70 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + sz
);
71 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(regid
/4) |
72 CP_LOAD_STATE4_0_STATE_SRC(src
) |
73 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type
)) |
74 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords
/4));
76 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
77 OUT_RELOC(ring
, bo
, offset
,
78 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
), 0);
80 OUT_RING(ring
, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
81 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
));
82 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
83 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
85 for (i
= 0; i
< sz
; i
++) {
86 OUT_RING(ring
, dwords
[i
]);
91 fd5_emit_const_bo(struct fd_ringbuffer
*ring
, enum shader_t type
, boolean write
,
92 uint32_t regid
, uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
)
94 uint32_t anum
= align(num
, 2);
97 debug_assert((regid
% 4) == 0);
99 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + (2 * anum
));
100 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(regid
/4) |
101 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
102 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type
)) |
103 CP_LOAD_STATE4_0_NUM_UNIT(anum
/2));
104 OUT_RING(ring
, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
105 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
));
106 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
108 for (i
= 0; i
< num
; i
++) {
111 OUT_RELOCW(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
113 OUT_RELOC(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
116 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
117 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
121 for (; i
< anum
; i
++) {
122 OUT_RING(ring
, 0xffffffff);
123 OUT_RING(ring
, 0xffffffff);
127 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
128 * the same as a6xx then move this somewhere common ;-)
130 * Entry layout looks like (total size, 0x60 bytes):
133 struct PACKED bcolor_entry
{
145 uint32_t z24
; /* also s8? */
149 #define FD5_BORDER_COLOR_SIZE 0x60
150 #define FD5_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD5_BORDER_COLOR_SIZE)
153 setup_border_colors(struct fd_texture_stateobj
*tex
, struct bcolor_entry
*entries
)
156 STATIC_ASSERT(sizeof(struct bcolor_entry
) == FD5_BORDER_COLOR_SIZE
);
158 for (i
= 0; i
< tex
->num_samplers
; i
++) {
159 struct bcolor_entry
*e
= &entries
[i
];
160 struct pipe_sampler_state
*sampler
= tex
->samplers
[i
];
161 union pipe_color_union
*bc
;
166 bc
= &sampler
->border_color
;
171 * The border colors need to be swizzled in a particular
172 * format-dependent order. Even though samplers don't know about
173 * formats, we can assume that with a GL state tracker, there's a
174 * 1:1 correspondence between sampler and texture. Take advantage
177 if ((i
>= tex
->num_textures
) || !tex
->textures
[i
])
180 const struct util_format_description
*desc
=
181 util_format_description(tex
->textures
[i
]->format
);
189 for (j
= 0; j
< 4; j
++) {
190 int c
= desc
->swizzle
[j
];
195 if (desc
->channel
[c
].pure_integer
) {
197 switch (desc
->channel
[c
].size
) {
199 assert(desc
->channel
[c
].type
== UTIL_FORMAT_TYPE_UNSIGNED
);
200 clamped
= CLAMP(bc
->ui
[j
], 0, 0x3);
203 if (desc
->channel
[c
].type
== UTIL_FORMAT_TYPE_SIGNED
)
204 clamped
= CLAMP(bc
->i
[j
], -128, 127);
206 clamped
= CLAMP(bc
->ui
[j
], 0, 255);
209 assert(desc
->channel
[c
].type
== UTIL_FORMAT_TYPE_UNSIGNED
);
210 clamped
= CLAMP(bc
->ui
[j
], 0, 0x3ff);
213 if (desc
->channel
[c
].type
== UTIL_FORMAT_TYPE_SIGNED
)
214 clamped
= CLAMP(bc
->i
[j
], -32768, 32767);
216 clamped
= CLAMP(bc
->ui
[j
], 0, 65535);
219 assert(!"Unexpected bit size");
224 e
->fp32
[c
] = bc
->ui
[j
];
225 e
->fp16
[c
] = clamped
;
228 float f_u
= CLAMP(f
, 0, 1);
229 float f_s
= CLAMP(f
, -1, 1);
232 e
->fp16
[c
] = util_float_to_half(f
);
233 e
->ui16
[c
] = f_u
* 0xffff;
234 e
->si16
[c
] = f_s
* 0x7fff;
235 e
->ui8
[c
] = f_u
* 0xff;
236 e
->si8
[c
] = f_s
* 0x7f;
238 e
->rgb565
|= (int)(f_u
* 0x3f) << 5;
240 e
->rgb565
|= (int)(f_u
* 0x1f) << (c
? 11 : 0);
242 e
->rgb5a1
|= (f_u
> 0.5) ? 0x8000 : 0;
244 e
->rgb5a1
|= (int)(f_u
* 0x1f) << (c
* 5);
246 e
->rgb10a2
|= (int)(f_u
* 0x3) << 30;
248 e
->rgb10a2
|= (int)(f_u
* 0x3ff) << (c
* 10);
249 e
->rgba4
|= (int)(f_u
* 0xf) << (c
* 4);
251 e
->z24
= f_u
* 0xffffff;
256 memset(&e
->__pad0
, 0, sizeof(e
->__pad0
));
257 memset(&e
->__pad1
, 0, sizeof(e
->__pad1
));
263 emit_border_color(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
)
265 struct fd5_context
*fd5_ctx
= fd5_context(ctx
);
266 struct bcolor_entry
*entries
;
270 STATIC_ASSERT(sizeof(struct bcolor_entry
) == FD5_BORDER_COLOR_SIZE
);
272 u_upload_alloc(fd5_ctx
->border_color_uploader
,
273 0, FD5_BORDER_COLOR_UPLOAD_SIZE
,
274 FD5_BORDER_COLOR_UPLOAD_SIZE
, &off
,
275 &fd5_ctx
->border_color_buf
,
280 setup_border_colors(&ctx
->tex
[PIPE_SHADER_VERTEX
], &entries
[0]);
281 setup_border_colors(&ctx
->tex
[PIPE_SHADER_FRAGMENT
],
282 &entries
[ctx
->tex
[PIPE_SHADER_VERTEX
].num_samplers
]);
284 OUT_PKT4(ring
, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO
, 2);
285 OUT_RELOC(ring
, fd_resource(fd5_ctx
->border_color_buf
)->bo
, off
, 0, 0);
287 u_upload_unmap(fd5_ctx
->border_color_uploader
);
291 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
292 enum a4xx_state_block sb
, struct fd_texture_stateobj
*tex
)
294 bool needs_border
= false;
295 unsigned bcolor_offset
= (sb
== SB4_FS_TEX
) ? ctx
->tex
[PIPE_SHADER_VERTEX
].num_samplers
: 0;
298 if (tex
->num_samplers
> 0) {
299 /* output sampler state: */
300 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + (4 * tex
->num_samplers
));
301 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
302 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
303 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
304 CP_LOAD_STATE4_0_NUM_UNIT(tex
->num_samplers
));
305 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER
) |
306 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
307 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
308 for (i
= 0; i
< tex
->num_samplers
; i
++) {
309 static const struct fd5_sampler_stateobj dummy_sampler
= {};
310 const struct fd5_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
311 fd5_sampler_stateobj(tex
->samplers
[i
]) :
313 OUT_RING(ring
, sampler
->texsamp0
);
314 OUT_RING(ring
, sampler
->texsamp1
);
315 OUT_RING(ring
, sampler
->texsamp2
|
316 A5XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset
));
317 OUT_RING(ring
, sampler
->texsamp3
);
319 needs_border
|= sampler
->needs_border
;
323 if (tex
->num_textures
> 0) {
324 unsigned num_textures
= tex
->num_textures
;
326 /* emit texture state: */
327 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + (12 * num_textures
));
328 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
329 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
330 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
331 CP_LOAD_STATE4_0_NUM_UNIT(num_textures
));
332 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
) |
333 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
334 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
335 for (i
= 0; i
< tex
->num_textures
; i
++) {
336 static const struct fd5_pipe_sampler_view dummy_view
= {};
337 const struct fd5_pipe_sampler_view
*view
= tex
->textures
[i
] ?
338 fd5_pipe_sampler_view(tex
->textures
[i
]) :
341 OUT_RING(ring
, view
->texconst0
);
342 OUT_RING(ring
, view
->texconst1
);
343 OUT_RING(ring
, view
->texconst2
);
344 OUT_RING(ring
, view
->texconst3
);
345 if (view
->base
.texture
) {
346 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
347 if (view
->base
.format
== PIPE_FORMAT_X32_S8X24_UINT
)
349 OUT_RELOC(ring
, rsc
->bo
, view
->offset
,
350 (uint64_t)view
->texconst5
<< 32, 0);
352 OUT_RING(ring
, 0x00000000);
353 OUT_RING(ring
, view
->texconst5
);
355 OUT_RING(ring
, view
->texconst6
);
356 OUT_RING(ring
, view
->texconst7
);
357 OUT_RING(ring
, view
->texconst8
);
358 OUT_RING(ring
, view
->texconst9
);
359 OUT_RING(ring
, view
->texconst10
);
360 OUT_RING(ring
, view
->texconst11
);
368 emit_ssbos(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
369 enum a4xx_state_block sb
, struct fd_shaderbuf_stateobj
*so
)
371 unsigned count
= util_last_bit(so
->enabled_mask
);
376 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + (4 * count
));
377 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
378 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
379 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
380 CP_LOAD_STATE4_0_NUM_UNIT(count
));
381 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(0) |
382 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
383 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
384 for (unsigned i
= 0; i
< count
; i
++) {
385 OUT_RING(ring
, 0x00000000);
386 OUT_RING(ring
, 0x00000000);
387 OUT_RING(ring
, 0x00000000);
388 OUT_RING(ring
, 0x00000000);
391 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + (2 * count
));
392 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
393 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
394 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
395 CP_LOAD_STATE4_0_NUM_UNIT(count
));
396 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(1) |
397 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
398 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
399 for (unsigned i
= 0; i
< count
; i
++) {
400 struct pipe_shader_buffer
*buf
= &so
->sb
[i
];
401 unsigned sz
= buf
->buffer_size
;
403 /* width is in dwords, overflows into height: */
406 OUT_RING(ring
, A5XX_SSBO_1_0_WIDTH(sz
));
407 OUT_RING(ring
, A5XX_SSBO_1_1_HEIGHT(sz
>> 16));
410 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + (2 * count
));
411 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
412 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
413 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
414 CP_LOAD_STATE4_0_NUM_UNIT(count
));
415 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(2) |
416 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
417 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
418 for (unsigned i
= 0; i
< count
; i
++) {
419 struct pipe_shader_buffer
*buf
= &so
->sb
[i
];
421 struct fd_resource
*rsc
= fd_resource(buf
->buffer
);
422 OUT_RELOCW(ring
, rsc
->bo
, buf
->buffer_offset
, 0, 0);
424 OUT_RING(ring
, 0x00000000);
425 OUT_RING(ring
, 0x00000000);
431 fd5_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd5_emit
*emit
)
434 const struct fd_vertex_state
*vtx
= emit
->vtx
;
435 const struct ir3_shader_variant
*vp
= fd5_emit_get_vp(emit
);
437 for (i
= 0, j
= 0; i
<= vp
->inputs_count
; i
++) {
438 if (vp
->inputs
[i
].sysval
)
440 if (vp
->inputs
[i
].compmask
) {
441 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
442 const struct pipe_vertex_buffer
*vb
=
443 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
444 struct fd_resource
*rsc
= fd_resource(vb
->buffer
.resource
);
445 enum pipe_format pfmt
= elem
->src_format
;
446 enum a5xx_vtx_fmt fmt
= fd5_pipe2vtx(pfmt
);
447 bool isint
= util_format_is_pure_integer(pfmt
);
448 uint32_t off
= vb
->buffer_offset
+ elem
->src_offset
;
449 uint32_t size
= fd_bo_size(rsc
->bo
) - off
;
450 debug_assert(fmt
!= ~0);
452 OUT_PKT4(ring
, REG_A5XX_VFD_FETCH(j
), 4);
453 OUT_RELOC(ring
, rsc
->bo
, off
, 0, 0);
454 OUT_RING(ring
, size
); /* VFD_FETCH[j].SIZE */
455 OUT_RING(ring
, vb
->stride
); /* VFD_FETCH[j].STRIDE */
457 OUT_PKT4(ring
, REG_A5XX_VFD_DECODE(j
), 2);
458 OUT_RING(ring
, A5XX_VFD_DECODE_INSTR_IDX(j
) |
459 A5XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
460 COND(elem
->instance_divisor
, A5XX_VFD_DECODE_INSTR_INSTANCED
) |
461 A5XX_VFD_DECODE_INSTR_SWAP(fd5_pipe2swap(pfmt
)) |
462 A5XX_VFD_DECODE_INSTR_UNK30
|
463 COND(!isint
, A5XX_VFD_DECODE_INSTR_FLOAT
));
464 OUT_RING(ring
, MAX2(1, elem
->instance_divisor
)); /* VFD_DECODE[j].STEP_RATE */
466 OUT_PKT4(ring
, REG_A5XX_VFD_DEST_CNTL(j
), 1);
467 OUT_RING(ring
, A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
468 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp
->inputs
[i
].regid
));
474 OUT_PKT4(ring
, REG_A5XX_VFD_CONTROL_0
, 1);
475 OUT_RING(ring
, A5XX_VFD_CONTROL_0_VTXCNT(j
));
479 fd5_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
480 struct fd5_emit
*emit
)
482 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
483 const struct ir3_shader_variant
*vp
= fd5_emit_get_vp(emit
);
484 const struct ir3_shader_variant
*fp
= fd5_emit_get_fp(emit
);
485 const enum fd_dirty_3d_state dirty
= emit
->dirty
;
486 bool needs_border
= false;
488 emit_marker5(ring
, 5);
490 if ((dirty
& FD_DIRTY_FRAMEBUFFER
) && !emit
->key
.binning_pass
) {
491 unsigned char mrt_comp
[A5XX_MAX_RENDER_TARGETS
] = {0};
493 for (unsigned i
= 0; i
< A5XX_MAX_RENDER_TARGETS
; i
++) {
494 mrt_comp
[i
] = ((i
< pfb
->nr_cbufs
) && pfb
->cbufs
[i
]) ? 0xf : 0;
497 OUT_PKT4(ring
, REG_A5XX_RB_RENDER_COMPONENTS
, 1);
498 OUT_RING(ring
, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
499 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
500 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
501 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
502 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
503 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
504 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
505 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
508 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_FRAMEBUFFER
)) {
509 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
510 uint32_t rb_alpha_control
= zsa
->rb_alpha_control
;
512 if (util_format_is_pure_integer(pipe_surface_format(pfb
->cbufs
[0])))
513 rb_alpha_control
&= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST
;
515 OUT_PKT4(ring
, REG_A5XX_RB_ALPHA_CONTROL
, 1);
516 OUT_RING(ring
, rb_alpha_control
);
518 OUT_PKT4(ring
, REG_A5XX_RB_STENCIL_CONTROL
, 1);
519 OUT_RING(ring
, zsa
->rb_stencil_control
);
522 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_BLEND
| FD_DIRTY_PROG
)) {
523 struct fd5_blend_stateobj
*blend
= fd5_blend_stateobj(ctx
->blend
);
524 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
527 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
528 uint32_t gras_lrz_cntl
= zsa
->gras_lrz_cntl
;
530 if (emit
->no_lrz_write
|| !rsc
->lrz
|| !rsc
->lrz_valid
)
532 else if (emit
->key
.binning_pass
&& blend
->lrz_write
&& zsa
->lrz_write
)
533 gras_lrz_cntl
|= A5XX_GRAS_LRZ_CNTL_LRZ_WRITE
;
535 OUT_PKT4(ring
, REG_A5XX_GRAS_LRZ_CNTL
, 1);
536 OUT_RING(ring
, gras_lrz_cntl
);
540 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
541 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
542 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
544 OUT_PKT4(ring
, REG_A5XX_RB_STENCILREFMASK
, 2);
545 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
546 A5XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
547 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
548 A5XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
551 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
552 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
553 bool fragz
= fp
->has_kill
| fp
->writes_pos
;
555 OUT_PKT4(ring
, REG_A5XX_RB_DEPTH_CNTL
, 1);
556 OUT_RING(ring
, zsa
->rb_depth_cntl
);
558 OUT_PKT4(ring
, REG_A5XX_RB_DEPTH_PLANE_CNTL
, 1);
559 OUT_RING(ring
, COND(fragz
, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
) |
560 COND(fragz
&& fp
->frag_coord
, A5XX_RB_DEPTH_PLANE_CNTL_UNK1
));
562 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
563 OUT_RING(ring
, COND(fragz
, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
) |
564 COND(fragz
&& fp
->frag_coord
, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1
));
567 if (dirty
& FD_DIRTY_SCISSOR
) {
568 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
570 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0
, 2);
571 OUT_RING(ring
, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor
->minx
) |
572 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor
->miny
));
573 OUT_RING(ring
, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor
->maxx
- 1) |
574 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor
->maxy
- 1));
576 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0
, 2);
577 OUT_RING(ring
, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor
->minx
) |
578 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor
->miny
));
579 OUT_RING(ring
, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor
->maxx
- 1) |
580 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor
->maxy
- 1));
582 ctx
->batch
->max_scissor
.minx
= MIN2(ctx
->batch
->max_scissor
.minx
, scissor
->minx
);
583 ctx
->batch
->max_scissor
.miny
= MIN2(ctx
->batch
->max_scissor
.miny
, scissor
->miny
);
584 ctx
->batch
->max_scissor
.maxx
= MAX2(ctx
->batch
->max_scissor
.maxx
, scissor
->maxx
);
585 ctx
->batch
->max_scissor
.maxy
= MAX2(ctx
->batch
->max_scissor
.maxy
, scissor
->maxy
);
588 if (dirty
& FD_DIRTY_VIEWPORT
) {
589 fd_wfi(ctx
->batch
, ring
);
590 OUT_PKT4(ring
, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
591 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_XOFFSET_0(ctx
->viewport
.translate
[0]));
592 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_XSCALE_0(ctx
->viewport
.scale
[0]));
593 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_YOFFSET_0(ctx
->viewport
.translate
[1]));
594 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_YSCALE_0(ctx
->viewport
.scale
[1]));
595 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_ZOFFSET_0(ctx
->viewport
.translate
[2]));
596 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx
->viewport
.scale
[2]));
599 if (dirty
& FD_DIRTY_PROG
)
600 fd5_program_emit(ctx
, ring
, emit
);
602 if (dirty
& FD_DIRTY_RASTERIZER
) {
603 struct fd5_rasterizer_stateobj
*rasterizer
=
604 fd5_rasterizer_stateobj(ctx
->rasterizer
);
606 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_CNTL
, 1);
607 OUT_RING(ring
, rasterizer
->gras_su_cntl
);
609 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_POINT_MINMAX
, 2);
610 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
611 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
613 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE
, 3);
614 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
615 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
616 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_clamp
);
618 OUT_PKT4(ring
, REG_A5XX_PC_RASTER_CNTL
, 1);
619 OUT_RING(ring
, rasterizer
->pc_raster_cntl
);
621 OUT_PKT4(ring
, REG_A5XX_GRAS_CL_CNTL
, 1);
622 OUT_RING(ring
, rasterizer
->gras_cl_clip_cntl
);
625 /* note: must come after program emit.. because there is some overlap
626 * in registers, ex. PC_PRIMITIVE_CNTL and we rely on some cached
627 * values from fd5_program_emit() to avoid having to re-emit the prog
628 * every time rast state changes.
630 * Since the primitive restart state is not part of a tracked object, we
631 * re-emit this register every time.
633 if (emit
->info
&& ctx
->rasterizer
) {
634 struct fd5_rasterizer_stateobj
*rasterizer
=
635 fd5_rasterizer_stateobj(ctx
->rasterizer
);
636 unsigned max_loc
= fd5_context(ctx
)->max_loc
;
638 OUT_PKT4(ring
, REG_A5XX_PC_PRIMITIVE_CNTL
, 1);
639 OUT_RING(ring
, rasterizer
->pc_primitive_cntl
|
640 A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(max_loc
) |
641 COND(emit
->info
->primitive_restart
&& emit
->info
->index_size
,
642 A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART
));
645 if (dirty
& (FD_DIRTY_FRAMEBUFFER
| FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
646 uint32_t posz_regid
= ir3_find_output_regid(fp
, FRAG_RESULT_DEPTH
);
647 unsigned nr
= pfb
->nr_cbufs
;
649 if (emit
->key
.binning_pass
)
651 else if (ctx
->rasterizer
->rasterizer_discard
)
654 OUT_PKT4(ring
, REG_A5XX_RB_FS_OUTPUT_CNTL
, 1);
655 OUT_RING(ring
, A5XX_RB_FS_OUTPUT_CNTL_MRT(nr
) |
656 COND(fp
->writes_pos
, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z
));
658 OUT_PKT4(ring
, REG_A5XX_SP_FS_OUTPUT_CNTL
, 1);
659 OUT_RING(ring
, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr
) |
660 A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid
) |
661 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
664 if (emit
->prog
== &ctx
->prog
) { /* evil hack to deal sanely with clear path */
665 ir3_emit_vs_consts(vp
, ring
, ctx
, emit
->info
);
666 if (!emit
->key
.binning_pass
)
667 ir3_emit_fs_consts(fp
, ring
, ctx
);
669 struct pipe_stream_output_info
*info
= &vp
->shader
->stream_output
;
670 if (info
->num_outputs
) {
671 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
673 for (unsigned i
= 0; i
< so
->num_targets
; i
++) {
674 struct pipe_stream_output_target
*target
= so
->targets
[i
];
679 unsigned offset
= (so
->offsets
[i
] * info
->stride
[i
] * 4) +
680 target
->buffer_offset
;
682 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_BASE_LO(i
), 3);
683 /* VPC_SO[i].BUFFER_BASE_LO: */
684 OUT_RELOCW(ring
, fd_resource(target
->buffer
)->bo
, 0, 0, 0);
685 OUT_RING(ring
, target
->buffer_size
+ offset
);
687 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(i
), 3);
688 OUT_RING(ring
, offset
);
689 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
690 // TODO just give hw a dummy addr for now.. we should
691 // be using this an then CP_MEM_TO_REG to set the
692 // VPC_SO[i].BUFFER_OFFSET for the next draw..
693 OUT_RELOCW(ring
, fd5_context(ctx
)->blit_mem
, 0x100, 0, 0);
695 emit
->streamout_mask
|= (1 << i
);
700 if ((dirty
& FD_DIRTY_BLEND
)) {
701 struct fd5_blend_stateobj
*blend
= fd5_blend_stateobj(ctx
->blend
);
704 for (i
= 0; i
< A5XX_MAX_RENDER_TARGETS
; i
++) {
705 enum pipe_format format
= pipe_surface_format(pfb
->cbufs
[i
]);
706 bool is_int
= util_format_is_pure_integer(format
);
707 bool has_alpha
= util_format_has_alpha(format
);
708 uint32_t control
= blend
->rb_mrt
[i
].control
;
709 uint32_t blend_control
= blend
->rb_mrt
[i
].blend_control_alpha
;
712 control
&= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
713 control
|= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
717 blend_control
|= blend
->rb_mrt
[i
].blend_control_rgb
;
719 blend_control
|= blend
->rb_mrt
[i
].blend_control_no_alpha_rgb
;
720 control
&= ~A5XX_RB_MRT_CONTROL_BLEND2
;
723 OUT_PKT4(ring
, REG_A5XX_RB_MRT_CONTROL(i
), 1);
724 OUT_RING(ring
, control
);
726 OUT_PKT4(ring
, REG_A5XX_RB_MRT_BLEND_CONTROL(i
), 1);
727 OUT_RING(ring
, blend_control
);
730 OUT_PKT4(ring
, REG_A5XX_RB_BLEND_CNTL
, 1);
731 OUT_RING(ring
, blend
->rb_blend_cntl
|
732 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(0xffff));
734 OUT_PKT4(ring
, REG_A5XX_SP_BLEND_CNTL
, 1);
735 OUT_RING(ring
, blend
->sp_blend_cntl
);
738 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
739 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
741 OUT_PKT4(ring
, REG_A5XX_RB_BLEND_RED
, 8);
742 OUT_RING(ring
, A5XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]) |
743 A5XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 0xff) |
744 A5XX_RB_BLEND_RED_SINT(bcolor
->color
[0] * 0x7f));
745 OUT_RING(ring
, A5XX_RB_BLEND_RED_F32(bcolor
->color
[0]));
746 OUT_RING(ring
, A5XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]) |
747 A5XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 0xff) |
748 A5XX_RB_BLEND_GREEN_SINT(bcolor
->color
[1] * 0x7f));
749 OUT_RING(ring
, A5XX_RB_BLEND_RED_F32(bcolor
->color
[1]));
750 OUT_RING(ring
, A5XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]) |
751 A5XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 0xff) |
752 A5XX_RB_BLEND_BLUE_SINT(bcolor
->color
[2] * 0x7f));
753 OUT_RING(ring
, A5XX_RB_BLEND_BLUE_F32(bcolor
->color
[2]));
754 OUT_RING(ring
, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]) |
755 A5XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 0xff) |
756 A5XX_RB_BLEND_ALPHA_SINT(bcolor
->color
[3] * 0x7f));
757 OUT_RING(ring
, A5XX_RB_BLEND_ALPHA_F32(bcolor
->color
[3]));
760 if (ctx
->dirty_shader
[PIPE_SHADER_VERTEX
] & FD_DIRTY_SHADER_TEX
) {
761 needs_border
|= emit_textures(ctx
, ring
, SB4_VS_TEX
,
762 &ctx
->tex
[PIPE_SHADER_VERTEX
]);
763 OUT_PKT4(ring
, REG_A5XX_TPL1_VS_TEX_COUNT
, 1);
764 OUT_RING(ring
, ctx
->tex
[PIPE_SHADER_VERTEX
].num_textures
);
767 if (ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] & FD_DIRTY_SHADER_TEX
) {
768 needs_border
|= emit_textures(ctx
, ring
, SB4_FS_TEX
,
769 &ctx
->tex
[PIPE_SHADER_FRAGMENT
]);
772 OUT_PKT4(ring
, REG_A5XX_TPL1_FS_TEX_COUNT
, 1);
773 OUT_RING(ring
, ctx
->shaderimg
[PIPE_SHADER_FRAGMENT
].enabled_mask
?
774 ~0 : ctx
->tex
[PIPE_SHADER_FRAGMENT
].num_textures
);
776 OUT_PKT4(ring
, REG_A5XX_TPL1_CS_TEX_COUNT
, 1);
780 emit_border_color(ctx
, ring
);
782 if (ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] & FD_DIRTY_SHADER_SSBO
)
783 emit_ssbos(ctx
, ring
, SB4_SSBO
, &ctx
->shaderbuf
[PIPE_SHADER_FRAGMENT
]);
785 if (ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] & FD_DIRTY_SHADER_IMAGE
)
786 fd5_emit_images(ctx
, ring
, PIPE_SHADER_FRAGMENT
);
790 fd5_emit_cs_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
791 struct ir3_shader_variant
*cp
)
793 enum fd_dirty_shader_state dirty
= ctx
->dirty_shader
[PIPE_SHADER_COMPUTE
];
795 if (dirty
& FD_DIRTY_SHADER_TEX
) {
796 bool needs_border
= false;
797 needs_border
|= emit_textures(ctx
, ring
, SB4_CS_TEX
,
798 &ctx
->tex
[PIPE_SHADER_COMPUTE
]);
801 emit_border_color(ctx
, ring
);
803 OUT_PKT4(ring
, REG_A5XX_TPL1_VS_TEX_COUNT
, 1);
806 OUT_PKT4(ring
, REG_A5XX_TPL1_HS_TEX_COUNT
, 1);
809 OUT_PKT4(ring
, REG_A5XX_TPL1_DS_TEX_COUNT
, 1);
812 OUT_PKT4(ring
, REG_A5XX_TPL1_GS_TEX_COUNT
, 1);
815 OUT_PKT4(ring
, REG_A5XX_TPL1_FS_TEX_COUNT
, 1);
819 OUT_PKT4(ring
, REG_A5XX_TPL1_CS_TEX_COUNT
, 1);
820 OUT_RING(ring
, ctx
->shaderimg
[PIPE_SHADER_COMPUTE
].enabled_mask
?
821 ~0 : ctx
->tex
[PIPE_SHADER_COMPUTE
].num_textures
);
823 if (dirty
& FD_DIRTY_SHADER_SSBO
)
824 emit_ssbos(ctx
, ring
, SB4_CS_SSBO
, &ctx
->shaderbuf
[PIPE_SHADER_COMPUTE
]);
826 if (dirty
& FD_DIRTY_SHADER_IMAGE
)
827 fd5_emit_images(ctx
, ring
, PIPE_SHADER_COMPUTE
);
830 /* emit setup at begin of new cmdstream buffer (don't rely on previous
831 * state, there could have been a context switch between ioctls):
834 fd5_emit_restore(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
836 struct fd_context
*ctx
= batch
->ctx
;
838 fd5_set_render_mode(ctx
, ring
, BYPASS
);
839 fd5_cache_flush(batch
, ring
);
841 OUT_PKT4(ring
, REG_A5XX_HLSQ_UPDATE_CNTL
, 1);
842 OUT_RING(ring
, 0xfffff);
845 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
846 0000000500024048: 70d08003 00000000 001c5000 00000005
847 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
848 0000000500024058: 70d08003 00000010 001c7000 00000005
850 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
851 0000000500024068: 70268000
854 OUT_PKT4(ring
, REG_A5XX_PC_RESTART_INDEX
, 1);
855 OUT_RING(ring
, 0xffffffff);
857 OUT_PKT4(ring
, REG_A5XX_PC_RASTER_CNTL
, 1);
858 OUT_RING(ring
, 0x00000012);
860 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_POINT_MINMAX
, 2);
861 OUT_RING(ring
, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
862 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
863 OUT_RING(ring
, A5XX_GRAS_SU_POINT_SIZE(0.5));
865 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL
, 1);
866 OUT_RING(ring
, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
868 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL
, 1);
869 OUT_RING(ring
, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */
871 OUT_PKT4(ring
, REG_A5XX_SP_VS_CONFIG_MAX_CONST
, 1);
872 OUT_RING(ring
, 0); /* SP_VS_CONFIG_MAX_CONST */
874 OUT_PKT4(ring
, REG_A5XX_SP_FS_CONFIG_MAX_CONST
, 1);
875 OUT_RING(ring
, 0); /* SP_FS_CONFIG_MAX_CONST */
877 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E292
, 2);
878 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E292 */
879 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E293 */
881 OUT_PKT4(ring
, REG_A5XX_RB_MODE_CNTL
, 1);
882 OUT_RING(ring
, 0x00000044); /* RB_MODE_CNTL */
884 OUT_PKT4(ring
, REG_A5XX_RB_DBG_ECO_CNTL
, 1);
885 OUT_RING(ring
, 0x00100000); /* RB_DBG_ECO_CNTL */
887 OUT_PKT4(ring
, REG_A5XX_VFD_MODE_CNTL
, 1);
888 OUT_RING(ring
, 0x00000000); /* VFD_MODE_CNTL */
890 OUT_PKT4(ring
, REG_A5XX_PC_MODE_CNTL
, 1);
891 OUT_RING(ring
, 0x0000001f); /* PC_MODE_CNTL */
893 OUT_PKT4(ring
, REG_A5XX_SP_MODE_CNTL
, 1);
894 OUT_RING(ring
, 0x0000001e); /* SP_MODE_CNTL */
896 OUT_PKT4(ring
, REG_A5XX_SP_DBG_ECO_CNTL
, 1);
897 OUT_RING(ring
, 0x40000800); /* SP_DBG_ECO_CNTL */
899 OUT_PKT4(ring
, REG_A5XX_TPL1_MODE_CNTL
, 1);
900 OUT_RING(ring
, 0x00000544); /* TPL1_MODE_CNTL */
902 OUT_PKT4(ring
, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0
, 2);
903 OUT_RING(ring
, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */
904 OUT_RING(ring
, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */
906 OUT_PKT4(ring
, REG_A5XX_VPC_DBG_ECO_CNTL
, 1);
907 OUT_RING(ring
, 0x00000400); /* VPC_DBG_ECO_CNTL */
909 OUT_PKT4(ring
, REG_A5XX_HLSQ_MODE_CNTL
, 1);
910 OUT_RING(ring
, 0x00000001); /* HLSQ_MODE_CNTL */
912 OUT_PKT4(ring
, REG_A5XX_VPC_MODE_CNTL
, 1);
913 OUT_RING(ring
, 0x00000000); /* VPC_MODE_CNTL */
915 /* we don't use this yet.. probably best to disable.. */
916 OUT_PKT7(ring
, CP_SET_DRAW_STATE
, 3);
917 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
918 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
919 CP_SET_DRAW_STATE__0_GROUP_ID(0));
920 OUT_RING(ring
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
921 OUT_RING(ring
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
923 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL
, 1);
924 OUT_RING(ring
, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
926 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_BIN_CNTL
, 1);
927 OUT_RING(ring
, 0x00000000); /* GRAS_SC_BIN_CNTL */
929 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_BIN_CNTL
, 1);
930 OUT_RING(ring
, 0x00000000); /* GRAS_SC_BIN_CNTL */
932 OUT_PKT4(ring
, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL
, 1);
933 OUT_RING(ring
, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */
935 OUT_PKT4(ring
, REG_A5XX_VPC_SO_OVERRIDE
, 1);
936 OUT_RING(ring
, A5XX_VPC_SO_OVERRIDE_SO_DISABLE
);
938 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_BASE_LO(0), 3);
939 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
940 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
941 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
943 OUT_PKT4(ring
, REG_A5XX_VPC_SO_FLUSH_BASE_LO(0), 2);
944 OUT_RING(ring
, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
945 OUT_RING(ring
, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
947 OUT_PKT4(ring
, REG_A5XX_PC_GS_PARAM
, 1);
948 OUT_RING(ring
, 0x00000000); /* PC_GS_PARAM */
950 OUT_PKT4(ring
, REG_A5XX_PC_HS_PARAM
, 1);
951 OUT_RING(ring
, 0x00000000); /* PC_HS_PARAM */
953 OUT_PKT4(ring
, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL
, 1);
954 OUT_RING(ring
, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */
956 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E001
, 1);
957 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E001 */
959 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E004
, 1);
960 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E004 */
962 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_LAYERED
, 1);
963 OUT_RING(ring
, 0x00000000); /* GRAS_SU_LAYERED */
965 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E29A
, 1);
966 OUT_RING(ring
, 0x00ffff00); /* UNKNOWN_E29A */
968 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUF_CNTL
, 1);
969 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUF_CNTL */
971 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(0), 1);
972 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E2AB */
974 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E389
, 1);
975 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E389 */
977 OUT_PKT4(ring
, REG_A5XX_PC_GS_LAYERED
, 1);
978 OUT_RING(ring
, 0x00000000); /* PC_GS_LAYERED */
980 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E5AB
, 1);
981 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E5AB */
983 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E5C2
, 1);
984 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E5C2 */
986 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_BASE_LO(1), 3);
987 OUT_RING(ring
, 0x00000000);
988 OUT_RING(ring
, 0x00000000);
989 OUT_RING(ring
, 0x00000000);
991 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(1), 6);
992 OUT_RING(ring
, 0x00000000);
993 OUT_RING(ring
, 0x00000000);
994 OUT_RING(ring
, 0x00000000);
995 OUT_RING(ring
, 0x00000000);
996 OUT_RING(ring
, 0x00000000);
997 OUT_RING(ring
, 0x00000000);
999 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(2), 6);
1000 OUT_RING(ring
, 0x00000000);
1001 OUT_RING(ring
, 0x00000000);
1002 OUT_RING(ring
, 0x00000000);
1003 OUT_RING(ring
, 0x00000000);
1004 OUT_RING(ring
, 0x00000000);
1005 OUT_RING(ring
, 0x00000000);
1007 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(3), 3);
1008 OUT_RING(ring
, 0x00000000);
1009 OUT_RING(ring
, 0x00000000);
1010 OUT_RING(ring
, 0x00000000);
1012 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E5DB
, 1);
1013 OUT_RING(ring
, 0x00000000);
1015 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E600
, 1);
1016 OUT_RING(ring
, 0x00000000);
1018 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E640
, 1);
1019 OUT_RING(ring
, 0x00000000);
1021 OUT_PKT4(ring
, REG_A5XX_TPL1_VS_TEX_COUNT
, 4);
1022 OUT_RING(ring
, 0x00000000);
1023 OUT_RING(ring
, 0x00000000);
1024 OUT_RING(ring
, 0x00000000);
1025 OUT_RING(ring
, 0x00000000);
1027 OUT_PKT4(ring
, REG_A5XX_TPL1_FS_TEX_COUNT
, 2);
1028 OUT_RING(ring
, 0x00000000);
1029 OUT_RING(ring
, 0x00000000);
1031 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7C0
, 3);
1032 OUT_RING(ring
, 0x00000000);
1033 OUT_RING(ring
, 0x00000000);
1034 OUT_RING(ring
, 0x00000000);
1036 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7C5
, 3);
1037 OUT_RING(ring
, 0x00000000);
1038 OUT_RING(ring
, 0x00000000);
1039 OUT_RING(ring
, 0x00000000);
1041 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7CA
, 3);
1042 OUT_RING(ring
, 0x00000000);
1043 OUT_RING(ring
, 0x00000000);
1044 OUT_RING(ring
, 0x00000000);
1046 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7CF
, 3);
1047 OUT_RING(ring
, 0x00000000);
1048 OUT_RING(ring
, 0x00000000);
1049 OUT_RING(ring
, 0x00000000);
1051 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7D4
, 3);
1052 OUT_RING(ring
, 0x00000000);
1053 OUT_RING(ring
, 0x00000000);
1054 OUT_RING(ring
, 0x00000000);
1056 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7D9
, 3);
1057 OUT_RING(ring
, 0x00000000);
1058 OUT_RING(ring
, 0x00000000);
1059 OUT_RING(ring
, 0x00000000);
1061 OUT_PKT4(ring
, REG_A5XX_RB_CLEAR_CNTL
, 1);
1062 OUT_RING(ring
, 0x00000000);
1066 fd5_emit_ib(struct fd_ringbuffer
*ring
, struct fd_ringbuffer
*target
)
1068 __OUT_IB5(ring
, target
);
1072 fd5_emit_init(struct pipe_context
*pctx
)
1074 struct fd_context
*ctx
= fd_context(pctx
);
1075 ctx
->emit_const
= fd5_emit_const
;
1076 ctx
->emit_const_bo
= fd5_emit_const_bo
;
1077 ctx
->emit_ib
= fd5_emit_ib
;