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freedreno: update generated headers
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd5_emit.h"
38 #include "fd5_blend.h"
39 #include "fd5_context.h"
40 #include "fd5_program.h"
41 #include "fd5_rasterizer.h"
42 #include "fd5_texture.h"
43 #include "fd5_format.h"
44 #include "fd5_zsa.h"
45
46 static const enum adreno_state_block sb[] = {
47 [SHADER_VERTEX] = SB_VERT_SHADER,
48 [SHADER_FRAGMENT] = SB_FRAG_SHADER,
49 };
50
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
54 */
55 static void
56 fd5_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
57 uint32_t regid, uint32_t offset, uint32_t sizedwords,
58 const uint32_t *dwords, struct pipe_resource *prsc)
59 {
60 uint32_t i, sz;
61 enum adreno_state_src src;
62
63 debug_assert((regid % 4) == 0);
64 debug_assert((sizedwords % 4) == 0);
65
66 if (prsc) {
67 sz = 0;
68 src = 0x2; // TODO ??
69 } else {
70 sz = sizedwords;
71 src = SS_DIRECT;
72 }
73
74 OUT_PKT7(ring, CP_LOAD_STATE, 3 + sz);
75 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
76 CP_LOAD_STATE_0_STATE_SRC(src) |
77 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
78 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/4));
79 if (prsc) {
80 struct fd_bo *bo = fd_resource(prsc)->bo;
81 OUT_RELOC(ring, bo, offset,
82 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
83 } else {
84 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
86 OUT_RING(ring, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
87 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
88 }
89 for (i = 0; i < sz; i++) {
90 OUT_RING(ring, dwords[i]);
91 }
92 }
93
94 static void
95 fd5_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
96 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
97 {
98 uint32_t i;
99
100 debug_assert((regid % 4) == 0);
101 debug_assert((num % 4) == 0);
102
103 OUT_PKT7(ring, CP_LOAD_STATE, 3 + num);
104 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
105 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
106 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
107 CP_LOAD_STATE_0_NUM_UNIT(num/4));
108 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
109 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
110 OUT_RING(ring, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
111
112 for (i = 0; i < num; i++) {
113 if (prscs[i]) {
114 if (write) {
115 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
116 } else {
117 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
118 }
119 } else {
120 OUT_RING(ring, 0xbad00000 | (i << 16));
121 }
122 }
123 }
124
125 static void
126 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
127 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
128 {
129 unsigned i;
130
131 if (tex->num_samplers > 0) {
132 /* output sampler state: */
133 OUT_PKT7(ring, CP_LOAD_STATE, 3 + (4 * tex->num_samplers));
134 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
135 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
136 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
137 CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
138 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
139 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
140 OUT_RING(ring, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
141 for (i = 0; i < tex->num_samplers; i++) {
142 static const struct fd5_sampler_stateobj dummy_sampler = {};
143 const struct fd5_sampler_stateobj *sampler = tex->samplers[i] ?
144 fd5_sampler_stateobj(tex->samplers[i]) :
145 &dummy_sampler;
146 OUT_RING(ring, sampler->texsamp0);
147 OUT_RING(ring, sampler->texsamp1);
148 OUT_RING(ring, sampler->texsamp2);
149 OUT_RING(ring, sampler->texsamp3);
150 }
151 }
152
153 if (tex->num_textures > 0) {
154 unsigned num_textures = tex->num_textures;
155
156 /* emit texture state: */
157 OUT_PKT7(ring, CP_LOAD_STATE, 3 + (12 * num_textures));
158 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
159 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
160 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
161 CP_LOAD_STATE_0_NUM_UNIT(num_textures));
162 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
163 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
164 OUT_RING(ring, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
165 for (i = 0; i < tex->num_textures; i++) {
166 static const struct fd5_pipe_sampler_view dummy_view = {};
167 const struct fd5_pipe_sampler_view *view = tex->textures[i] ?
168 fd5_pipe_sampler_view(tex->textures[i]) :
169 &dummy_view;
170
171 OUT_RING(ring, view->texconst0);
172 OUT_RING(ring, view->texconst1);
173 OUT_RING(ring, view->texconst2);
174 OUT_RING(ring, view->texconst3);
175 if (view->base.texture) {
176 struct fd_resource *rsc = fd_resource(view->base.texture);
177 OUT_RELOC(ring, rsc->bo, view->offset,
178 (uint64_t)view->texconst5 << 32, 0);
179 } else {
180 OUT_RING(ring, 0x00000000);
181 OUT_RING(ring, view->texconst5);
182 }
183 OUT_RING(ring, view->texconst6);
184 OUT_RING(ring, view->texconst7);
185 OUT_RING(ring, view->texconst8);
186 OUT_RING(ring, view->texconst9);
187 OUT_RING(ring, view->texconst10);
188 OUT_RING(ring, view->texconst11);
189 }
190 }
191 }
192
193 void
194 fd5_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd5_emit *emit)
195 {
196 int32_t i, j;
197 const struct fd_vertex_state *vtx = emit->vtx;
198 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
199
200 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
201 if (vp->inputs[i].sysval)
202 continue;
203 if (vp->inputs[i].compmask) {
204 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
205 const struct pipe_vertex_buffer *vb =
206 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
207 struct fd_resource *rsc = fd_resource(vb->buffer);
208 enum pipe_format pfmt = elem->src_format;
209 enum a5xx_vtx_fmt fmt = fd5_pipe2vtx(pfmt);
210 uint32_t off = vb->buffer_offset + elem->src_offset;
211 uint32_t size = fd_bo_size(rsc->bo) - off;
212 debug_assert(fmt != ~0);
213
214 OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4);
215 OUT_RELOC(ring, rsc->bo, off, 0, 0);
216 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
217 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
218
219 OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2);
220 OUT_RING(ring, A5XX_VFD_DECODE_INSTR_IDX(j) |
221 A5XX_VFD_DECODE_INSTR_FORMAT(fmt) |
222 A5XX_VFD_DECODE_INSTR_SWAP(fd5_pipe2swap(pfmt)));
223 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
224
225 OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1);
226 OUT_RING(ring, A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
227 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
228
229 j++;
230 }
231 }
232
233 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1);
234 OUT_RING(ring, A5XX_VFD_CONTROL_0_VTXCNT(j));
235 }
236
237 void
238 fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
239 struct fd5_emit *emit)
240 {
241 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
242 const struct ir3_shader_variant *fp = fd5_emit_get_fp(emit);
243 uint32_t dirty = emit->dirty;
244
245 emit_marker5(ring, 5);
246
247 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
248 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
249 unsigned char mrt_comp[A5XX_MAX_RENDER_TARGETS] = {0};
250
251 for (unsigned i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
252 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
253 }
254
255 OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1);
256 OUT_RING(ring, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
257 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
258 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
259 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
260 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
261 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
262 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
263 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
264 }
265
266 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
267 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
268 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
269 uint32_t rb_alpha_control = zsa->rb_alpha_control;
270
271 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
272 rb_alpha_control &= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST;
273
274 OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1);
275 OUT_RING(ring, rb_alpha_control);
276
277 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1);
278 OUT_RING(ring, zsa->rb_stencil_control);
279 }
280
281 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
282 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
283 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
284
285 OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 1);
286 OUT_RING(ring, zsa->rb_stencilrefmask |
287 A5XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
288 }
289
290 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
291 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
292 bool fragz = fp->has_kill | fp->writes_pos;
293
294 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_CNTL, 1);
295 OUT_RING(ring, zsa->rb_depth_cntl);
296
297 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_PLANE_CNTL, 1);
298 OUT_RING(ring, COND(fragz, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
299
300 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
301 OUT_RING(ring, COND(fragz, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
302 }
303
304 if (dirty & FD_DIRTY_RASTERIZER) {
305 struct fd5_rasterizer_stateobj *rasterizer =
306 fd5_rasterizer_stateobj(ctx->rasterizer);
307
308 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
309 OUT_RING(ring, rasterizer->gras_su_cntl);
310
311 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
312 OUT_RING(ring, rasterizer->gras_su_point_minmax);
313 OUT_RING(ring, rasterizer->gras_su_point_size);
314
315 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
316 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
317 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
318 OUT_RING(ring, rasterizer->gras_su_poly_offset_clamp);
319 }
320
321 /* NOTE: since primitive_restart is not actually part of any
322 * state object, we need to make sure that we always emit
323 * PRIM_VTX_CNTL.. either that or be more clever and detect
324 * when it changes.
325 */
326 if (emit->info) {
327 struct fd5_rasterizer_stateobj *rast =
328 fd5_rasterizer_stateobj(ctx->rasterizer);
329 uint32_t val = rast->pc_prim_vtx_cntl;
330
331 val |= COND(vp->writes_psize, A5XX_PC_PRIM_VTX_CNTL_PSIZE);
332
333 OUT_PKT4(ring, REG_A5XX_PC_PRIM_VTX_CNTL, 1);
334 OUT_RING(ring, val);
335 }
336
337 if (dirty & FD_DIRTY_SCISSOR) {
338 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
339
340 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
341 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
342 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
343 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
344 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
345
346 OUT_PKT4(ring, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
347 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
348 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
349 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
350 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
351
352 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
353 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
354 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
355 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
356 }
357
358 if (dirty & FD_DIRTY_VIEWPORT) {
359 fd_wfi(ctx->batch, ring);
360 OUT_PKT4(ring, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0, 6);
361 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
362 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
363 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
364 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
365 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
366 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
367 }
368
369 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
370 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
371 unsigned n = pfb->nr_cbufs;
372 /* if we have depth/stencil, we need at least on MRT: */
373 if (pfb->zsbuf)
374 n = MAX2(1, n);
375 fd5_program_emit(ring, emit, n, pfb->cbufs);
376 }
377
378 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
379 ir3_emit_consts(vp, ring, ctx, emit->info, dirty);
380 if (!emit->key.binning_pass)
381 ir3_emit_consts(fp, ring, ctx, emit->info, dirty);
382 }
383
384 if ((dirty & FD_DIRTY_BLEND)) {
385 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
386 uint32_t i;
387
388 for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
389 enum pipe_format format = pipe_surface_format(
390 ctx->batch->framebuffer.cbufs[i]);
391 bool is_int = util_format_is_pure_integer(format);
392 bool has_alpha = util_format_has_alpha(format);
393 uint32_t control = blend->rb_mrt[i].control;
394 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
395
396 if (is_int) {
397 control &= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
398 // control |= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
399 }
400
401 if (has_alpha) {
402 blend_control |= blend->rb_mrt[i].blend_control_rgb;
403 } else {
404 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
405 control &= ~A5XX_RB_MRT_CONTROL_BLEND2;
406 }
407
408 OUT_PKT4(ring, REG_A5XX_RB_MRT_CONTROL(i), 1);
409 OUT_RING(ring, control);
410
411 OUT_PKT4(ring, REG_A5XX_RB_MRT_BLEND_CONTROL(i), 1);
412 OUT_RING(ring, blend_control);
413 }
414
415 OUT_PKT4(ring, REG_A5XX_RB_BLEND_CNTL, 1);
416 OUT_RING(ring, blend->rb_blend_cntl |
417 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(0xffff));
418
419 OUT_PKT4(ring, REG_A5XX_SP_BLEND_CNTL, 1);
420 OUT_RING(ring, 0x00000100);
421 }
422
423 if (dirty & FD_DIRTY_BLEND_COLOR) {
424 struct pipe_blend_color *bcolor = &ctx->blend_color;
425
426 OUT_PKT4(ring, REG_A5XX_RB_BLEND_RED, 8);
427 OUT_RING(ring, A5XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
428 A5XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
429 A5XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
430 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[0]));
431 OUT_RING(ring, A5XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
432 A5XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
433 A5XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
434 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[1]));
435 OUT_RING(ring, A5XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
436 A5XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
437 A5XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
438 OUT_RING(ring, A5XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
439 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
440 A5XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
441 A5XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
442 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
443 }
444
445 if (dirty & FD_DIRTY_VERTTEX) {
446 if (vp->has_samp) {
447 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
448 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
449 OUT_RING(ring, ctx->verttex.num_textures);
450 } else {
451 dirty &= ~FD_DIRTY_VERTTEX;
452 }
453 }
454
455 if (dirty & FD_DIRTY_FRAGTEX) {
456 if (fp->has_samp) {
457 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
458 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
459 OUT_RING(ring, ctx->fragtex.num_textures);
460 } else {
461 dirty &= ~FD_DIRTY_FRAGTEX;
462 }
463 }
464
465 ctx->dirty &= ~dirty;
466 }
467
468 /* emit setup at begin of new cmdstream buffer (don't rely on previous
469 * state, there could have been a context switch between ioctls):
470 */
471 void
472 fd5_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
473 {
474 struct fd_context *ctx = batch->ctx;
475
476 fd5_set_render_mode(ctx, ring, BYPASS);
477 fd5_cache_flush(batch, ring);
478
479 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
480 OUT_RING(ring, 0xfffff);
481
482 /*
483 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
484 0000000500024048: 70d08003 00000000 001c5000 00000005
485 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
486 0000000500024058: 70d08003 00000010 001c7000 00000005
487
488 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
489 0000000500024068: 70268000
490 */
491
492 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
493 OUT_RING(ring, 0xffffffff);
494
495 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
496 OUT_RING(ring, 0x00000012);
497
498 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
499 OUT_RING(ring, 0x00000000);
500
501 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
502 OUT_RING(ring, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
503 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
504 OUT_RING(ring, A5XX_GRAS_SU_POINT_SIZE(0.5));
505
506 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
507 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
508
509 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL, 1);
510 OUT_RING(ring, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */
511
512 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG_MAX_CONST, 1);
513 OUT_RING(ring, 0); /* SP_VS_CONFIG_MAX_CONST */
514
515 OUT_PKT4(ring, REG_A5XX_SP_FS_CONFIG_MAX_CONST, 1);
516 OUT_RING(ring, 0); /* SP_FS_CONFIG_MAX_CONST */
517
518 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E292, 2);
519 OUT_RING(ring, 0x00000000); /* UNKNOWN_E292 */
520 OUT_RING(ring, 0x00000000); /* UNKNOWN_E293 */
521
522 OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1);
523 OUT_RING(ring, 0x00000044); /* RB_MODE_CNTL */
524
525 OUT_PKT4(ring, REG_A5XX_RB_DBG_ECO_CNTL, 1);
526 OUT_RING(ring, 0x00100000); /* RB_DBG_ECO_CNTL */
527
528 OUT_PKT4(ring, REG_A5XX_VFD_MODE_CNTL, 1);
529 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
530
531 OUT_PKT4(ring, REG_A5XX_PC_MODE_CNTL, 1);
532 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
533
534 OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1);
535 OUT_RING(ring, 0x0000001e); /* SP_MODE_CNTL */
536
537 OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
538 OUT_RING(ring, 0x40000800); /* SP_DBG_ECO_CNTL */
539
540 OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1);
541 OUT_RING(ring, 0x00000544); /* TPL1_MODE_CNTL */
542
543 OUT_PKT4(ring, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0, 2);
544 OUT_RING(ring, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */
545 OUT_RING(ring, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */
546
547 OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);
548 OUT_RING(ring, 0x00000400); /* VPC_DBG_ECO_CNTL */
549
550 OUT_PKT4(ring, REG_A5XX_HLSQ_MODE_CNTL, 1);
551 OUT_RING(ring, 0x00000001); /* HLSQ_MODE_CNTL */
552
553 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
554 OUT_RING(ring, 0x00000000); /* VPC_MODE_CNTL */
555
556 /* we don't use this yet.. probably best to disable.. */
557 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
558 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
559 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
560 CP_SET_DRAW_STATE__0_GROUP_ID(0));
561 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
562 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
563
564 /* other regs not used (yet?) and always seem to have same value: */
565 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
566 OUT_RING(ring, 0x00000080); /* GRAS_CL_CNTL */
567
568 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
569 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
570
571 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
572 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
573
574 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
575 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
576
577 OUT_PKT4(ring, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL, 1);
578 OUT_RING(ring, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */
579
580 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
581 OUT_RING(ring, 0x00000001); /* VPC_SO_OVERRIDE */
582
583 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO_0, 3);
584 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
585 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
586 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
587
588 OUT_PKT4(ring, REG_A5XX_VPC_SO_FLUSH_BASE_LO_0, 2);
589 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
590 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
591
592 OUT_PKT4(ring, REG_A5XX_PC_GS_PARAM, 1);
593 OUT_RING(ring, 0x00000000); /* PC_GS_PARAM */
594
595 OUT_PKT4(ring, REG_A5XX_PC_HS_PARAM, 1);
596 OUT_RING(ring, 0x00000000); /* PC_HS_PARAM */
597
598 OUT_PKT4(ring, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL, 1);
599 OUT_RING(ring, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */
600
601 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E001, 1);
602 OUT_RING(ring, 0x00000000); /* UNKNOWN_E001 */
603
604 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E004, 1);
605 OUT_RING(ring, 0x00000000); /* UNKNOWN_E004 */
606
607 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E093, 1);
608 OUT_RING(ring, 0x00000000); /* UNKNOWN_E093 */
609
610 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E1C7, 1);
611 OUT_RING(ring, 0x00000000); /* UNKNOWN_E1C7 */
612
613 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E29A, 1);
614 OUT_RING(ring, 0x00ffff00); /* UNKNOWN_E29A */
615
616 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E2A1, 1);
617 OUT_RING(ring, 0x00000000); /* UNKNOWN_E2A1 */
618
619 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E2AB, 1);
620 OUT_RING(ring, 0x00000000); /* UNKNOWN_E2AB */
621
622 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E389, 1);
623 OUT_RING(ring, 0x00000000); /* UNKNOWN_E389 */
624
625 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E38D, 1);
626 OUT_RING(ring, 0x00000000); /* UNKNOWN_E38D */
627
628 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5AB, 1);
629 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5AB */
630
631 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5C2, 1);
632 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5C2 */
633
634 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E2AE, 3);
635 OUT_RING(ring, 0x00000000);
636 OUT_RING(ring, 0x00000000);
637 OUT_RING(ring, 0x00000000);
638
639 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E2B2, 6);
640 OUT_RING(ring, 0x00000000);
641 OUT_RING(ring, 0x00000000);
642 OUT_RING(ring, 0x00000000);
643 OUT_RING(ring, 0x00000000);
644 OUT_RING(ring, 0x00000000);
645 OUT_RING(ring, 0x00000000);
646
647 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E2B9, 6);
648 OUT_RING(ring, 0x00000000);
649 OUT_RING(ring, 0x00000000);
650 OUT_RING(ring, 0x00000000);
651 OUT_RING(ring, 0x00000000);
652 OUT_RING(ring, 0x00000000);
653 OUT_RING(ring, 0x00000000);
654
655 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E2C0, 3);
656 OUT_RING(ring, 0x00000000);
657 OUT_RING(ring, 0x00000000);
658 OUT_RING(ring, 0x00000000);
659
660 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5DB, 1);
661 OUT_RING(ring, 0x00000000);
662
663 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E600, 1);
664 OUT_RING(ring, 0x00000000);
665
666 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E640, 1);
667 OUT_RING(ring, 0x00000000);
668
669 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 4);
670 OUT_RING(ring, 0x00000000);
671 OUT_RING(ring, 0x00000000);
672 OUT_RING(ring, 0x00000000);
673 OUT_RING(ring, 0x00000000);
674
675 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 2);
676 OUT_RING(ring, 0x00000000);
677 OUT_RING(ring, 0x00000000);
678
679 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C0, 3);
680 OUT_RING(ring, 0x00000000);
681 OUT_RING(ring, 0x00000000);
682 OUT_RING(ring, 0x00000000);
683
684 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C5, 3);
685 OUT_RING(ring, 0x00000000);
686 OUT_RING(ring, 0x00000000);
687 OUT_RING(ring, 0x00000000);
688
689 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CA, 3);
690 OUT_RING(ring, 0x00000000);
691 OUT_RING(ring, 0x00000000);
692 OUT_RING(ring, 0x00000000);
693
694 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CF, 3);
695 OUT_RING(ring, 0x00000000);
696 OUT_RING(ring, 0x00000000);
697 OUT_RING(ring, 0x00000000);
698
699 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D4, 3);
700 OUT_RING(ring, 0x00000000);
701 OUT_RING(ring, 0x00000000);
702 OUT_RING(ring, 0x00000000);
703
704 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D9, 3);
705 OUT_RING(ring, 0x00000000);
706 OUT_RING(ring, 0x00000000);
707 OUT_RING(ring, 0x00000000);
708
709 // TODO hacks.. these should not be hardcoded:
710 OUT_PKT4(ring, REG_A5XX_GRAS_SC_CNTL, 1);
711 OUT_RING(ring, 0x00000008); /* GRAS_SC_CNTL */
712
713 fd_hw_query_enable(batch, ring);
714 }
715
716 static void
717 fd5_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
718 {
719 __OUT_IB5(ring, target);
720 }
721
722 void
723 fd5_emit_init(struct pipe_context *pctx)
724 {
725 struct fd_context *ctx = fd_context(pctx);
726 ctx->emit_const = fd5_emit_const;
727 ctx->emit_const_bo = fd5_emit_const_bo;
728 ctx->emit_ib = fd5_emit_ib;
729 }