projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
freedreno: reorder format check
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_gmem.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/format/u_format.h"
32
33 #include "freedreno_draw.h"
34 #include "freedreno_state.h"
35 #include "freedreno_resource.h"
36
37 #include "fd5_gmem.h"
38 #include "fd5_context.h"
39 #include "fd5_draw.h"
40 #include "fd5_emit.h"
41 #include "fd5_program.h"
42 #include "fd5_format.h"
43 #include "fd5_zsa.h"
44
45 static void
46 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
47 struct pipe_surface **bufs, struct fd_gmem_stateobj *gmem)
48 {
49 enum a5xx_tile_mode tile_mode;
50 unsigned i;
51
52 for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
53 enum a5xx_color_fmt format = 0;
54 enum a3xx_color_swap swap = WZYX;
55 bool srgb = false, sint = false, uint = false;
56 struct fd_resource *rsc = NULL;
57 struct fdl_slice *slice = NULL;
58 uint32_t stride = 0;
59 uint32_t size = 0;
60 uint32_t base = 0;
61 uint32_t offset = 0;
62
63 if (gmem) {
64 tile_mode = TILE5_2;
65 } else {
66 tile_mode = TILE5_LINEAR;
67 }
68
69 if ((i < nr_bufs) && bufs[i]) {
70 struct pipe_surface *psurf = bufs[i];
71 enum pipe_format pformat = psurf->format;
72
73 rsc = fd_resource(psurf->texture);
74
75 slice = fd_resource_slice(rsc, psurf->u.tex.level);
76 format = fd5_pipe2color(pformat);
77 swap = fd5_pipe2swap(pformat);
78 srgb = util_format_is_srgb(pformat);
79 sint = util_format_is_pure_sint(pformat);
80 uint = util_format_is_pure_uint(pformat);
81
82 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
83
84 offset = fd_resource_offset(rsc, psurf->u.tex.level,
85 psurf->u.tex.first_layer);
86
87 if (gmem) {
88 stride = gmem->bin_w * gmem->cbuf_cpp[i];
89 size = stride * gmem->bin_h;
90 base = gmem->cbuf_base[i];
91 } else {
92 stride = slice->pitch * rsc->layout.cpp;
93 size = slice->size0;
94
95 tile_mode = fd_resource_tile_mode(psurf->texture, psurf->u.tex.level);
96 }
97 }
98
99 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(i), 5);
100 OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
101 A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
102 A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
103 COND(gmem, 0x800) | /* XXX 0x1000 for RECTLIST clear, 0x0 for BLIT.. */
104 COND(srgb, A5XX_RB_MRT_BUF_INFO_COLOR_SRGB));
105 OUT_RING(ring, A5XX_RB_MRT_PITCH(stride));
106 OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(size));
107 if (gmem || (i >= nr_bufs) || !bufs[i]) {
108 OUT_RING(ring, base); /* RB_MRT[i].BASE_LO */
109 OUT_RING(ring, 0x00000000); /* RB_MRT[i].BASE_HI */
110 } else {
111 debug_assert((offset + size) <= fd_bo_size(rsc->bo));
112 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* BASE_LO/HI */
113 }
114
115 OUT_PKT4(ring, REG_A5XX_SP_FS_MRT_REG(i), 1);
116 OUT_RING(ring, A5XX_SP_FS_MRT_REG_COLOR_FORMAT(format) |
117 COND(sint, A5XX_SP_FS_MRT_REG_COLOR_SINT) |
118 COND(uint, A5XX_SP_FS_MRT_REG_COLOR_UINT) |
119 COND(srgb, A5XX_SP_FS_MRT_REG_COLOR_SRGB));
120
121 /* when we support UBWC, these would be the system memory
122 * addr/pitch/etc:
123 */
124 OUT_PKT4(ring, REG_A5XX_RB_MRT_FLAG_BUFFER(i), 4);
125 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
126 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
127 OUT_RING(ring, A5XX_RB_MRT_FLAG_BUFFER_PITCH(0));
128 OUT_RING(ring, A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(0));
129 }
130 }
131
132 static void
133 emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
134 struct fd_gmem_stateobj *gmem)
135 {
136 if (zsbuf) {
137 struct fd_resource *rsc = fd_resource(zsbuf->texture);
138 enum a5xx_depth_format fmt = fd5_pipe2depth(zsbuf->format);
139 uint32_t cpp = rsc->layout.cpp;
140 uint32_t stride = 0;
141 uint32_t size = 0;
142
143 if (gmem) {
144 stride = cpp * gmem->bin_w;
145 size = stride * gmem->bin_h;
146 } else {
147 struct fdl_slice *slice = fd_resource_slice(rsc, 0);
148 stride = slice->pitch * rsc->layout.cpp;
149 size = slice->size0;
150 }
151
152 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_BUFFER_INFO, 5);
153 OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
154 if (gmem) {
155 OUT_RING(ring, gmem->zsbuf_base[0]); /* RB_DEPTH_BUFFER_BASE_LO */
156 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
157 } else {
158 OUT_RELOCW(ring, rsc->bo, 0, 0, 0); /* RB_DEPTH_BUFFER_BASE_LO/HI */
159 }
160 OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_PITCH(stride));
161 OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(size));
162
163 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
164 OUT_RING(ring, A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
165
166 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
167 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
168 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
169 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */
170
171 if (rsc->lrz) {
172 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO, 3);
173 OUT_RELOCW(ring, rsc->lrz, 0x1000, 0, 0);
174 OUT_RING(ring, A5XX_GRAS_LRZ_BUFFER_PITCH(rsc->lrz_pitch));
175
176 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO, 2);
177 OUT_RELOCW(ring, rsc->lrz, 0, 0, 0);
178 } else {
179 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO, 3);
180 OUT_RING(ring, 0x00000000);
181 OUT_RING(ring, 0x00000000);
182 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
183
184 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO, 2);
185 OUT_RING(ring, 0x00000000);
186 OUT_RING(ring, 0x00000000);
187 }
188
189 if (rsc->stencil) {
190 if (gmem) {
191 stride = 1 * gmem->bin_w;
192 size = stride * gmem->bin_h;
193 } else {
194 struct fdl_slice *slice = fd_resource_slice(rsc->stencil, 0);
195 stride = slice->pitch * rsc->layout.cpp;
196 size = slice->size0;
197 }
198
199 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 5);
200 OUT_RING(ring, A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL);
201 if (gmem) {
202 OUT_RING(ring, gmem->zsbuf_base[1]); /* RB_STENCIL_BASE_LO */
203 OUT_RING(ring, 0x00000000); /* RB_STENCIL_BASE_HI */
204 } else {
205 OUT_RELOCW(ring, rsc->stencil->bo, 0, 0, 0); /* RB_STENCIL_BASE_LO/HI */
206 }
207 OUT_RING(ring, A5XX_RB_STENCIL_PITCH(stride));
208 OUT_RING(ring, A5XX_RB_STENCIL_ARRAY_PITCH(size));
209 } else {
210 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 1);
211 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
212 }
213 } else {
214 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_BUFFER_INFO, 5);
215 OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH5_NONE));
216 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
217 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
218 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
219 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
220
221 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
222 OUT_RING(ring, A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH5_NONE));
223
224 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
225 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
226 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
227 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */
228
229 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 1);
230 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
231 }
232 }
233
234 static bool
235 use_hw_binning(struct fd_batch *batch)
236 {
237 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
238
239 if ((gmem->maxpw * gmem->maxph) > 32)
240 return false;
241
242 if ((gmem->maxpw > 15) || (gmem->maxph > 15))
243 return false;
244
245 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2) &&
246 (batch->num_draws > 0);
247 }
248
249 static void
250 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
251 {
252 unsigned i;
253 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
254 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
255 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
256 }
257 util_dynarray_clear(&batch->draw_patches);
258 }
259
260 static void
261 update_vsc_pipe(struct fd_batch *batch)
262 {
263 struct fd_context *ctx = batch->ctx;
264 struct fd5_context *fd5_ctx = fd5_context(ctx);
265 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
266 struct fd_ringbuffer *ring = batch->gmem;
267 int i;
268
269 OUT_PKT4(ring, REG_A5XX_VSC_BIN_SIZE, 3);
270 OUT_RING(ring, A5XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
271 A5XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
272 OUT_RELOCW(ring, fd5_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS_LO/HI */
273
274 OUT_PKT4(ring, REG_A5XX_UNKNOWN_0BC5, 2);
275 OUT_RING(ring, 0x00000000); /* UNKNOWN_0BC5 */
276 OUT_RING(ring, 0x00000000); /* UNKNOWN_0BC6 */
277
278 OUT_PKT4(ring, REG_A5XX_VSC_PIPE_CONFIG_REG(0), 16);
279 for (i = 0; i < 16; i++) {
280 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
281 OUT_RING(ring, A5XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
282 A5XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
283 A5XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
284 A5XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
285 }
286
287 OUT_PKT4(ring, REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(0), 32);
288 for (i = 0; i < 16; i++) {
289 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
290 if (!pipe->bo) {
291 pipe->bo = fd_bo_new(ctx->dev, 0x20000,
292 DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_pipe[%u]", i);
293 }
294 OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i].LO/HI */
295 }
296
297 OUT_PKT4(ring, REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(0), 16);
298 for (i = 0; i < 16; i++) {
299 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
300 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
301 }
302 }
303
304 static void
305 emit_binning_pass(struct fd_batch *batch)
306 {
307 struct fd_context *ctx = batch->ctx;
308 struct fd_ringbuffer *ring = batch->gmem;
309 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
310
311 uint32_t x1 = gmem->minx;
312 uint32_t y1 = gmem->miny;
313 uint32_t x2 = gmem->minx + gmem->width - 1;
314 uint32_t y2 = gmem->miny + gmem->height - 1;
315
316 fd5_set_render_mode(batch->ctx, ring, BINNING);
317
318 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
319 OUT_RING(ring, A5XX_RB_CNTL_WIDTH(gmem->bin_w) |
320 A5XX_RB_CNTL_HEIGHT(gmem->bin_h));
321
322 OUT_PKT4(ring, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
323 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
324 A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
325 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
326 A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
327
328 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
329 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(x1) |
330 A5XX_RB_RESOLVE_CNTL_1_Y(y1));
331 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(x2) |
332 A5XX_RB_RESOLVE_CNTL_2_Y(y2));
333
334 update_vsc_pipe(batch);
335
336 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
337 OUT_RING(ring, A5XX_VPC_MODE_CNTL_BINNING_PASS);
338
339 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
340 OUT_RING(ring, UNK_2C);
341
342 OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1);
343 OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(0) |
344 A5XX_RB_WINDOW_OFFSET_Y(0));
345
346 /* emit IB to binning drawcmds: */
347 fd5_emit_ib(ring, batch->binning);
348
349 fd_reset_wfi(batch);
350
351 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
352 OUT_RING(ring, UNK_2D);
353
354 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
355 OUT_RING(ring, CACHE_FLUSH_TS);
356 OUT_RELOCW(ring, fd5_context(ctx)->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
357 OUT_RING(ring, 0x00000000);
358
359 // TODO CP_COND_WRITE's for all the vsc buffers (check for overflow??)
360
361 fd_wfi(batch, ring);
362
363 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
364 OUT_RING(ring, 0x0);
365 }
366
367 /* before first tile */
368 static void
369 fd5_emit_tile_init(struct fd_batch *batch)
370 {
371 struct fd_context *ctx = batch->ctx;
372 struct fd_ringbuffer *ring = batch->gmem;
373 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
374
375 fd5_emit_restore(batch, ring);
376
377 if (batch->lrz_clear)
378 fd5_emit_ib(ring, batch->lrz_clear);
379
380 fd5_emit_lrz_flush(ring);
381
382 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
383 OUT_RING(ring, 0x00000080); /* GRAS_CL_CNTL */
384
385 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
386 OUT_RING(ring, 0x0);
387
388 OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
389 OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
390
391 OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
392 OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
393
394 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
395 fd_wfi(batch, ring);
396 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
397 OUT_RING(ring, 0x7c13c080); /* RB_CCU_CNTL */
398
399 emit_zs(ring, pfb->zsbuf, &ctx->gmem);
400 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, &ctx->gmem);
401
402 if (use_hw_binning(batch)) {
403 emit_binning_pass(batch);
404 fd5_emit_lrz_flush(ring);
405 patch_draws(batch, USE_VISIBILITY);
406 } else {
407 patch_draws(batch, IGNORE_VISIBILITY);
408 }
409
410 fd5_set_render_mode(batch->ctx, ring, GMEM);
411 }
412
413 /* before mem2gmem */
414 static void
415 fd5_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
416 {
417 struct fd_context *ctx = batch->ctx;
418 struct fd5_context *fd5_ctx = fd5_context(ctx);
419 struct fd_ringbuffer *ring = batch->gmem;
420
421 uint32_t x1 = tile->xoff;
422 uint32_t y1 = tile->yoff;
423 uint32_t x2 = tile->xoff + tile->bin_w - 1;
424 uint32_t y2 = tile->yoff + tile->bin_h - 1;
425
426 OUT_PKT4(ring, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
427 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
428 A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
429 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
430 A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
431
432 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
433 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(x1) |
434 A5XX_RB_RESOLVE_CNTL_1_Y(y1));
435 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(x2) |
436 A5XX_RB_RESOLVE_CNTL_2_Y(y2));
437
438 if (use_hw_binning(batch)) {
439 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
440
441 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
442
443 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
444 OUT_RING(ring, 0x0);
445
446 OUT_PKT7(ring, CP_SET_BIN_DATA5, 5);
447 OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
448 CP_SET_BIN_DATA5_0_VSC_N(tile->n));
449 OUT_RELOC(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE[p].DATA_ADDRESS */
450 OUT_RELOC(ring, fd5_ctx->vsc_size_mem, /* VSC_SIZE_ADDRESS + (p * 4) */
451 (tile->p * 4), 0, 0);
452 } else {
453 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
454 OUT_RING(ring, 0x1);
455 }
456
457 OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1);
458 OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(x1) |
459 A5XX_RB_WINDOW_OFFSET_Y(y1));
460 }
461
462
463 /*
464 * transfer from system memory to gmem
465 */
466
467 static void
468 emit_mem2gmem_surf(struct fd_batch *batch, uint32_t base,
469 struct pipe_surface *psurf, enum a5xx_blit_buf buf)
470 {
471 struct fd_ringbuffer *ring = batch->gmem;
472 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
473 struct fd_resource *rsc = fd_resource(psurf->texture);
474 uint32_t stride, size;
475
476 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
477
478 if (buf == BLIT_S)
479 rsc = rsc->stencil;
480
481 if ((buf == BLIT_ZS) || (buf == BLIT_S)) {
482 // XXX hack import via BLIT_MRT0 instead of BLIT_ZS, since I don't
483 // know otherwise how to go from linear in sysmem to tiled in gmem.
484 // possibly we want to flip this around gmem2mem and keep depth
485 // tiled in sysmem (and fixup sampler state to assume tiled).. this
486 // might be required for doing depth/stencil in bypass mode?
487 struct fdl_slice *slice = fd_resource_slice(rsc, 0);
488 enum a5xx_color_fmt format =
489 fd5_pipe2color(fd_gmem_restore_format(rsc->base.format));
490
491 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(0), 5);
492 OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
493 A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(rsc->layout.tile_mode) |
494 A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX));
495 OUT_RING(ring, A5XX_RB_MRT_PITCH(slice->pitch * rsc->layout.cpp));
496 OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(slice->size0));
497 OUT_RELOC(ring, rsc->bo, 0, 0, 0); /* BASE_LO/HI */
498
499 buf = BLIT_MRT0;
500 }
501
502 stride = gmem->bin_w * rsc->layout.cpp;
503 size = stride * gmem->bin_h;
504
505 OUT_PKT4(ring, REG_A5XX_RB_BLIT_FLAG_DST_LO, 4);
506 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_LO */
507 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_HI */
508 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_PITCH */
509 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_ARRAY_PITCH */
510
511 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_3, 5);
512 OUT_RING(ring, 0x00000000); /* RB_RESOLVE_CNTL_3 */
513 OUT_RING(ring, base); /* RB_BLIT_DST_LO */
514 OUT_RING(ring, 0x00000000); /* RB_BLIT_DST_HI */
515 OUT_RING(ring, A5XX_RB_BLIT_DST_PITCH(stride));
516 OUT_RING(ring, A5XX_RB_BLIT_DST_ARRAY_PITCH(size));
517
518 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
519 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(buf));
520
521 fd5_emit_blit(batch->ctx, ring);
522 }
523
524 static void
525 fd5_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
526 {
527 struct fd_ringbuffer *ring = batch->gmem;
528 struct fd_context *ctx = batch->ctx;
529 struct fd_gmem_stateobj *gmem = &ctx->gmem;
530 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
531
532 /*
533 * setup mrt and zs with system memory base addresses:
534 */
535
536 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL);
537 // emit_zs(ring, pfb->zsbuf, NULL);
538
539 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
540 OUT_RING(ring, A5XX_RB_CNTL_WIDTH(gmem->bin_w) |
541 A5XX_RB_CNTL_HEIGHT(gmem->bin_h) |
542 A5XX_RB_CNTL_BYPASS);
543
544 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
545 unsigned i;
546 for (i = 0; i < pfb->nr_cbufs; i++) {
547 if (!pfb->cbufs[i])
548 continue;
549 if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
550 continue;
551 emit_mem2gmem_surf(batch, gmem->cbuf_base[i],
552 pfb->cbufs[i], BLIT_MRT0 + i);
553 }
554 }
555
556 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
557 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
558
559 if (!rsc->stencil || fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH))
560 emit_mem2gmem_surf(batch, gmem->zsbuf_base[0], pfb->zsbuf, BLIT_ZS);
561 if (rsc->stencil && fd_gmem_needs_restore(batch, tile, FD_BUFFER_STENCIL))
562 emit_mem2gmem_surf(batch, gmem->zsbuf_base[1], pfb->zsbuf, BLIT_S);
563 }
564 }
565
566
567 /* before IB to rendering cmds: */
568 static void
569 fd5_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
570 {
571 struct fd_ringbuffer *ring = batch->gmem;
572 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
573 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
574
575 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
576 OUT_RING(ring, A5XX_RB_CNTL_WIDTH(gmem->bin_w) |
577 A5XX_RB_CNTL_HEIGHT(gmem->bin_h));
578
579 emit_zs(ring, pfb->zsbuf, gmem);
580 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem);
581
582 enum a3xx_msaa_samples samples = fd_msaa_samples(pfb->samples);
583
584 OUT_PKT4(ring, REG_A5XX_TPL1_TP_RAS_MSAA_CNTL, 2);
585 OUT_RING(ring, A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(samples));
586 OUT_RING(ring, A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
587 COND(samples == MSAA_ONE, A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
588
589 OUT_PKT4(ring, REG_A5XX_RB_RAS_MSAA_CNTL, 2);
590 OUT_RING(ring, A5XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
591 OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
592 COND(samples == MSAA_ONE, A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
593
594
595 OUT_PKT4(ring, REG_A5XX_GRAS_SC_RAS_MSAA_CNTL, 2);
596 OUT_RING(ring, A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(samples));
597 OUT_RING(ring, A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(samples) |
598 COND(samples == MSAA_ONE, A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE));
599 }
600
601
602 /*
603 * transfer from gmem to system memory (ie. normal RAM)
604 */
605
606 static void
607 emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
608 struct pipe_surface *psurf, enum a5xx_blit_buf buf)
609 {
610 struct fd_ringbuffer *ring = batch->gmem;
611 struct fd_resource *rsc = fd_resource(psurf->texture);
612 struct fdl_slice *slice;
613 bool tiled;
614 uint32_t offset;
615
616 if (!rsc->valid)
617 return;
618
619 if (buf == BLIT_S)
620 rsc = rsc->stencil;
621
622 slice = fd_resource_slice(rsc, psurf->u.tex.level);
623 offset = fd_resource_offset(rsc, psurf->u.tex.level,
624 psurf->u.tex.first_layer);
625
626 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
627
628 OUT_PKT4(ring, REG_A5XX_RB_BLIT_FLAG_DST_LO, 4);
629 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_LO */
630 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_HI */
631 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_PITCH */
632 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_ARRAY_PITCH */
633
634 tiled = fd_resource_tile_mode(psurf->texture, psurf->u.tex.level);
635
636 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_3, 5);
637 OUT_RING(ring, 0x00000004 | /* XXX RB_RESOLVE_CNTL_3 */
638 COND(tiled, A5XX_RB_RESOLVE_CNTL_3_TILED));
639 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_BLIT_DST_LO/HI */
640 OUT_RING(ring, A5XX_RB_BLIT_DST_PITCH(slice->pitch * rsc->layout.cpp));
641 OUT_RING(ring, A5XX_RB_BLIT_DST_ARRAY_PITCH(slice->size0));
642
643 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
644 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(buf));
645
646 // bool msaa_resolve = pfb->samples > 1;
647 bool msaa_resolve = false;
648 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
649 OUT_RING(ring, COND(msaa_resolve, A5XX_RB_CLEAR_CNTL_MSAA_RESOLVE));
650
651 fd5_emit_blit(batch->ctx, ring);
652 }
653
654 static void
655 fd5_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
656 {
657 struct fd_context *ctx = batch->ctx;
658 struct fd_gmem_stateobj *gmem = &ctx->gmem;
659 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
660
661 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
662 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
663
664 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH))
665 emit_gmem2mem_surf(batch, gmem->zsbuf_base[0], pfb->zsbuf, BLIT_ZS);
666 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL))
667 emit_gmem2mem_surf(batch, gmem->zsbuf_base[1], pfb->zsbuf, BLIT_S);
668 }
669
670 if (batch->resolve & FD_BUFFER_COLOR) {
671 unsigned i;
672 for (i = 0; i < pfb->nr_cbufs; i++) {
673 if (!pfb->cbufs[i])
674 continue;
675 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
676 continue;
677 emit_gmem2mem_surf(batch, gmem->cbuf_base[i],
678 pfb->cbufs[i], BLIT_MRT0 + i);
679 }
680 }
681 }
682
683 static void
684 fd5_emit_tile_fini(struct fd_batch *batch)
685 {
686 struct fd_ringbuffer *ring = batch->gmem;
687
688 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
689 OUT_RING(ring, 0x0);
690
691 fd5_emit_lrz_flush(ring);
692
693 fd5_cache_flush(batch, ring);
694 fd5_set_render_mode(batch->ctx, ring, BYPASS);
695 }
696
697 static void
698 fd5_emit_sysmem_prep(struct fd_batch *batch)
699 {
700 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
701 struct fd_ringbuffer *ring = batch->gmem;
702
703 fd5_emit_restore(batch, ring);
704
705 fd5_emit_lrz_flush(ring);
706
707 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
708 OUT_RING(ring, 0x0);
709
710 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
711 OUT_RING(ring, PC_CCU_INVALIDATE_COLOR);
712
713 OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
714 OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
715
716 OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
717 OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
718
719 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
720 fd_wfi(batch, ring);
721 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
722 OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */
723
724 OUT_PKT4(ring, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
725 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
726 A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
727 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
728 A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
729
730 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
731 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(0) |
732 A5XX_RB_RESOLVE_CNTL_1_Y(0));
733 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(pfb->width - 1) |
734 A5XX_RB_RESOLVE_CNTL_2_Y(pfb->height - 1));
735
736 OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1);
737 OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(0) |
738 A5XX_RB_WINDOW_OFFSET_Y(0));
739
740 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
741 OUT_RING(ring, 0x1);
742
743 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
744 OUT_RING(ring, A5XX_RB_CNTL_WIDTH(0) |
745 A5XX_RB_CNTL_HEIGHT(0) |
746 A5XX_RB_CNTL_BYPASS);
747
748 patch_draws(batch, IGNORE_VISIBILITY);
749
750 emit_zs(ring, pfb->zsbuf, NULL);
751 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL);
752
753 OUT_PKT4(ring, REG_A5XX_TPL1_TP_RAS_MSAA_CNTL, 2);
754 OUT_RING(ring, A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
755 OUT_RING(ring, A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
756 A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE);
757
758 OUT_PKT4(ring, REG_A5XX_RB_RAS_MSAA_CNTL, 2);
759 OUT_RING(ring, A5XX_RB_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
760 OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
761 A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE);
762
763 OUT_PKT4(ring, REG_A5XX_GRAS_SC_RAS_MSAA_CNTL, 2);
764 OUT_RING(ring, A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
765 OUT_RING(ring, A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
766 A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE);
767 }
768
769 static void
770 fd5_emit_sysmem_fini(struct fd_batch *batch)
771 {
772 struct fd5_context *fd5_ctx = fd5_context(batch->ctx);
773 struct fd_ringbuffer *ring = batch->gmem;
774
775 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
776 OUT_RING(ring, 0x0);
777
778 fd5_emit_lrz_flush(ring);
779
780 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
781 OUT_RING(ring, UNK_1D);
782 OUT_RELOCW(ring, fd5_ctx->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
783 OUT_RING(ring, 0x00000000);
784 }
785
786 void
787 fd5_gmem_init(struct pipe_context *pctx)
788 {
789 struct fd_context *ctx = fd_context(pctx);
790
791 ctx->emit_tile_init = fd5_emit_tile_init;
792 ctx->emit_tile_prep = fd5_emit_tile_prep;
793 ctx->emit_tile_mem2gmem = fd5_emit_tile_mem2gmem;
794 ctx->emit_tile_renderprep = fd5_emit_tile_renderprep;
795 ctx->emit_tile_gmem2mem = fd5_emit_tile_gmem2mem;
796 ctx->emit_tile_fini = fd5_emit_tile_fini;
797 ctx->emit_sysmem_prep = fd5_emit_sysmem_prep;
798 ctx->emit_sysmem_fini = fd5_emit_sysmem_fini;
799 }