2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/u_format.h"
33 #include "freedreno_draw.h"
34 #include "freedreno_state.h"
35 #include "freedreno_resource.h"
38 #include "fd5_context.h"
41 #include "fd5_program.h"
42 #include "fd5_format.h"
46 emit_mrt(struct fd_ringbuffer
*ring
, unsigned nr_bufs
,
47 struct pipe_surface
**bufs
, struct fd_gmem_stateobj
*gmem
)
49 enum a5xx_tile_mode tile_mode
;
55 tile_mode
= TILE5_LINEAR
;
58 for (i
= 0; i
< A5XX_MAX_RENDER_TARGETS
; i
++) {
59 enum a5xx_color_fmt format
= 0;
60 enum a3xx_color_swap swap
= WZYX
;
61 bool srgb
= false, sint
= false, uint
= false;
62 struct fd_resource
*rsc
= NULL
;
63 struct fd_resource_slice
*slice
= NULL
;
69 if ((i
< nr_bufs
) && bufs
[i
]) {
70 struct pipe_surface
*psurf
= bufs
[i
];
71 enum pipe_format pformat
= psurf
->format
;
73 rsc
= fd_resource(psurf
->texture
);
75 slice
= fd_resource_slice(rsc
, psurf
->u
.tex
.level
);
76 format
= fd5_pipe2color(pformat
);
77 swap
= fd5_pipe2swap(pformat
);
78 srgb
= util_format_is_srgb(pformat
);
79 sint
= util_format_is_pure_sint(pformat
);
80 uint
= util_format_is_pure_uint(pformat
);
82 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
84 offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
85 psurf
->u
.tex
.first_layer
);
88 stride
= gmem
->bin_w
* rsc
->cpp
;
89 size
= stride
* gmem
->bin_h
;
90 base
= gmem
->cbuf_base
[i
];
92 stride
= slice
->pitch
* rsc
->cpp
;
97 OUT_PKT4(ring
, REG_A5XX_RB_MRT_BUF_INFO(i
), 5);
98 OUT_RING(ring
, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format
) |
99 A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode
) |
100 A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap
) |
101 COND(gmem
, 0x800) | /* XXX 0x1000 for RECTLIST clear, 0x0 for BLIT.. */
102 COND(srgb
, A5XX_RB_MRT_BUF_INFO_COLOR_SRGB
));
103 OUT_RING(ring
, A5XX_RB_MRT_PITCH(stride
));
104 OUT_RING(ring
, A5XX_RB_MRT_ARRAY_PITCH(size
));
105 if (gmem
|| (i
>= nr_bufs
) || !bufs
[i
]) {
106 OUT_RING(ring
, base
); /* RB_MRT[i].BASE_LO */
107 OUT_RING(ring
, 0x00000000); /* RB_MRT[i].BASE_HI */
109 debug_assert((offset
+ size
) <= fd_bo_size(rsc
->bo
));
110 OUT_RELOCW(ring
, rsc
->bo
, offset
, 0, 0); /* BASE_LO/HI */
113 OUT_PKT4(ring
, REG_A5XX_SP_FS_MRT_REG(i
), 1);
114 OUT_RING(ring
, A5XX_SP_FS_MRT_REG_COLOR_FORMAT(format
) |
115 COND(sint
, A5XX_SP_FS_MRT_REG_COLOR_SINT
) |
116 COND(uint
, A5XX_SP_FS_MRT_REG_COLOR_UINT
) |
117 COND(srgb
, A5XX_SP_FS_MRT_REG_COLOR_SRGB
));
119 /* when we support UBWC, these would be the system memory
122 OUT_PKT4(ring
, REG_A5XX_RB_MRT_FLAG_BUFFER(i
), 4);
123 OUT_RING(ring
, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
124 OUT_RING(ring
, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
125 OUT_RING(ring
, A5XX_RB_MRT_FLAG_BUFFER_PITCH(0));
126 OUT_RING(ring
, A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(0));
131 emit_zs(struct fd_ringbuffer
*ring
, struct pipe_surface
*zsbuf
,
132 struct fd_gmem_stateobj
*gmem
)
135 struct fd_resource
*rsc
= fd_resource(zsbuf
->texture
);
136 enum a5xx_depth_format fmt
= fd5_pipe2depth(zsbuf
->format
);
137 uint32_t cpp
= rsc
->cpp
;
142 stride
= cpp
* gmem
->bin_w
;
143 size
= stride
* gmem
->bin_h
;
145 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, 0);
146 stride
= slice
->pitch
* rsc
->cpp
;
150 OUT_PKT4(ring
, REG_A5XX_RB_DEPTH_BUFFER_INFO
, 5);
151 OUT_RING(ring
, A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt
));
153 OUT_RING(ring
, gmem
->zsbuf_base
[0]); /* RB_DEPTH_BUFFER_BASE_LO */
154 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
156 OUT_RELOCW(ring
, rsc
->bo
, 0, 0, 0); /* RB_DEPTH_BUFFER_BASE_LO/HI */
158 OUT_RING(ring
, A5XX_RB_DEPTH_BUFFER_PITCH(stride
));
159 OUT_RING(ring
, A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(size
));
161 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO
, 1);
162 OUT_RING(ring
, A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt
));
164 OUT_PKT4(ring
, REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
165 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
166 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
167 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */
170 OUT_PKT4(ring
, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO
, 3);
171 OUT_RELOCW(ring
, rsc
->lrz
, 0x1000, 0, 0);
172 OUT_RING(ring
, A5XX_GRAS_LRZ_BUFFER_PITCH(rsc
->lrz_pitch
));
174 OUT_PKT4(ring
, REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO
, 2);
175 OUT_RELOCW(ring
, rsc
->lrz
, 0, 0, 0);
177 OUT_PKT4(ring
, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO
, 3);
178 OUT_RING(ring
, 0x00000000);
179 OUT_RING(ring
, 0x00000000);
180 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
182 OUT_PKT4(ring
, REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO
, 2);
183 OUT_RING(ring
, 0x00000000);
184 OUT_RING(ring
, 0x00000000);
189 stride
= 1 * gmem
->bin_w
;
190 size
= stride
* gmem
->bin_h
;
192 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
->stencil
, 0);
193 stride
= slice
->pitch
* rsc
->cpp
;
197 OUT_PKT4(ring
, REG_A5XX_RB_STENCIL_INFO
, 5);
198 OUT_RING(ring
, A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL
);
200 OUT_RING(ring
, gmem
->zsbuf_base
[1]); /* RB_STENCIL_BASE_LO */
201 OUT_RING(ring
, 0x00000000); /* RB_STENCIL_BASE_HI */
203 OUT_RELOCW(ring
, rsc
->stencil
->bo
, 0, 0, 0); /* RB_STENCIL_BASE_LO/HI */
205 OUT_RING(ring
, A5XX_RB_STENCIL_PITCH(stride
));
206 OUT_RING(ring
, A5XX_RB_STENCIL_ARRAY_PITCH(size
));
208 OUT_PKT4(ring
, REG_A5XX_RB_STENCIL_INFO
, 1);
209 OUT_RING(ring
, 0x00000000); /* RB_STENCIL_INFO */
212 OUT_PKT4(ring
, REG_A5XX_RB_DEPTH_BUFFER_INFO
, 5);
213 OUT_RING(ring
, A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH5_NONE
));
214 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
215 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
216 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
217 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
219 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO
, 1);
220 OUT_RING(ring
, A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH5_NONE
));
222 OUT_PKT4(ring
, REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
223 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
224 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
225 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */
227 OUT_PKT4(ring
, REG_A5XX_RB_STENCIL_INFO
, 1);
228 OUT_RING(ring
, 0x00000000); /* RB_STENCIL_INFO */
233 use_hw_binning(struct fd_batch
*batch
)
235 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
237 if ((gmem
->maxpw
* gmem
->maxph
) > 32)
240 if ((gmem
->maxpw
> 15) || (gmem
->maxph
> 15))
243 return fd_binning_enabled
&& ((gmem
->nbins_x
* gmem
->nbins_y
) > 2) &&
244 (batch
->num_draws
> 0);
248 patch_draws(struct fd_batch
*batch
, enum pc_di_vis_cull_mode vismode
)
251 for (i
= 0; i
< fd_patch_num_elements(&batch
->draw_patches
); i
++) {
252 struct fd_cs_patch
*patch
= fd_patch_element(&batch
->draw_patches
, i
);
253 *patch
->cs
= patch
->val
| DRAW4(0, 0, 0, vismode
);
255 util_dynarray_resize(&batch
->draw_patches
, 0);
259 update_vsc_pipe(struct fd_batch
*batch
)
261 struct fd_context
*ctx
= batch
->ctx
;
262 struct fd5_context
*fd5_ctx
= fd5_context(ctx
);
263 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
264 struct fd_ringbuffer
*ring
= batch
->gmem
;
267 OUT_PKT4(ring
, REG_A5XX_VSC_BIN_SIZE
, 3);
268 OUT_RING(ring
, A5XX_VSC_BIN_SIZE_WIDTH(gmem
->bin_w
) |
269 A5XX_VSC_BIN_SIZE_HEIGHT(gmem
->bin_h
));
270 OUT_RELOCW(ring
, fd5_ctx
->vsc_size_mem
, 0, 0, 0); /* VSC_SIZE_ADDRESS_LO/HI */
272 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_0BC5
, 2);
273 OUT_RING(ring
, 0x00000000); /* UNKNOWN_0BC5 */
274 OUT_RING(ring
, 0x00000000); /* UNKNOWN_0BC6 */
276 OUT_PKT4(ring
, REG_A5XX_VSC_PIPE_CONFIG_REG(0), 16);
277 for (i
= 0; i
< 16; i
++) {
278 struct fd_vsc_pipe
*pipe
= &ctx
->vsc_pipe
[i
];
279 OUT_RING(ring
, A5XX_VSC_PIPE_CONFIG_REG_X(pipe
->x
) |
280 A5XX_VSC_PIPE_CONFIG_REG_Y(pipe
->y
) |
281 A5XX_VSC_PIPE_CONFIG_REG_W(pipe
->w
) |
282 A5XX_VSC_PIPE_CONFIG_REG_H(pipe
->h
));
285 OUT_PKT4(ring
, REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(0), 32);
286 for (i
= 0; i
< 16; i
++) {
287 struct fd_vsc_pipe
*pipe
= &ctx
->vsc_pipe
[i
];
289 pipe
->bo
= fd_bo_new(ctx
->dev
, 0x20000,
290 DRM_FREEDRENO_GEM_TYPE_KMEM
);
292 OUT_RELOCW(ring
, pipe
->bo
, 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i].LO/HI */
295 OUT_PKT4(ring
, REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(0), 16);
296 for (i
= 0; i
< 16; i
++) {
297 struct fd_vsc_pipe
*pipe
= &ctx
->vsc_pipe
[i
];
298 OUT_RING(ring
, fd_bo_size(pipe
->bo
) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
303 emit_binning_pass(struct fd_batch
*batch
)
305 struct fd_context
*ctx
= batch
->ctx
;
306 struct fd_ringbuffer
*ring
= batch
->gmem
;
307 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
309 uint32_t x1
= gmem
->minx
;
310 uint32_t y1
= gmem
->miny
;
311 uint32_t x2
= gmem
->minx
+ gmem
->width
- 1;
312 uint32_t y2
= gmem
->miny
+ gmem
->height
- 1;
314 fd5_set_render_mode(batch
->ctx
, ring
, BINNING
);
316 OUT_PKT4(ring
, REG_A5XX_RB_CNTL
, 1);
317 OUT_RING(ring
, A5XX_RB_CNTL_WIDTH(gmem
->bin_w
) |
318 A5XX_RB_CNTL_HEIGHT(gmem
->bin_h
));
320 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
321 OUT_RING(ring
, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1
) |
322 A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1
));
323 OUT_RING(ring
, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2
) |
324 A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2
));
326 OUT_PKT4(ring
, REG_A5XX_RB_RESOLVE_CNTL_1
, 2);
327 OUT_RING(ring
, A5XX_RB_RESOLVE_CNTL_1_X(x1
) |
328 A5XX_RB_RESOLVE_CNTL_1_Y(y1
));
329 OUT_RING(ring
, A5XX_RB_RESOLVE_CNTL_2_X(x2
) |
330 A5XX_RB_RESOLVE_CNTL_2_Y(y2
));
332 update_vsc_pipe(batch
);
334 OUT_PKT4(ring
, REG_A5XX_VPC_MODE_CNTL
, 1);
335 OUT_RING(ring
, A5XX_VPC_MODE_CNTL_BINNING_PASS
);
337 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
338 OUT_RING(ring
, UNK_2C
);
340 OUT_PKT4(ring
, REG_A5XX_RB_WINDOW_OFFSET
, 1);
341 OUT_RING(ring
, A5XX_RB_WINDOW_OFFSET_X(0) |
342 A5XX_RB_WINDOW_OFFSET_Y(0));
344 /* emit IB to binning drawcmds: */
345 ctx
->emit_ib(ring
, batch
->binning
);
349 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
350 OUT_RING(ring
, UNK_2D
);
352 OUT_PKT7(ring
, CP_EVENT_WRITE
, 4);
353 OUT_RING(ring
, CACHE_FLUSH_TS
);
354 OUT_RELOCW(ring
, fd5_context(ctx
)->blit_mem
, 0, 0, 0); /* ADDR_LO/HI */
355 OUT_RING(ring
, 0x00000000);
357 // TODO CP_COND_WRITE's for all the vsc buffers (check for overflow??)
361 OUT_PKT4(ring
, REG_A5XX_VPC_MODE_CNTL
, 1);
365 /* before first tile */
367 fd5_emit_tile_init(struct fd_batch
*batch
)
369 struct fd_context
*ctx
= batch
->ctx
;
370 struct fd_ringbuffer
*ring
= batch
->gmem
;
371 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
373 fd5_emit_restore(batch
, ring
);
375 if (batch
->lrz_clear
)
376 ctx
->emit_ib(ring
, batch
->lrz_clear
);
378 fd5_emit_lrz_flush(ring
);
380 OUT_PKT4(ring
, REG_A5XX_GRAS_CL_CNTL
, 1);
381 OUT_RING(ring
, 0x00000080); /* GRAS_CL_CNTL */
383 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
386 OUT_PKT4(ring
, REG_A5XX_PC_POWER_CNTL
, 1);
387 OUT_RING(ring
, 0x00000003); /* PC_POWER_CNTL */
389 OUT_PKT4(ring
, REG_A5XX_VFD_POWER_CNTL
, 1);
390 OUT_RING(ring
, 0x00000003); /* VFD_POWER_CNTL */
392 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
394 OUT_PKT4(ring
, REG_A5XX_RB_CCU_CNTL
, 1);
395 OUT_RING(ring
, 0x7c13c080); /* RB_CCU_CNTL */
397 emit_zs(ring
, pfb
->zsbuf
, &ctx
->gmem
);
398 emit_mrt(ring
, pfb
->nr_cbufs
, pfb
->cbufs
, &ctx
->gmem
);
400 if (use_hw_binning(batch
)) {
401 emit_binning_pass(batch
);
402 fd5_emit_lrz_flush(ring
);
403 patch_draws(batch
, USE_VISIBILITY
);
405 patch_draws(batch
, IGNORE_VISIBILITY
);
408 fd5_set_render_mode(batch
->ctx
, ring
, GMEM
);
411 /* before mem2gmem */
413 fd5_emit_tile_prep(struct fd_batch
*batch
, struct fd_tile
*tile
)
415 struct fd_context
*ctx
= batch
->ctx
;
416 struct fd5_context
*fd5_ctx
= fd5_context(ctx
);
417 struct fd_ringbuffer
*ring
= batch
->gmem
;
419 uint32_t x1
= tile
->xoff
;
420 uint32_t y1
= tile
->yoff
;
421 uint32_t x2
= tile
->xoff
+ tile
->bin_w
- 1;
422 uint32_t y2
= tile
->yoff
+ tile
->bin_h
- 1;
424 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
425 OUT_RING(ring
, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1
) |
426 A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1
));
427 OUT_RING(ring
, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2
) |
428 A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2
));
430 OUT_PKT4(ring
, REG_A5XX_RB_RESOLVE_CNTL_1
, 2);
431 OUT_RING(ring
, A5XX_RB_RESOLVE_CNTL_1_X(x1
) |
432 A5XX_RB_RESOLVE_CNTL_1_Y(y1
));
433 OUT_RING(ring
, A5XX_RB_RESOLVE_CNTL_2_X(x2
) |
434 A5XX_RB_RESOLVE_CNTL_2_Y(y2
));
436 if (use_hw_binning(batch
)) {
437 struct fd_vsc_pipe
*pipe
= &ctx
->vsc_pipe
[tile
->p
];
439 OUT_PKT7(ring
, CP_WAIT_FOR_ME
, 0);
441 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
444 OUT_PKT7(ring
, CP_SET_BIN_DATA5
, 5);
445 OUT_RING(ring
, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe
->w
* pipe
->h
) |
446 CP_SET_BIN_DATA5_0_VSC_N(tile
->n
));
447 OUT_RELOC(ring
, pipe
->bo
, 0, 0, 0); /* VSC_PIPE[p].DATA_ADDRESS */
448 OUT_RELOC(ring
, fd5_ctx
->vsc_size_mem
, /* VSC_SIZE_ADDRESS + (p * 4) */
449 (tile
->p
* 4), 0, 0);
451 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
455 OUT_PKT4(ring
, REG_A5XX_RB_WINDOW_OFFSET
, 1);
456 OUT_RING(ring
, A5XX_RB_WINDOW_OFFSET_X(x1
) |
457 A5XX_RB_WINDOW_OFFSET_Y(y1
));
462 * transfer from system memory to gmem
466 emit_mem2gmem_surf(struct fd_batch
*batch
, uint32_t base
,
467 struct pipe_surface
*psurf
, enum a5xx_blit_buf buf
)
469 struct fd_ringbuffer
*ring
= batch
->gmem
;
470 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
471 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
472 uint32_t stride
, size
;
474 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
479 if ((buf
== BLIT_ZS
) || (buf
== BLIT_S
)) {
480 // XXX hack import via BLIT_MRT0 instead of BLIT_ZS, since I don't
481 // know otherwise how to go from linear in sysmem to tiled in gmem.
482 // possibly we want to flip this around gmem2mem and keep depth
483 // tiled in sysmem (and fixup sampler state to assume tiled).. this
484 // might be required for doing depth/stencil in bypass mode?
485 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, 0);
486 enum a5xx_color_fmt format
=
487 fd5_pipe2color(fd_gmem_restore_format(rsc
->base
.b
.format
));
489 OUT_PKT4(ring
, REG_A5XX_RB_MRT_BUF_INFO(0), 5);
490 OUT_RING(ring
, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format
) |
491 A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(TILE5_LINEAR
) |
492 A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX
));
493 OUT_RING(ring
, A5XX_RB_MRT_PITCH(slice
->pitch
* rsc
->cpp
));
494 OUT_RING(ring
, A5XX_RB_MRT_ARRAY_PITCH(slice
->size0
));
495 OUT_RELOC(ring
, rsc
->bo
, 0, 0, 0); /* BASE_LO/HI */
500 stride
= gmem
->bin_w
* rsc
->cpp
;
501 size
= stride
* gmem
->bin_h
;
503 OUT_PKT4(ring
, REG_A5XX_RB_BLIT_FLAG_DST_LO
, 4);
504 OUT_RING(ring
, 0x00000000); /* RB_BLIT_FLAG_DST_LO */
505 OUT_RING(ring
, 0x00000000); /* RB_BLIT_FLAG_DST_HI */
506 OUT_RING(ring
, 0x00000000); /* RB_BLIT_FLAG_DST_PITCH */
507 OUT_RING(ring
, 0x00000000); /* RB_BLIT_FLAG_DST_ARRAY_PITCH */
509 OUT_PKT4(ring
, REG_A5XX_RB_RESOLVE_CNTL_3
, 5);
510 OUT_RING(ring
, 0x00000000); /* RB_RESOLVE_CNTL_3 */
511 OUT_RING(ring
, base
); /* RB_BLIT_DST_LO */
512 OUT_RING(ring
, 0x00000000); /* RB_BLIT_DST_HI */
513 OUT_RING(ring
, A5XX_RB_BLIT_DST_PITCH(stride
));
514 OUT_RING(ring
, A5XX_RB_BLIT_DST_ARRAY_PITCH(size
));
516 OUT_PKT4(ring
, REG_A5XX_RB_BLIT_CNTL
, 1);
517 OUT_RING(ring
, A5XX_RB_BLIT_CNTL_BUF(buf
));
519 fd5_emit_blit(batch
->ctx
, ring
);
523 fd5_emit_tile_mem2gmem(struct fd_batch
*batch
, struct fd_tile
*tile
)
525 struct fd_ringbuffer
*ring
= batch
->gmem
;
526 struct fd_context
*ctx
= batch
->ctx
;
527 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
528 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
531 * setup mrt and zs with system memory base addresses:
534 emit_mrt(ring
, pfb
->nr_cbufs
, pfb
->cbufs
, NULL
);
535 // emit_zs(ring, pfb->zsbuf, NULL);
537 OUT_PKT4(ring
, REG_A5XX_RB_CNTL
, 1);
538 OUT_RING(ring
, A5XX_RB_CNTL_WIDTH(gmem
->bin_w
) |
539 A5XX_RB_CNTL_HEIGHT(gmem
->bin_h
) |
540 A5XX_RB_CNTL_BYPASS
);
542 if (fd_gmem_needs_restore(batch
, tile
, FD_BUFFER_COLOR
)) {
544 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
547 if (!(batch
->restore
& (PIPE_CLEAR_COLOR0
<< i
)))
549 emit_mem2gmem_surf(batch
, gmem
->cbuf_base
[i
],
550 pfb
->cbufs
[i
], BLIT_MRT0
+ i
);
554 if (fd_gmem_needs_restore(batch
, tile
, FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
555 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
557 if (!rsc
->stencil
|| fd_gmem_needs_restore(batch
, tile
, FD_BUFFER_DEPTH
))
558 emit_mem2gmem_surf(batch
, gmem
->zsbuf_base
[0], pfb
->zsbuf
, BLIT_ZS
);
559 if (rsc
->stencil
&& fd_gmem_needs_restore(batch
, tile
, FD_BUFFER_STENCIL
))
560 emit_mem2gmem_surf(batch
, gmem
->zsbuf_base
[1], pfb
->zsbuf
, BLIT_S
);
565 /* before IB to rendering cmds: */
567 fd5_emit_tile_renderprep(struct fd_batch
*batch
, struct fd_tile
*tile
)
569 struct fd_ringbuffer
*ring
= batch
->gmem
;
570 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
571 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
573 OUT_PKT4(ring
, REG_A5XX_RB_CNTL
, 1);
574 OUT_RING(ring
, A5XX_RB_CNTL_WIDTH(gmem
->bin_w
) |
575 A5XX_RB_CNTL_HEIGHT(gmem
->bin_h
));
577 emit_zs(ring
, pfb
->zsbuf
, gmem
);
578 emit_mrt(ring
, pfb
->nr_cbufs
, pfb
->cbufs
, gmem
);
581 OUT_PKT4(ring
, REG_A5XX_TPL1_TP_RAS_MSAA_CNTL
, 2);
582 OUT_RING(ring
, A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE
));
583 OUT_RING(ring
, A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE
) |
584 A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE
);
586 OUT_PKT4(ring
, REG_A5XX_RB_RAS_MSAA_CNTL
, 2);
587 OUT_RING(ring
, A5XX_RB_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE
));
588 OUT_RING(ring
, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE
) |
589 A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE
);
591 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_RAS_MSAA_CNTL
, 2);
592 OUT_RING(ring
, A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE
));
593 OUT_RING(ring
, A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE
) |
594 A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE
);
599 * transfer from gmem to system memory (ie. normal RAM)
603 emit_gmem2mem_surf(struct fd_batch
*batch
, uint32_t base
,
604 struct pipe_surface
*psurf
, enum a5xx_blit_buf buf
)
606 struct fd_ringbuffer
*ring
= batch
->gmem
;
607 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
608 struct fd_resource_slice
*slice
;
614 slice
= fd_resource_slice(rsc
, psurf
->u
.tex
.level
);
615 offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
616 psurf
->u
.tex
.first_layer
);
618 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
620 OUT_PKT4(ring
, REG_A5XX_RB_BLIT_FLAG_DST_LO
, 4);
621 OUT_RING(ring
, 0x00000000); /* RB_BLIT_FLAG_DST_LO */
622 OUT_RING(ring
, 0x00000000); /* RB_BLIT_FLAG_DST_HI */
623 OUT_RING(ring
, 0x00000000); /* RB_BLIT_FLAG_DST_PITCH */
624 OUT_RING(ring
, 0x00000000); /* RB_BLIT_FLAG_DST_ARRAY_PITCH */
626 OUT_PKT4(ring
, REG_A5XX_RB_RESOLVE_CNTL_3
, 5);
627 OUT_RING(ring
, 0x00000004); /* XXX RB_RESOLVE_CNTL_3 */
628 OUT_RELOCW(ring
, rsc
->bo
, offset
, 0, 0); /* RB_BLIT_DST_LO/HI */
629 OUT_RING(ring
, A5XX_RB_BLIT_DST_PITCH(slice
->pitch
* rsc
->cpp
));
630 OUT_RING(ring
, A5XX_RB_BLIT_DST_ARRAY_PITCH(slice
->size0
));
632 OUT_PKT4(ring
, REG_A5XX_RB_BLIT_CNTL
, 1);
633 OUT_RING(ring
, A5XX_RB_BLIT_CNTL_BUF(buf
));
635 fd5_emit_blit(batch
->ctx
, ring
);
639 fd5_emit_tile_gmem2mem(struct fd_batch
*batch
, struct fd_tile
*tile
)
641 struct fd_context
*ctx
= batch
->ctx
;
642 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
643 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
645 if (batch
->resolve
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
646 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
648 if (!rsc
->stencil
|| (batch
->resolve
& FD_BUFFER_DEPTH
))
649 emit_gmem2mem_surf(batch
, gmem
->zsbuf_base
[0], pfb
->zsbuf
, BLIT_ZS
);
650 if (rsc
->stencil
&& (batch
->resolve
& FD_BUFFER_STENCIL
))
651 emit_gmem2mem_surf(batch
, gmem
->zsbuf_base
[1], pfb
->zsbuf
, BLIT_S
);
654 if (batch
->resolve
& FD_BUFFER_COLOR
) {
656 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
659 if (!(batch
->resolve
& (PIPE_CLEAR_COLOR0
<< i
)))
661 emit_gmem2mem_surf(batch
, gmem
->cbuf_base
[i
],
662 pfb
->cbufs
[i
], BLIT_MRT0
+ i
);
668 fd5_emit_tile_fini(struct fd_batch
*batch
)
670 struct fd_ringbuffer
*ring
= batch
->gmem
;
672 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
675 fd5_emit_lrz_flush(ring
);
677 fd5_cache_flush(batch
, ring
);
678 fd5_set_render_mode(batch
->ctx
, ring
, BYPASS
);
682 fd5_emit_sysmem_prep(struct fd_batch
*batch
)
684 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
685 struct fd_ringbuffer
*ring
= batch
->gmem
;
687 fd5_emit_restore(batch
, ring
);
689 fd5_emit_lrz_flush(ring
);
691 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
694 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
695 OUT_RING(ring
, UNK_19
);
697 OUT_PKT4(ring
, REG_A5XX_PC_POWER_CNTL
, 1);
698 OUT_RING(ring
, 0x00000003); /* PC_POWER_CNTL */
700 OUT_PKT4(ring
, REG_A5XX_VFD_POWER_CNTL
, 1);
701 OUT_RING(ring
, 0x00000003); /* VFD_POWER_CNTL */
703 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
705 OUT_PKT4(ring
, REG_A5XX_RB_CCU_CNTL
, 1);
706 OUT_RING(ring
, 0x10000000); /* RB_CCU_CNTL */
708 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
709 OUT_RING(ring
, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
710 A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
711 OUT_RING(ring
, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb
->width
- 1) |
712 A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb
->height
- 1));
714 OUT_PKT4(ring
, REG_A5XX_RB_RESOLVE_CNTL_1
, 2);
715 OUT_RING(ring
, A5XX_RB_RESOLVE_CNTL_1_X(0) |
716 A5XX_RB_RESOLVE_CNTL_1_Y(0));
717 OUT_RING(ring
, A5XX_RB_RESOLVE_CNTL_2_X(pfb
->width
- 1) |
718 A5XX_RB_RESOLVE_CNTL_2_Y(pfb
->height
- 1));
720 OUT_PKT4(ring
, REG_A5XX_RB_WINDOW_OFFSET
, 1);
721 OUT_RING(ring
, A5XX_RB_WINDOW_OFFSET_X(0) |
722 A5XX_RB_WINDOW_OFFSET_Y(0));
724 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
727 OUT_PKT4(ring
, REG_A5XX_RB_CNTL
, 1);
728 OUT_RING(ring
, A5XX_RB_CNTL_WIDTH(0) |
729 A5XX_RB_CNTL_HEIGHT(0) |
730 A5XX_RB_CNTL_BYPASS
);
732 patch_draws(batch
, IGNORE_VISIBILITY
);
734 emit_zs(ring
, pfb
->zsbuf
, NULL
);
735 emit_mrt(ring
, pfb
->nr_cbufs
, pfb
->cbufs
, NULL
);
738 OUT_PKT4(ring
, REG_A5XX_TPL1_TP_RAS_MSAA_CNTL
, 2);
739 OUT_RING(ring
, A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE
));
740 OUT_RING(ring
, A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE
) |
741 A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE
);
743 OUT_PKT4(ring
, REG_A5XX_RB_RAS_MSAA_CNTL
, 2);
744 OUT_RING(ring
, A5XX_RB_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE
));
745 OUT_RING(ring
, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE
) |
746 A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE
);
748 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_RAS_MSAA_CNTL
, 2);
749 OUT_RING(ring
, A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE
));
750 OUT_RING(ring
, A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE
) |
751 A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE
);
755 fd5_emit_sysmem_fini(struct fd_batch
*batch
)
757 struct fd5_context
*fd5_ctx
= fd5_context(batch
->ctx
);
758 struct fd_ringbuffer
*ring
= batch
->gmem
;
760 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
763 fd5_emit_lrz_flush(ring
);
765 OUT_PKT7(ring
, CP_EVENT_WRITE
, 4);
766 OUT_RING(ring
, UNK_1D
);
767 OUT_RELOCW(ring
, fd5_ctx
->blit_mem
, 0, 0, 0); /* ADDR_LO/HI */
768 OUT_RING(ring
, 0x00000000);
772 fd5_gmem_init(struct pipe_context
*pctx
)
774 struct fd_context
*ctx
= fd_context(pctx
);
776 ctx
->emit_tile_init
= fd5_emit_tile_init
;
777 ctx
->emit_tile_prep
= fd5_emit_tile_prep
;
778 ctx
->emit_tile_mem2gmem
= fd5_emit_tile_mem2gmem
;
779 ctx
->emit_tile_renderprep
= fd5_emit_tile_renderprep
;
780 ctx
->emit_tile_gmem2mem
= fd5_emit_tile_gmem2mem
;
781 ctx
->emit_tile_fini
= fd5_emit_tile_fini
;
782 ctx
->emit_sysmem_prep
= fd5_emit_sysmem_prep
;
783 ctx
->emit_sysmem_fini
= fd5_emit_sysmem_fini
;