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b403dad5e699fe039c029132f4830be641078939
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_gmem.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/u_format.h"
32
33 #include "freedreno_draw.h"
34 #include "freedreno_state.h"
35 #include "freedreno_resource.h"
36
37 #include "fd5_gmem.h"
38 #include "fd5_context.h"
39 #include "fd5_draw.h"
40 #include "fd5_emit.h"
41 #include "fd5_program.h"
42 #include "fd5_format.h"
43 #include "fd5_zsa.h"
44
45 static void
46 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
47 struct pipe_surface **bufs, struct fd_gmem_stateobj *gmem)
48 {
49 enum a5xx_tile_mode tile_mode;
50 unsigned i;
51
52 if (gmem) {
53 tile_mode = TILE5_2;
54 } else {
55 tile_mode = TILE5_LINEAR;
56 }
57
58 for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
59 enum a5xx_color_fmt format = 0;
60 enum a3xx_color_swap swap = WZYX;
61 bool srgb = false;
62 struct fd_resource *rsc = NULL;
63 struct fd_resource_slice *slice = NULL;
64 uint32_t stride = 0;
65 uint32_t size = 0;
66 uint32_t base = 0;
67 uint32_t offset = 0;
68
69 if ((i < nr_bufs) && bufs[i]) {
70 struct pipe_surface *psurf = bufs[i];
71 enum pipe_format pformat = psurf->format;
72
73 rsc = fd_resource(psurf->texture);
74
75 slice = fd_resource_slice(rsc, psurf->u.tex.level);
76 format = fd5_pipe2color(pformat);
77 swap = fd5_pipe2swap(pformat);
78 srgb = util_format_is_srgb(pformat);
79
80 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
81
82 offset = fd_resource_offset(rsc, psurf->u.tex.level,
83 psurf->u.tex.first_layer);
84
85 if (gmem) {
86 stride = gmem->bin_w * rsc->cpp;
87 size = stride * gmem->bin_h;
88 base = gmem->cbuf_base[i];
89 } else {
90 stride = slice->pitch * rsc->cpp;
91 size = slice->size0;
92 }
93 }
94
95 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(i), 5);
96 OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
97 A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
98 A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
99 COND(gmem, 0x800) | /* XXX 0x1000 for RECTLIST clear, 0x0 for BLIT.. */
100 COND(srgb, A5XX_RB_MRT_BUF_INFO_COLOR_SRGB));
101 OUT_RING(ring, A5XX_RB_MRT_PITCH(stride));
102 OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(size));
103 if (gmem || (i >= nr_bufs) || !bufs[i]) {
104 OUT_RING(ring, base); /* RB_MRT[i].BASE_LO */
105 OUT_RING(ring, 0x00000000); /* RB_MRT[i].BASE_HI */
106 } else {
107 debug_assert((offset + size) <= fd_bo_size(rsc->bo));
108 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* BASE_LO/HI */
109 }
110
111 OUT_PKT4(ring, REG_A5XX_SP_FS_MRT_REG(i), 1);
112 OUT_RING(ring, A5XX_SP_FS_MRT_REG_COLOR_FORMAT(format) |
113 COND(srgb, A5XX_SP_FS_MRT_REG_COLOR_SRGB));
114
115 /* when we support UBWC, these would be the system memory
116 * addr/pitch/etc:
117 */
118 OUT_PKT4(ring, REG_A5XX_RB_MRT_FLAG_BUFFER(i), 4);
119 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
120 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
121 OUT_RING(ring, A5XX_RB_MRT_FLAG_BUFFER_PITCH(0));
122 OUT_RING(ring, A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(0));
123 }
124 }
125
126 static void
127 emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
128 struct fd_gmem_stateobj *gmem)
129 {
130 if (zsbuf) {
131 struct fd_resource *rsc = fd_resource(zsbuf->texture);
132 enum a5xx_depth_format fmt = fd5_pipe2depth(zsbuf->format);
133 uint32_t cpp = rsc->cpp;
134 uint32_t stride = 0;
135 uint32_t size = 0;
136
137 if (gmem) {
138 stride = cpp * gmem->bin_w;
139 size = stride * gmem->bin_h;
140 } else {
141 struct fd_resource_slice *slice = fd_resource_slice(rsc, 0);
142 stride = slice->pitch * rsc->cpp;
143 size = slice->size0;
144 }
145
146 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_BUFFER_INFO, 5);
147 OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
148 if (gmem) {
149 OUT_RING(ring, gmem->zsbuf_base[0]); /* RB_DEPTH_BUFFER_BASE_LO */
150 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
151 } else {
152 OUT_RELOCW(ring, rsc->bo, 0, 0, 0); /* RB_DEPTH_BUFFER_BASE_LO/HI */
153 }
154 OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_PITCH(stride));
155 OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(size));
156
157 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
158 OUT_RING(ring, A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
159
160 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
161 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
162 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
163 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */
164
165 if (rsc->stencil) {
166 if (gmem) {
167 stride = 1 * gmem->bin_w;
168 size = stride * gmem->bin_h;
169 } else {
170 struct fd_resource_slice *slice = fd_resource_slice(rsc->stencil, 0);
171 stride = slice->pitch * rsc->cpp;
172 size = slice->size0;
173 }
174
175 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 5);
176 OUT_RING(ring, A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL);
177 if (gmem) {
178 OUT_RING(ring, gmem->zsbuf_base[1]); /* RB_STENCIL_BASE_LO */
179 OUT_RING(ring, 0x00000000); /* RB_STENCIL_BASE_HI */
180 } else {
181 OUT_RELOCW(ring, rsc->stencil->bo, 0, 0, 0); /* RB_STENCIL_BASE_LO/HI */
182 }
183 OUT_RING(ring, A5XX_RB_STENCIL_PITCH(stride));
184 OUT_RING(ring, A5XX_RB_STENCIL_ARRAY_PITCH(size));
185 } else {
186 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 1);
187 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
188 }
189 } else {
190 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_BUFFER_INFO, 5);
191 OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH5_NONE));
192 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
193 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
194 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
195 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
196
197 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
198 OUT_RING(ring, A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH5_NONE));
199
200 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
201 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
202 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
203 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */
204
205 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 1);
206 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
207 }
208 }
209
210 static bool
211 use_hw_binning(struct fd_batch *batch)
212 {
213 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
214
215 if ((gmem->maxpw * gmem->maxph) > 32)
216 return false;
217
218 if ((gmem->maxpw > 15) || (gmem->maxph > 15))
219 return false;
220
221 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2) &&
222 (batch->num_draws > 0);
223 }
224
225 static void
226 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
227 {
228 unsigned i;
229 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
230 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
231 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
232 }
233 util_dynarray_resize(&batch->draw_patches, 0);
234 }
235
236 static void
237 update_vsc_pipe(struct fd_batch *batch)
238 {
239 struct fd_context *ctx = batch->ctx;
240 struct fd5_context *fd5_ctx = fd5_context(ctx);
241 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
242 struct fd_ringbuffer *ring = batch->gmem;
243 int i;
244
245 OUT_PKT4(ring, REG_A5XX_VSC_BIN_SIZE, 3);
246 OUT_RING(ring, A5XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
247 A5XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
248 OUT_RELOCW(ring, fd5_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS_LO/HI */
249
250 OUT_PKT4(ring, REG_A5XX_UNKNOWN_0BC5, 2);
251 OUT_RING(ring, 0x00000000); /* UNKNOWN_0BC5 */
252 OUT_RING(ring, 0x00000000); /* UNKNOWN_0BC6 */
253
254 OUT_PKT4(ring, REG_A5XX_VSC_PIPE_CONFIG_REG(0), 16);
255 for (i = 0; i < 16; i++) {
256 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
257 OUT_RING(ring, A5XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
258 A5XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
259 A5XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
260 A5XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
261 }
262
263 OUT_PKT4(ring, REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(0), 32);
264 for (i = 0; i < 16; i++) {
265 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
266 if (!pipe->bo) {
267 pipe->bo = fd_bo_new(ctx->dev, 0x20000,
268 DRM_FREEDRENO_GEM_TYPE_KMEM);
269 }
270 OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i].LO/HI */
271 }
272
273 OUT_PKT4(ring, REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(0), 16);
274 for (i = 0; i < 16; i++) {
275 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
276 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
277 }
278 }
279
280 static void
281 emit_binning_pass(struct fd_batch *batch)
282 {
283 struct fd_context *ctx = batch->ctx;
284 struct fd_ringbuffer *ring = batch->gmem;
285 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
286
287 uint32_t x1 = gmem->minx;
288 uint32_t y1 = gmem->miny;
289 uint32_t x2 = gmem->minx + gmem->width - 1;
290 uint32_t y2 = gmem->miny + gmem->height - 1;
291
292 fd5_set_render_mode(batch->ctx, ring, BINNING);
293
294 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
295 OUT_RING(ring, A5XX_RB_CNTL_WIDTH(gmem->bin_w) |
296 A5XX_RB_CNTL_HEIGHT(gmem->bin_h));
297
298 OUT_PKT4(ring, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
299 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
300 A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
301 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
302 A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
303
304 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
305 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(x1) |
306 A5XX_RB_RESOLVE_CNTL_1_Y(y1));
307 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(x2) |
308 A5XX_RB_RESOLVE_CNTL_2_Y(y2));
309
310 update_vsc_pipe(batch);
311
312 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
313 OUT_RING(ring, A5XX_VPC_MODE_CNTL_BINNING_PASS);
314
315 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
316 OUT_RING(ring, UNK_2C);
317
318 OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1);
319 OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(0) |
320 A5XX_RB_WINDOW_OFFSET_Y(0));
321
322 /* emit IB to binning drawcmds: */
323 ctx->emit_ib(ring, batch->binning);
324
325 fd_reset_wfi(batch);
326
327 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
328 OUT_RING(ring, UNK_2D);
329
330 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
331 OUT_RING(ring, CACHE_FLUSH_TS);
332 OUT_RELOCW(ring, fd5_context(ctx)->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
333 OUT_RING(ring, 0x00000000);
334
335 // TODO CP_COND_WRITE's for all the vsc buffers (check for overflow??)
336
337 fd_wfi(batch, ring);
338
339 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
340 OUT_RING(ring, 0x0);
341 }
342
343 /* before first tile */
344 static void
345 fd5_emit_tile_init(struct fd_batch *batch)
346 {
347 struct fd_ringbuffer *ring = batch->gmem;
348
349 fd5_emit_restore(batch, ring);
350
351 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
352 OUT_RING(ring, LRZ_FLUSH);
353
354 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
355 OUT_RING(ring, 0x0);
356
357 OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
358 OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
359
360 OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
361 OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
362
363 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
364 fd_wfi(batch, ring);
365 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
366 OUT_RING(ring, 0x7c13c080); /* RB_CCU_CNTL */
367
368 if (use_hw_binning(batch)) {
369 emit_binning_pass(batch);
370 patch_draws(batch, USE_VISIBILITY);
371 } else {
372 patch_draws(batch, IGNORE_VISIBILITY);
373 }
374
375 fd5_set_render_mode(batch->ctx, ring, GMEM);
376 }
377
378 /* before mem2gmem */
379 static void
380 fd5_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
381 {
382 struct fd_context *ctx = batch->ctx;
383 struct fd5_context *fd5_ctx = fd5_context(ctx);
384 struct fd_ringbuffer *ring = batch->gmem;
385
386 uint32_t x1 = tile->xoff;
387 uint32_t y1 = tile->yoff;
388 uint32_t x2 = tile->xoff + tile->bin_w - 1;
389 uint32_t y2 = tile->yoff + tile->bin_h - 1;
390
391 OUT_PKT4(ring, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
392 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
393 A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
394 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
395 A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
396
397 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
398 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(x1) |
399 A5XX_RB_RESOLVE_CNTL_1_Y(y1));
400 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(x2) |
401 A5XX_RB_RESOLVE_CNTL_2_Y(y2));
402
403 if (use_hw_binning(batch)) {
404 struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
405
406 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
407
408 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
409 OUT_RING(ring, 0x0);
410
411 OUT_PKT7(ring, CP_SET_BIN_DATA5, 5);
412 OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
413 CP_SET_BIN_DATA5_0_VSC_N(tile->n));
414 OUT_RELOC(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE[p].DATA_ADDRESS */
415 OUT_RELOC(ring, fd5_ctx->vsc_size_mem, /* VSC_SIZE_ADDRESS + (p * 4) */
416 (tile->p * 4), 0, 0);
417 } else {
418 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
419 OUT_RING(ring, 0x1);
420 }
421
422 OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1);
423 OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(x1) |
424 A5XX_RB_WINDOW_OFFSET_Y(y1));
425 }
426
427
428 /*
429 * transfer from system memory to gmem
430 */
431
432 static void
433 emit_mem2gmem_surf(struct fd_batch *batch, uint32_t base,
434 struct pipe_surface *psurf, enum a5xx_blit_buf buf)
435 {
436 struct fd_ringbuffer *ring = batch->gmem;
437 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
438 struct fd_resource *rsc = fd_resource(psurf->texture);
439 uint32_t stride, size;
440
441 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
442
443 stride = gmem->bin_w * rsc->cpp;
444 size = stride * gmem->bin_h;
445
446 OUT_PKT4(ring, REG_A5XX_RB_BLIT_FLAG_DST_LO, 4);
447 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_LO */
448 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_HI */
449 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_PITCH */
450 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_ARRAY_PITCH */
451
452 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_3, 5);
453 OUT_RING(ring, 0x00000000); /* RB_RESOLVE_CNTL_3 */
454 OUT_RING(ring, base); /* RB_BLIT_DST_LO */
455 OUT_RING(ring, 0x00000000); /* RB_BLIT_DST_HI */
456 OUT_RING(ring, A5XX_RB_BLIT_DST_PITCH(stride));
457 OUT_RING(ring, A5XX_RB_BLIT_DST_ARRAY_PITCH(size));
458
459 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
460 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(buf));
461
462 fd5_emit_blit(batch->ctx, ring);
463 }
464
465 static void
466 fd5_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
467 {
468 struct fd_ringbuffer *ring = batch->gmem;
469 struct fd_context *ctx = batch->ctx;
470 struct fd_gmem_stateobj *gmem = &ctx->gmem;
471 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
472
473 /*
474 * setup mrt and zs with system memory base addresses:
475 */
476
477 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL);
478 // emit_zs(ring, pfb->zsbuf, NULL);
479
480 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
481 OUT_RING(ring, A5XX_RB_CNTL_WIDTH(gmem->bin_w) |
482 A5XX_RB_CNTL_HEIGHT(gmem->bin_h) |
483 A5XX_RB_CNTL_BYPASS);
484
485 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
486 unsigned i;
487 for (i = 0; i < pfb->nr_cbufs; i++) {
488 if (!pfb->cbufs[i])
489 continue;
490 if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
491 continue;
492 emit_mem2gmem_surf(batch, gmem->cbuf_base[i],
493 pfb->cbufs[i], BLIT_MRT0 + i);
494 }
495 }
496
497 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
498 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
499 // XXX BLIT_ZS vs BLIT_Z32 .. need some more cmdstream traces
500 // with z32_x24s8..
501
502 // XXX hack import via BLIT_MRT0 instead of BLIT_ZS, since I don't
503 // know otherwise how to go from linear in sysmem to tiled in gmem.
504 // possibly we want to flip this around gmem2mem and keep depth
505 // tiled in sysmem (and fixup sampler state to assume tiled).. this
506 // might be required for doing depth/stencil in bypass mode?
507 struct fd_resource_slice *slice = fd_resource_slice(rsc, 0);
508 enum a5xx_color_fmt format =
509 fd5_pipe2color(fd_gmem_restore_format(pfb->zsbuf->format));
510
511 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(0), 5);
512 OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
513 A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(TILE5_LINEAR) |
514 A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX));
515 OUT_RING(ring, A5XX_RB_MRT_PITCH(slice->pitch * rsc->cpp));
516 OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(slice->size0));
517 OUT_RELOCW(ring, rsc->bo, 0, 0, 0); /* BASE_LO/HI */
518
519 emit_mem2gmem_surf(batch, ctx->gmem.zsbuf_base[0], pfb->zsbuf, BLIT_MRT0);
520 }
521 }
522
523
524 /* before IB to rendering cmds: */
525 static void
526 fd5_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
527 {
528 struct fd_ringbuffer *ring = batch->gmem;
529 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
530 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
531
532 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
533 OUT_RING(ring, A5XX_RB_CNTL_WIDTH(gmem->bin_w) |
534 A5XX_RB_CNTL_HEIGHT(gmem->bin_h));
535
536 emit_zs(ring, pfb->zsbuf, gmem);
537 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem);
538
539 // TODO MSAA
540 OUT_PKT4(ring, REG_A5XX_TPL1_TP_RAS_MSAA_CNTL, 2);
541 OUT_RING(ring, A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
542 OUT_RING(ring, A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
543 A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE);
544
545 OUT_PKT4(ring, REG_A5XX_RB_RAS_MSAA_CNTL, 2);
546 OUT_RING(ring, A5XX_RB_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
547 OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
548 A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE);
549
550 OUT_PKT4(ring, REG_A5XX_GRAS_SC_RAS_MSAA_CNTL, 2);
551 OUT_RING(ring, A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
552 OUT_RING(ring, A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
553 A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE);
554 }
555
556
557 /*
558 * transfer from gmem to system memory (ie. normal RAM)
559 */
560
561 static void
562 emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
563 struct pipe_surface *psurf, enum a5xx_blit_buf buf)
564 {
565 struct fd_ringbuffer *ring = batch->gmem;
566 struct fd_resource *rsc = fd_resource(psurf->texture);
567 struct fd_resource_slice *slice;
568 uint32_t offset;
569
570 slice = fd_resource_slice(rsc, psurf->u.tex.level);
571 offset = fd_resource_offset(rsc, psurf->u.tex.level,
572 psurf->u.tex.first_layer);
573
574 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
575
576 OUT_PKT4(ring, REG_A5XX_RB_BLIT_FLAG_DST_LO, 4);
577 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_LO */
578 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_HI */
579 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_PITCH */
580 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_ARRAY_PITCH */
581
582 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_3, 5);
583 OUT_RING(ring, 0x00000004); /* XXX RB_RESOLVE_CNTL_3 */
584 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_BLIT_DST_LO/HI */
585 OUT_RING(ring, A5XX_RB_BLIT_DST_PITCH(slice->pitch * rsc->cpp));
586 OUT_RING(ring, A5XX_RB_BLIT_DST_ARRAY_PITCH(slice->size0));
587
588 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
589 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(buf));
590
591 fd5_emit_blit(batch->ctx, ring);
592 }
593
594 static void
595 fd5_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
596 {
597 struct fd_context *ctx = batch->ctx;
598 struct fd_gmem_stateobj *gmem = &ctx->gmem;
599 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
600
601 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
602 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
603 // XXX BLIT_ZS vs BLIT_Z32 .. need some more cmdstream traces
604 // with z32_x24s8..
605 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH))
606 emit_gmem2mem_surf(batch, gmem->zsbuf_base[0], pfb->zsbuf, BLIT_ZS);
607 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL))
608 emit_gmem2mem_surf(batch, gmem->zsbuf_base[1], pfb->zsbuf, BLIT_ZS);
609 }
610
611 if (batch->resolve & FD_BUFFER_COLOR) {
612 unsigned i;
613 for (i = 0; i < pfb->nr_cbufs; i++) {
614 if (!pfb->cbufs[i])
615 continue;
616 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
617 continue;
618 emit_gmem2mem_surf(batch, gmem->cbuf_base[i],
619 pfb->cbufs[i], BLIT_MRT0 + i);
620 }
621 }
622 }
623
624 static void
625 fd5_emit_tile_fini(struct fd_batch *batch)
626 {
627 struct fd_ringbuffer *ring = batch->gmem;
628
629 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
630 OUT_RING(ring, 0x0);
631
632 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
633 OUT_RING(ring, LRZ_FLUSH);
634
635 fd5_cache_flush(batch, ring);
636 fd5_set_render_mode(batch->ctx, ring, BYPASS);
637 }
638
639 static void
640 fd5_emit_sysmem_prep(struct fd_batch *batch)
641 {
642 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
643 struct fd_ringbuffer *ring = batch->gmem;
644
645 fd5_emit_restore(batch, ring);
646
647 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
648 OUT_RING(ring, LRZ_FLUSH);
649
650 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
651 OUT_RING(ring, 0x0);
652
653 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
654 OUT_RING(ring, UNK_19);
655
656 OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
657 OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
658
659 OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
660 OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
661
662 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
663 fd_wfi(batch, ring);
664 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
665 OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */
666
667 OUT_PKT4(ring, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
668 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
669 A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
670 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
671 A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
672
673 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
674 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(0) |
675 A5XX_RB_RESOLVE_CNTL_1_Y(0));
676 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(pfb->width - 1) |
677 A5XX_RB_RESOLVE_CNTL_2_Y(pfb->height - 1));
678
679 OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1);
680 OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(0) |
681 A5XX_RB_WINDOW_OFFSET_Y(0));
682
683 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
684 OUT_RING(ring, 0x1);
685
686 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
687 OUT_RING(ring, A5XX_RB_CNTL_WIDTH(0) |
688 A5XX_RB_CNTL_HEIGHT(0) |
689 A5XX_RB_CNTL_BYPASS);
690
691 patch_draws(batch, IGNORE_VISIBILITY);
692
693 emit_zs(ring, pfb->zsbuf, NULL);
694 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL);
695
696 // TODO MSAA
697 OUT_PKT4(ring, REG_A5XX_TPL1_TP_RAS_MSAA_CNTL, 2);
698 OUT_RING(ring, A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
699 OUT_RING(ring, A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
700 A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE);
701
702 OUT_PKT4(ring, REG_A5XX_RB_RAS_MSAA_CNTL, 2);
703 OUT_RING(ring, A5XX_RB_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
704 OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
705 A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE);
706
707 OUT_PKT4(ring, REG_A5XX_GRAS_SC_RAS_MSAA_CNTL, 2);
708 OUT_RING(ring, A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
709 OUT_RING(ring, A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
710 A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE);
711 }
712
713 static void
714 fd5_emit_sysmem_fini(struct fd_batch *batch)
715 {
716 struct fd5_context *fd5_ctx = fd5_context(batch->ctx);
717 struct fd_ringbuffer *ring = batch->gmem;
718
719 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
720 OUT_RING(ring, 0x0);
721
722 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
723 OUT_RING(ring, LRZ_FLUSH);
724
725 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
726 OUT_RING(ring, UNK_1D);
727 OUT_RELOCW(ring, fd5_ctx->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
728 OUT_RING(ring, 0x00000000);
729 }
730
731 void
732 fd5_gmem_init(struct pipe_context *pctx)
733 {
734 struct fd_context *ctx = fd_context(pctx);
735
736 ctx->emit_tile_init = fd5_emit_tile_init;
737 ctx->emit_tile_prep = fd5_emit_tile_prep;
738 ctx->emit_tile_mem2gmem = fd5_emit_tile_mem2gmem;
739 ctx->emit_tile_renderprep = fd5_emit_tile_renderprep;
740 ctx->emit_tile_gmem2mem = fd5_emit_tile_gmem2mem;
741 ctx->emit_tile_fini = fd5_emit_tile_fini;
742 ctx->emit_sysmem_prep = fd5_emit_sysmem_prep;
743 ctx->emit_sysmem_fini = fd5_emit_sysmem_fini;
744 }