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a5xx: set uint/sint bits for mrt output register
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_gmem.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/u_format.h"
32
33 #include "freedreno_draw.h"
34 #include "freedreno_state.h"
35 #include "freedreno_resource.h"
36
37 #include "fd5_gmem.h"
38 #include "fd5_context.h"
39 #include "fd5_draw.h"
40 #include "fd5_emit.h"
41 #include "fd5_program.h"
42 #include "fd5_format.h"
43 #include "fd5_zsa.h"
44
45 static void
46 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
47 struct pipe_surface **bufs, struct fd_gmem_stateobj *gmem)
48 {
49 enum a5xx_tile_mode tile_mode;
50 unsigned i;
51
52 if (gmem) {
53 tile_mode = TILE5_2;
54 } else {
55 tile_mode = TILE5_LINEAR;
56 }
57
58 for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
59 enum a5xx_color_fmt format = 0;
60 enum a3xx_color_swap swap = WZYX;
61 bool srgb = false, sint = false, uint = false;
62 struct fd_resource *rsc = NULL;
63 struct fd_resource_slice *slice = NULL;
64 uint32_t stride = 0;
65 uint32_t size = 0;
66 uint32_t base = 0;
67 uint32_t offset = 0;
68
69 if ((i < nr_bufs) && bufs[i]) {
70 struct pipe_surface *psurf = bufs[i];
71 enum pipe_format pformat = psurf->format;
72
73 rsc = fd_resource(psurf->texture);
74
75 slice = fd_resource_slice(rsc, psurf->u.tex.level);
76 format = fd5_pipe2color(pformat);
77 swap = fd5_pipe2swap(pformat);
78 srgb = util_format_is_srgb(pformat);
79 sint = util_format_is_pure_sint(pformat);
80 uint = util_format_is_pure_uint(pformat);
81
82 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
83
84 offset = fd_resource_offset(rsc, psurf->u.tex.level,
85 psurf->u.tex.first_layer);
86
87 if (gmem) {
88 stride = gmem->bin_w * rsc->cpp;
89 size = stride * gmem->bin_h;
90 base = gmem->cbuf_base[i];
91 } else {
92 stride = slice->pitch * rsc->cpp;
93 size = slice->size0;
94 }
95 }
96
97 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(i), 5);
98 OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
99 A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
100 A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
101 COND(gmem, 0x800) | /* XXX 0x1000 for RECTLIST clear, 0x0 for BLIT.. */
102 COND(srgb, A5XX_RB_MRT_BUF_INFO_COLOR_SRGB));
103 OUT_RING(ring, A5XX_RB_MRT_PITCH(stride));
104 OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(size));
105 if (gmem || (i >= nr_bufs) || !bufs[i]) {
106 OUT_RING(ring, base); /* RB_MRT[i].BASE_LO */
107 OUT_RING(ring, 0x00000000); /* RB_MRT[i].BASE_HI */
108 } else {
109 debug_assert((offset + size) <= fd_bo_size(rsc->bo));
110 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* BASE_LO/HI */
111 }
112
113 OUT_PKT4(ring, REG_A5XX_SP_FS_MRT_REG(i), 1);
114 OUT_RING(ring, A5XX_SP_FS_MRT_REG_COLOR_FORMAT(format) |
115 COND(sint, A5XX_SP_FS_MRT_REG_COLOR_SINT) |
116 COND(uint, A5XX_SP_FS_MRT_REG_COLOR_UINT) |
117 COND(srgb, A5XX_SP_FS_MRT_REG_COLOR_SRGB));
118
119 /* when we support UBWC, these would be the system memory
120 * addr/pitch/etc:
121 */
122 OUT_PKT4(ring, REG_A5XX_RB_MRT_FLAG_BUFFER(i), 4);
123 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
124 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
125 OUT_RING(ring, A5XX_RB_MRT_FLAG_BUFFER_PITCH(0));
126 OUT_RING(ring, A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(0));
127 }
128 }
129
130 static void
131 emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
132 struct fd_gmem_stateobj *gmem)
133 {
134 if (zsbuf) {
135 struct fd_resource *rsc = fd_resource(zsbuf->texture);
136 enum a5xx_depth_format fmt = fd5_pipe2depth(zsbuf->format);
137 uint32_t cpp = rsc->cpp;
138 uint32_t stride = 0;
139 uint32_t size = 0;
140
141 if (gmem) {
142 stride = cpp * gmem->bin_w;
143 size = stride * gmem->bin_h;
144 } else {
145 struct fd_resource_slice *slice = fd_resource_slice(rsc, 0);
146 stride = slice->pitch * rsc->cpp;
147 size = slice->size0;
148 }
149
150 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_BUFFER_INFO, 5);
151 OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
152 if (gmem) {
153 OUT_RING(ring, gmem->zsbuf_base[0]); /* RB_DEPTH_BUFFER_BASE_LO */
154 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
155 } else {
156 OUT_RELOCW(ring, rsc->bo, 0, 0, 0); /* RB_DEPTH_BUFFER_BASE_LO/HI */
157 }
158 OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_PITCH(stride));
159 OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(size));
160
161 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
162 OUT_RING(ring, A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
163
164 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
165 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
166 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
167 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */
168
169 if (rsc->lrz) {
170 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO, 3);
171 OUT_RELOCW(ring, rsc->lrz, 0x1000, 0, 0);
172 OUT_RING(ring, A5XX_GRAS_LRZ_BUFFER_PITCH(rsc->lrz_pitch));
173
174 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO, 2);
175 OUT_RELOCW(ring, rsc->lrz, 0, 0, 0);
176 } else {
177 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO, 3);
178 OUT_RING(ring, 0x00000000);
179 OUT_RING(ring, 0x00000000);
180 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
181
182 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO, 2);
183 OUT_RING(ring, 0x00000000);
184 OUT_RING(ring, 0x00000000);
185 }
186
187 if (rsc->stencil) {
188 if (gmem) {
189 stride = 1 * gmem->bin_w;
190 size = stride * gmem->bin_h;
191 } else {
192 struct fd_resource_slice *slice = fd_resource_slice(rsc->stencil, 0);
193 stride = slice->pitch * rsc->cpp;
194 size = slice->size0;
195 }
196
197 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 5);
198 OUT_RING(ring, A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL);
199 if (gmem) {
200 OUT_RING(ring, gmem->zsbuf_base[1]); /* RB_STENCIL_BASE_LO */
201 OUT_RING(ring, 0x00000000); /* RB_STENCIL_BASE_HI */
202 } else {
203 OUT_RELOCW(ring, rsc->stencil->bo, 0, 0, 0); /* RB_STENCIL_BASE_LO/HI */
204 }
205 OUT_RING(ring, A5XX_RB_STENCIL_PITCH(stride));
206 OUT_RING(ring, A5XX_RB_STENCIL_ARRAY_PITCH(size));
207 } else {
208 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 1);
209 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
210 }
211 } else {
212 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_BUFFER_INFO, 5);
213 OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH5_NONE));
214 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
215 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
216 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
217 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
218
219 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
220 OUT_RING(ring, A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH5_NONE));
221
222 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
223 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
224 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
225 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */
226
227 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 1);
228 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
229 }
230 }
231
232 static bool
233 use_hw_binning(struct fd_batch *batch)
234 {
235 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
236
237 if ((gmem->maxpw * gmem->maxph) > 32)
238 return false;
239
240 if ((gmem->maxpw > 15) || (gmem->maxph > 15))
241 return false;
242
243 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2) &&
244 (batch->num_draws > 0);
245 }
246
247 static void
248 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
249 {
250 unsigned i;
251 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
252 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
253 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
254 }
255 util_dynarray_resize(&batch->draw_patches, 0);
256 }
257
258 static void
259 update_vsc_pipe(struct fd_batch *batch)
260 {
261 struct fd_context *ctx = batch->ctx;
262 struct fd5_context *fd5_ctx = fd5_context(ctx);
263 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
264 struct fd_ringbuffer *ring = batch->gmem;
265 int i;
266
267 OUT_PKT4(ring, REG_A5XX_VSC_BIN_SIZE, 3);
268 OUT_RING(ring, A5XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
269 A5XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
270 OUT_RELOCW(ring, fd5_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS_LO/HI */
271
272 OUT_PKT4(ring, REG_A5XX_UNKNOWN_0BC5, 2);
273 OUT_RING(ring, 0x00000000); /* UNKNOWN_0BC5 */
274 OUT_RING(ring, 0x00000000); /* UNKNOWN_0BC6 */
275
276 OUT_PKT4(ring, REG_A5XX_VSC_PIPE_CONFIG_REG(0), 16);
277 for (i = 0; i < 16; i++) {
278 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
279 OUT_RING(ring, A5XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
280 A5XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
281 A5XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
282 A5XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
283 }
284
285 OUT_PKT4(ring, REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(0), 32);
286 for (i = 0; i < 16; i++) {
287 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
288 if (!pipe->bo) {
289 pipe->bo = fd_bo_new(ctx->dev, 0x20000,
290 DRM_FREEDRENO_GEM_TYPE_KMEM);
291 }
292 OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i].LO/HI */
293 }
294
295 OUT_PKT4(ring, REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(0), 16);
296 for (i = 0; i < 16; i++) {
297 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
298 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
299 }
300 }
301
302 static void
303 emit_binning_pass(struct fd_batch *batch)
304 {
305 struct fd_context *ctx = batch->ctx;
306 struct fd_ringbuffer *ring = batch->gmem;
307 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
308
309 uint32_t x1 = gmem->minx;
310 uint32_t y1 = gmem->miny;
311 uint32_t x2 = gmem->minx + gmem->width - 1;
312 uint32_t y2 = gmem->miny + gmem->height - 1;
313
314 fd5_set_render_mode(batch->ctx, ring, BINNING);
315
316 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
317 OUT_RING(ring, A5XX_RB_CNTL_WIDTH(gmem->bin_w) |
318 A5XX_RB_CNTL_HEIGHT(gmem->bin_h));
319
320 OUT_PKT4(ring, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
321 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
322 A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
323 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
324 A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
325
326 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
327 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(x1) |
328 A5XX_RB_RESOLVE_CNTL_1_Y(y1));
329 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(x2) |
330 A5XX_RB_RESOLVE_CNTL_2_Y(y2));
331
332 update_vsc_pipe(batch);
333
334 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
335 OUT_RING(ring, A5XX_VPC_MODE_CNTL_BINNING_PASS);
336
337 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
338 OUT_RING(ring, UNK_2C);
339
340 OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1);
341 OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(0) |
342 A5XX_RB_WINDOW_OFFSET_Y(0));
343
344 /* emit IB to binning drawcmds: */
345 ctx->emit_ib(ring, batch->binning);
346
347 fd_reset_wfi(batch);
348
349 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
350 OUT_RING(ring, UNK_2D);
351
352 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
353 OUT_RING(ring, CACHE_FLUSH_TS);
354 OUT_RELOCW(ring, fd5_context(ctx)->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
355 OUT_RING(ring, 0x00000000);
356
357 // TODO CP_COND_WRITE's for all the vsc buffers (check for overflow??)
358
359 fd_wfi(batch, ring);
360
361 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
362 OUT_RING(ring, 0x0);
363 }
364
365 /* before first tile */
366 static void
367 fd5_emit_tile_init(struct fd_batch *batch)
368 {
369 struct fd_context *ctx = batch->ctx;
370 struct fd_ringbuffer *ring = batch->gmem;
371 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
372
373 fd5_emit_restore(batch, ring);
374
375 if (batch->lrz_clear)
376 ctx->emit_ib(ring, batch->lrz_clear);
377
378 fd5_emit_lrz_flush(ring);
379
380 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
381 OUT_RING(ring, 0x00000080); /* GRAS_CL_CNTL */
382
383 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
384 OUT_RING(ring, 0x0);
385
386 OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
387 OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
388
389 OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
390 OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
391
392 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
393 fd_wfi(batch, ring);
394 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
395 OUT_RING(ring, 0x7c13c080); /* RB_CCU_CNTL */
396
397 emit_zs(ring, pfb->zsbuf, &ctx->gmem);
398 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, &ctx->gmem);
399
400 if (use_hw_binning(batch)) {
401 emit_binning_pass(batch);
402 fd5_emit_lrz_flush(ring);
403 patch_draws(batch, USE_VISIBILITY);
404 } else {
405 patch_draws(batch, IGNORE_VISIBILITY);
406 }
407
408 fd5_set_render_mode(batch->ctx, ring, GMEM);
409 }
410
411 /* before mem2gmem */
412 static void
413 fd5_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
414 {
415 struct fd_context *ctx = batch->ctx;
416 struct fd5_context *fd5_ctx = fd5_context(ctx);
417 struct fd_ringbuffer *ring = batch->gmem;
418
419 uint32_t x1 = tile->xoff;
420 uint32_t y1 = tile->yoff;
421 uint32_t x2 = tile->xoff + tile->bin_w - 1;
422 uint32_t y2 = tile->yoff + tile->bin_h - 1;
423
424 OUT_PKT4(ring, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
425 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
426 A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
427 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
428 A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
429
430 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
431 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(x1) |
432 A5XX_RB_RESOLVE_CNTL_1_Y(y1));
433 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(x2) |
434 A5XX_RB_RESOLVE_CNTL_2_Y(y2));
435
436 if (use_hw_binning(batch)) {
437 struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
438
439 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
440
441 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
442 OUT_RING(ring, 0x0);
443
444 OUT_PKT7(ring, CP_SET_BIN_DATA5, 5);
445 OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
446 CP_SET_BIN_DATA5_0_VSC_N(tile->n));
447 OUT_RELOC(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE[p].DATA_ADDRESS */
448 OUT_RELOC(ring, fd5_ctx->vsc_size_mem, /* VSC_SIZE_ADDRESS + (p * 4) */
449 (tile->p * 4), 0, 0);
450 } else {
451 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
452 OUT_RING(ring, 0x1);
453 }
454
455 OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1);
456 OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(x1) |
457 A5XX_RB_WINDOW_OFFSET_Y(y1));
458 }
459
460
461 /*
462 * transfer from system memory to gmem
463 */
464
465 static void
466 emit_mem2gmem_surf(struct fd_batch *batch, uint32_t base,
467 struct pipe_surface *psurf, enum a5xx_blit_buf buf)
468 {
469 struct fd_ringbuffer *ring = batch->gmem;
470 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
471 struct fd_resource *rsc = fd_resource(psurf->texture);
472 uint32_t stride, size;
473
474 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
475
476 stride = gmem->bin_w * rsc->cpp;
477 size = stride * gmem->bin_h;
478
479 OUT_PKT4(ring, REG_A5XX_RB_BLIT_FLAG_DST_LO, 4);
480 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_LO */
481 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_HI */
482 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_PITCH */
483 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_ARRAY_PITCH */
484
485 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_3, 5);
486 OUT_RING(ring, 0x00000000); /* RB_RESOLVE_CNTL_3 */
487 OUT_RING(ring, base); /* RB_BLIT_DST_LO */
488 OUT_RING(ring, 0x00000000); /* RB_BLIT_DST_HI */
489 OUT_RING(ring, A5XX_RB_BLIT_DST_PITCH(stride));
490 OUT_RING(ring, A5XX_RB_BLIT_DST_ARRAY_PITCH(size));
491
492 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
493 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(buf));
494
495 fd5_emit_blit(batch->ctx, ring);
496 }
497
498 static void
499 fd5_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
500 {
501 struct fd_ringbuffer *ring = batch->gmem;
502 struct fd_context *ctx = batch->ctx;
503 struct fd_gmem_stateobj *gmem = &ctx->gmem;
504 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
505
506 /*
507 * setup mrt and zs with system memory base addresses:
508 */
509
510 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL);
511 // emit_zs(ring, pfb->zsbuf, NULL);
512
513 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
514 OUT_RING(ring, A5XX_RB_CNTL_WIDTH(gmem->bin_w) |
515 A5XX_RB_CNTL_HEIGHT(gmem->bin_h) |
516 A5XX_RB_CNTL_BYPASS);
517
518 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
519 unsigned i;
520 for (i = 0; i < pfb->nr_cbufs; i++) {
521 if (!pfb->cbufs[i])
522 continue;
523 if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
524 continue;
525 emit_mem2gmem_surf(batch, gmem->cbuf_base[i],
526 pfb->cbufs[i], BLIT_MRT0 + i);
527 }
528 }
529
530 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
531 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
532 // XXX BLIT_ZS vs BLIT_Z32 .. need some more cmdstream traces
533 // with z32_x24s8..
534
535 // XXX hack import via BLIT_MRT0 instead of BLIT_ZS, since I don't
536 // know otherwise how to go from linear in sysmem to tiled in gmem.
537 // possibly we want to flip this around gmem2mem and keep depth
538 // tiled in sysmem (and fixup sampler state to assume tiled).. this
539 // might be required for doing depth/stencil in bypass mode?
540 struct fd_resource_slice *slice = fd_resource_slice(rsc, 0);
541 enum a5xx_color_fmt format =
542 fd5_pipe2color(fd_gmem_restore_format(pfb->zsbuf->format));
543
544 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(0), 5);
545 OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
546 A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(TILE5_LINEAR) |
547 A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX));
548 OUT_RING(ring, A5XX_RB_MRT_PITCH(slice->pitch * rsc->cpp));
549 OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(slice->size0));
550 OUT_RELOCW(ring, rsc->bo, 0, 0, 0); /* BASE_LO/HI */
551
552 emit_mem2gmem_surf(batch, ctx->gmem.zsbuf_base[0], pfb->zsbuf, BLIT_MRT0);
553 }
554 }
555
556
557 /* before IB to rendering cmds: */
558 static void
559 fd5_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
560 {
561 struct fd_ringbuffer *ring = batch->gmem;
562 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
563 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
564
565 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
566 OUT_RING(ring, A5XX_RB_CNTL_WIDTH(gmem->bin_w) |
567 A5XX_RB_CNTL_HEIGHT(gmem->bin_h));
568
569 emit_zs(ring, pfb->zsbuf, gmem);
570 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem);
571
572 // TODO MSAA
573 OUT_PKT4(ring, REG_A5XX_TPL1_TP_RAS_MSAA_CNTL, 2);
574 OUT_RING(ring, A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
575 OUT_RING(ring, A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
576 A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE);
577
578 OUT_PKT4(ring, REG_A5XX_RB_RAS_MSAA_CNTL, 2);
579 OUT_RING(ring, A5XX_RB_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
580 OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
581 A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE);
582
583 OUT_PKT4(ring, REG_A5XX_GRAS_SC_RAS_MSAA_CNTL, 2);
584 OUT_RING(ring, A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
585 OUT_RING(ring, A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
586 A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE);
587 }
588
589
590 /*
591 * transfer from gmem to system memory (ie. normal RAM)
592 */
593
594 static void
595 emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
596 struct pipe_surface *psurf, enum a5xx_blit_buf buf)
597 {
598 struct fd_ringbuffer *ring = batch->gmem;
599 struct fd_resource *rsc = fd_resource(psurf->texture);
600 struct fd_resource_slice *slice;
601 uint32_t offset;
602
603 slice = fd_resource_slice(rsc, psurf->u.tex.level);
604 offset = fd_resource_offset(rsc, psurf->u.tex.level,
605 psurf->u.tex.first_layer);
606
607 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
608
609 OUT_PKT4(ring, REG_A5XX_RB_BLIT_FLAG_DST_LO, 4);
610 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_LO */
611 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_HI */
612 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_PITCH */
613 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_ARRAY_PITCH */
614
615 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_3, 5);
616 OUT_RING(ring, 0x00000004); /* XXX RB_RESOLVE_CNTL_3 */
617 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_BLIT_DST_LO/HI */
618 OUT_RING(ring, A5XX_RB_BLIT_DST_PITCH(slice->pitch * rsc->cpp));
619 OUT_RING(ring, A5XX_RB_BLIT_DST_ARRAY_PITCH(slice->size0));
620
621 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
622 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(buf));
623
624 fd5_emit_blit(batch->ctx, ring);
625 }
626
627 static void
628 fd5_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
629 {
630 struct fd_context *ctx = batch->ctx;
631 struct fd_gmem_stateobj *gmem = &ctx->gmem;
632 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
633
634 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
635 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
636 // XXX BLIT_ZS vs BLIT_Z32 .. need some more cmdstream traces
637 // with z32_x24s8..
638 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH))
639 emit_gmem2mem_surf(batch, gmem->zsbuf_base[0], pfb->zsbuf, BLIT_ZS);
640 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL))
641 emit_gmem2mem_surf(batch, gmem->zsbuf_base[1], pfb->zsbuf, BLIT_ZS);
642 }
643
644 if (batch->resolve & FD_BUFFER_COLOR) {
645 unsigned i;
646 for (i = 0; i < pfb->nr_cbufs; i++) {
647 if (!pfb->cbufs[i])
648 continue;
649 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
650 continue;
651 emit_gmem2mem_surf(batch, gmem->cbuf_base[i],
652 pfb->cbufs[i], BLIT_MRT0 + i);
653 }
654 }
655 }
656
657 static void
658 fd5_emit_tile_fini(struct fd_batch *batch)
659 {
660 struct fd_ringbuffer *ring = batch->gmem;
661
662 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
663 OUT_RING(ring, 0x0);
664
665 fd5_emit_lrz_flush(ring);
666
667 fd5_cache_flush(batch, ring);
668 fd5_set_render_mode(batch->ctx, ring, BYPASS);
669 }
670
671 static void
672 fd5_emit_sysmem_prep(struct fd_batch *batch)
673 {
674 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
675 struct fd_ringbuffer *ring = batch->gmem;
676
677 fd5_emit_restore(batch, ring);
678
679 fd5_emit_lrz_flush(ring);
680
681 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
682 OUT_RING(ring, 0x0);
683
684 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
685 OUT_RING(ring, UNK_19);
686
687 OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
688 OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
689
690 OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
691 OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
692
693 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
694 fd_wfi(batch, ring);
695 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
696 OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */
697
698 OUT_PKT4(ring, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
699 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
700 A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
701 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
702 A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
703
704 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
705 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(0) |
706 A5XX_RB_RESOLVE_CNTL_1_Y(0));
707 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(pfb->width - 1) |
708 A5XX_RB_RESOLVE_CNTL_2_Y(pfb->height - 1));
709
710 OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1);
711 OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(0) |
712 A5XX_RB_WINDOW_OFFSET_Y(0));
713
714 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
715 OUT_RING(ring, 0x1);
716
717 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
718 OUT_RING(ring, A5XX_RB_CNTL_WIDTH(0) |
719 A5XX_RB_CNTL_HEIGHT(0) |
720 A5XX_RB_CNTL_BYPASS);
721
722 patch_draws(batch, IGNORE_VISIBILITY);
723
724 emit_zs(ring, pfb->zsbuf, NULL);
725 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL);
726
727 // TODO MSAA
728 OUT_PKT4(ring, REG_A5XX_TPL1_TP_RAS_MSAA_CNTL, 2);
729 OUT_RING(ring, A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
730 OUT_RING(ring, A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
731 A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE);
732
733 OUT_PKT4(ring, REG_A5XX_RB_RAS_MSAA_CNTL, 2);
734 OUT_RING(ring, A5XX_RB_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
735 OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
736 A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE);
737
738 OUT_PKT4(ring, REG_A5XX_GRAS_SC_RAS_MSAA_CNTL, 2);
739 OUT_RING(ring, A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
740 OUT_RING(ring, A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
741 A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE);
742 }
743
744 static void
745 fd5_emit_sysmem_fini(struct fd_batch *batch)
746 {
747 struct fd5_context *fd5_ctx = fd5_context(batch->ctx);
748 struct fd_ringbuffer *ring = batch->gmem;
749
750 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
751 OUT_RING(ring, 0x0);
752
753 fd5_emit_lrz_flush(ring);
754
755 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
756 OUT_RING(ring, UNK_1D);
757 OUT_RELOCW(ring, fd5_ctx->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
758 OUT_RING(ring, 0x00000000);
759 }
760
761 void
762 fd5_gmem_init(struct pipe_context *pctx)
763 {
764 struct fd_context *ctx = fd_context(pctx);
765
766 ctx->emit_tile_init = fd5_emit_tile_init;
767 ctx->emit_tile_prep = fd5_emit_tile_prep;
768 ctx->emit_tile_mem2gmem = fd5_emit_tile_mem2gmem;
769 ctx->emit_tile_renderprep = fd5_emit_tile_renderprep;
770 ctx->emit_tile_gmem2mem = fd5_emit_tile_gmem2mem;
771 ctx->emit_tile_fini = fd5_emit_tile_fini;
772 ctx->emit_sysmem_prep = fd5_emit_sysmem_prep;
773 ctx->emit_sysmem_fini = fd5_emit_sysmem_fini;
774 }