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d37c9d41f665435e76a42f1af5a3073465affdaf
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_gmem.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/u_format.h"
32
33 #include "freedreno_draw.h"
34 #include "freedreno_state.h"
35 #include "freedreno_resource.h"
36
37 #include "fd5_gmem.h"
38 #include "fd5_context.h"
39 #include "fd5_draw.h"
40 #include "fd5_emit.h"
41 #include "fd5_program.h"
42 #include "fd5_format.h"
43 #include "fd5_zsa.h"
44
45 static void
46 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
47 struct pipe_surface **bufs, struct fd_gmem_stateobj *gmem)
48 {
49 enum a5xx_tile_mode tile_mode;
50 unsigned i;
51
52 if (gmem) {
53 tile_mode = TILE5_2;
54 } else {
55 tile_mode = TILE5_LINEAR;
56 }
57
58 for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
59 enum a5xx_color_fmt format = 0;
60 enum a3xx_color_swap swap = WZYX;
61 bool srgb = false;
62 struct fd_resource *rsc = NULL;
63 struct fd_resource_slice *slice = NULL;
64 uint32_t stride = 0;
65 uint32_t size = 0;
66 uint32_t base = 0;
67 uint32_t offset = 0;
68
69 if ((i < nr_bufs) && bufs[i]) {
70 struct pipe_surface *psurf = bufs[i];
71 enum pipe_format pformat = psurf->format;
72
73 rsc = fd_resource(psurf->texture);
74
75 slice = fd_resource_slice(rsc, psurf->u.tex.level);
76 format = fd5_pipe2color(pformat);
77 swap = fd5_pipe2swap(pformat);
78 srgb = util_format_is_srgb(pformat);
79
80 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
81
82 offset = fd_resource_offset(rsc, psurf->u.tex.level,
83 psurf->u.tex.first_layer);
84
85 if (gmem) {
86 stride = gmem->bin_w * rsc->cpp;
87 size = stride * gmem->bin_h;
88 base = gmem->cbuf_base[i];
89 } else {
90 stride = slice->pitch * rsc->cpp;
91 size = slice->size0;
92 }
93 }
94
95 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(i), 5);
96 OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
97 A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
98 A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
99 0x800 | /* XXX 0x1000 for RECTLIST clear, 0x0 for BLIT.. */
100 COND(srgb, A5XX_RB_MRT_BUF_INFO_COLOR_SRGB));
101 OUT_RING(ring, A5XX_RB_MRT_PITCH(stride));
102 OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(size));
103 if (gmem || (i >= nr_bufs) || !bufs[i]) {
104 OUT_RING(ring, base); /* RB_MRT[i].BASE_LO */
105 OUT_RING(ring, 0x00000000); /* RB_MRT[i].BASE_HI */
106 } else {
107 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* BASE_LO/HI */
108 }
109
110 OUT_PKT4(ring, REG_A5XX_SP_FS_MRT_REG(i), 1);
111 OUT_RING(ring, A5XX_SP_FS_MRT_REG_COLOR_FORMAT(format));
112
113 /* when we support UBWC, these would be the system memory
114 * addr/pitch/etc:
115 */
116 OUT_PKT4(ring, REG_A5XX_RB_MRT_FLAG_BUFFER(i), 4);
117 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
118 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
119 OUT_RING(ring, A5XX_RB_MRT_FLAG_BUFFER_PITCH(0));
120 OUT_RING(ring, A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(0));
121 }
122 }
123
124 static void
125 emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
126 struct fd_gmem_stateobj *gmem)
127 {
128 if (zsbuf) {
129 struct fd_resource *rsc = fd_resource(zsbuf->texture);
130 enum a5xx_depth_format fmt = fd5_pipe2depth(zsbuf->format);
131 uint32_t cpp = rsc->cpp;
132 uint32_t stride = 0;
133 uint32_t size = 0;
134
135 if (gmem) {
136 stride = cpp * gmem->bin_w;
137 size = stride * gmem->bin_h;
138 } else {
139 struct fd_resource_slice *slice = fd_resource_slice(rsc, 0);
140 stride = slice->pitch * rsc->cpp;
141 size = slice->size0;
142 }
143
144 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_BUFFER_INFO, 5);
145 OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
146 if (gmem) {
147 OUT_RING(ring, gmem->zsbuf_base[0]); /* RB_DEPTH_BUFFER_BASE_LO */
148 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
149 } else {
150 OUT_RELOCW(ring, rsc->bo, 0, 0, 0); /* RB_DEPTH_BUFFER_BASE_LO/HI */
151 }
152 OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_PITCH(stride));
153 OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(size));
154
155 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
156 OUT_RING(ring, A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
157
158 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
159 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
160 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
161 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */
162
163 if (rsc->stencil) {
164 if (gmem) {
165 stride = 1 * gmem->bin_w;
166 size = stride * gmem->bin_h;
167 } else {
168 struct fd_resource_slice *slice = fd_resource_slice(rsc->stencil, 0);
169 stride = slice->pitch * rsc->cpp;
170 size = slice->size0;
171 }
172
173 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 5);
174 OUT_RING(ring, A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL);
175 if (gmem) {
176 OUT_RING(ring, gmem->zsbuf_base[1]); /* RB_STENCIL_BASE_LO */
177 OUT_RING(ring, 0x00000000); /* RB_STENCIL_BASE_HI */
178 } else {
179 OUT_RELOCW(ring, rsc->stencil->bo, 0, 0, 0); /* RB_STENCIL_BASE_LO/HI */
180 }
181 OUT_RING(ring, A5XX_RB_STENCIL_PITCH(stride));
182 OUT_RING(ring, A5XX_RB_STENCIL_ARRAY_PITCH(size));
183 } else {
184 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 1);
185 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
186 }
187 } else {
188 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_BUFFER_INFO, 5);
189 OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH5_NONE));
190 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
191 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
192 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
193 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
194
195 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
196 OUT_RING(ring, A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH5_NONE));
197
198 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
199 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
200 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
201 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */
202
203 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 1);
204 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
205 }
206 }
207
208 static void
209 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
210 {
211 unsigned i;
212 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
213 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
214 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
215 }
216 util_dynarray_resize(&batch->draw_patches, 0);
217 }
218
219 /* before first tile */
220 static void
221 fd5_emit_tile_init(struct fd_batch *batch)
222 {
223 struct fd_ringbuffer *ring = batch->gmem;
224
225 fd5_emit_restore(batch, ring);
226
227 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
228 OUT_RING(ring, UNK_26);
229
230 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
231 OUT_RING(ring, 0x0);
232
233 OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
234 OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
235
236 OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
237 OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
238
239 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
240 fd_wfi(batch, ring);
241 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
242 OUT_RING(ring, 0x7c13c080); /* RB_CCU_CNTL */
243
244 /*
245 opcode: CP_PREEMPT_ENABLE_LOCAL (6a) (2 dwords)
246 */
247
248 fd5_set_render_mode(batch->ctx, ring, GMEM);
249 }
250
251 /* before mem2gmem */
252 static void
253 fd5_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
254 {
255 struct fd_ringbuffer *ring = batch->gmem;
256
257 uint32_t x1 = tile->xoff;
258 uint32_t y1 = tile->yoff;
259 uint32_t x2 = tile->xoff + tile->bin_w - 1;
260 uint32_t y2 = tile->yoff + tile->bin_h - 1;
261
262 OUT_PKT4(ring, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
263 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
264 A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
265 OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
266 A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
267
268 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
269 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(x1) |
270 A5XX_RB_RESOLVE_CNTL_1_Y(y1));
271 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(x2) |
272 A5XX_RB_RESOLVE_CNTL_2_Y(y2));
273
274 OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1);
275 OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(x1) |
276 A5XX_RB_WINDOW_OFFSET_Y(y1));
277 }
278
279
280 /*
281 * transfer from system memory to gmem
282 */
283
284 static void
285 emit_mem2gmem_surf(struct fd_batch *batch, uint32_t base,
286 struct pipe_surface *psurf, enum a5xx_blit_buf buf)
287 {
288 struct fd_ringbuffer *ring = batch->gmem;
289 struct fd_resource *rsc = fd_resource(psurf->texture);
290 struct fd_resource_slice *slice;
291
292 slice = fd_resource_slice(rsc, psurf->u.tex.level);
293
294 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
295
296 OUT_PKT4(ring, REG_A5XX_RB_BLIT_FLAG_DST_LO, 4);
297 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_LO */
298 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_HI */
299 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_PITCH */
300 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_ARRAY_PITCH */
301
302 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_3, 5);
303 OUT_RING(ring, 0x00000000); /* RB_RESOLVE_CNTL_3 */
304 OUT_RING(ring, base); /* RB_BLIT_DST_LO */
305 OUT_RING(ring, 0x00000000); /* RB_BLIT_DST_HI */
306 OUT_RING(ring, A5XX_RB_BLIT_DST_PITCH(slice->pitch * rsc->cpp));
307 OUT_RING(ring, A5XX_RB_BLIT_DST_ARRAY_PITCH(slice->size0));
308
309 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
310 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(buf));
311
312 fd5_emit_blit(batch->ctx, ring);
313 }
314
315 static void
316 fd5_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
317 {
318 struct fd_ringbuffer *ring = batch->gmem;
319 struct fd_context *ctx = batch->ctx;
320 struct fd_gmem_stateobj *gmem = &ctx->gmem;
321 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
322
323 /*
324 * setup mrt and zs with system memory base addresses:
325 */
326
327 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL);
328 emit_zs(ring, pfb->zsbuf, NULL);
329
330 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
331 OUT_RING(ring, A5XX_RB_CNTL_WIDTH(gmem->bin_w) |
332 A5XX_RB_CNTL_HEIGHT(gmem->bin_h) |
333 A5XX_RB_CNTL_BYPASS);
334
335 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
336 unsigned i;
337 for (i = 0; i < pfb->nr_cbufs; i++) {
338 if (!pfb->cbufs[i])
339 continue;
340 if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
341 continue;
342 emit_mem2gmem_surf(batch, gmem->cbuf_base[i],
343 pfb->cbufs[i], BLIT_MRT0 + i);
344 }
345 }
346
347 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
348 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
349 // XXX BLIT_ZS vs BLIT_Z32 .. need some more cmdstream traces
350 // with z32_x24s8..
351 if (!rsc->stencil || (batch->restore & FD_BUFFER_DEPTH))
352 emit_mem2gmem_surf(batch, ctx->gmem.zsbuf_base[0], pfb->zsbuf, BLIT_ZS);
353 if (rsc->stencil && (batch->restore & FD_BUFFER_STENCIL))
354 emit_mem2gmem_surf(batch, ctx->gmem.zsbuf_base[1], pfb->zsbuf, BLIT_ZS);
355 }
356 }
357
358
359 /* before IB to rendering cmds: */
360 static void
361 fd5_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
362 {
363 struct fd_ringbuffer *ring = batch->gmem;
364 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
365 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
366
367 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
368 OUT_RING(ring, 0x1);
369
370 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
371 OUT_RING(ring, A5XX_RB_CNTL_WIDTH(gmem->bin_w) |
372 A5XX_RB_CNTL_HEIGHT(gmem->bin_h));
373
374 patch_draws(batch, IGNORE_VISIBILITY);
375
376 emit_zs(ring, pfb->zsbuf, gmem);
377 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem);
378
379 // TODO MSAA
380 OUT_PKT4(ring, REG_A5XX_TPL1_TP_RAS_MSAA_CNTL, 2);
381 OUT_RING(ring, A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
382 OUT_RING(ring, A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
383 A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE);
384
385 OUT_PKT4(ring, REG_A5XX_RB_RAS_MSAA_CNTL, 2);
386 OUT_RING(ring, A5XX_RB_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
387 OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
388 A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE);
389
390 OUT_PKT4(ring, REG_A5XX_GRAS_SC_RAS_MSAA_CNTL, 2);
391 OUT_RING(ring, A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
392 OUT_RING(ring, A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
393 A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE);
394 }
395
396
397 /*
398 * transfer from gmem to system memory (ie. normal RAM)
399 */
400
401 static void
402 emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
403 struct pipe_surface *psurf, enum a5xx_blit_buf buf)
404 {
405 struct fd_ringbuffer *ring = batch->gmem;
406 struct fd_resource *rsc = fd_resource(psurf->texture);
407 struct fd_resource_slice *slice;
408 uint32_t offset;
409
410 slice = fd_resource_slice(rsc, psurf->u.tex.level);
411 offset = fd_resource_offset(rsc, psurf->u.tex.level,
412 psurf->u.tex.first_layer);
413
414 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
415
416 OUT_PKT4(ring, REG_A5XX_RB_BLIT_FLAG_DST_LO, 4);
417 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_LO */
418 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_HI */
419 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_PITCH */
420 OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_ARRAY_PITCH */
421
422 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_3, 5);
423 OUT_RING(ring, 0x00000004); /* XXX RB_RESOLVE_CNTL_3 */
424 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_BLIT_DST_LO/HI */
425 OUT_RING(ring, A5XX_RB_BLIT_DST_PITCH(slice->pitch * rsc->cpp));
426 OUT_RING(ring, A5XX_RB_BLIT_DST_ARRAY_PITCH(slice->size0));
427
428 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
429 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(buf));
430
431 fd5_emit_blit(batch->ctx, ring);
432 }
433
434 static void
435 fd5_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
436 {
437 struct fd_context *ctx = batch->ctx;
438 struct fd_gmem_stateobj *gmem = &ctx->gmem;
439 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
440
441 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
442 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
443 // XXX BLIT_ZS vs BLIT_Z32 .. need some more cmdstream traces
444 // with z32_x24s8..
445 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH))
446 emit_gmem2mem_surf(batch, gmem->zsbuf_base[0], pfb->zsbuf, BLIT_ZS);
447 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL))
448 emit_gmem2mem_surf(batch, gmem->zsbuf_base[1], pfb->zsbuf, BLIT_ZS);
449 }
450
451 if (batch->resolve & FD_BUFFER_COLOR) {
452 unsigned i;
453 for (i = 0; i < pfb->nr_cbufs; i++) {
454 if (!pfb->cbufs[i])
455 continue;
456 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
457 continue;
458 emit_gmem2mem_surf(batch, gmem->cbuf_base[i],
459 pfb->cbufs[i], BLIT_MRT0 + i);
460 }
461 }
462 }
463
464 static void
465 fd5_emit_tile_fini(struct fd_batch *batch)
466 {
467 fd5_cache_flush(batch, batch->gmem);
468 fd5_set_render_mode(batch->ctx, batch->gmem, BYPASS);
469 }
470
471 void
472 fd5_gmem_init(struct pipe_context *pctx)
473 {
474 struct fd_context *ctx = fd_context(pctx);
475
476 ctx->emit_tile_init = fd5_emit_tile_init;
477 ctx->emit_tile_prep = fd5_emit_tile_prep;
478 ctx->emit_tile_mem2gmem = fd5_emit_tile_mem2gmem;
479 ctx->emit_tile_renderprep = fd5_emit_tile_renderprep;
480 ctx->emit_tile_gmem2mem = fd5_emit_tile_gmem2mem;
481 ctx->emit_tile_fini = fd5_emit_tile_fini;
482 }