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cf5571d54ea55059a648ac4799066dc539787bf3
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_perfcntr.c
1 /*
2 * Copyright (C) 2018 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #ifndef FD5_PERFCNTR_H_
28 #define FD5_PERFCNTR_H_
29
30 #include "freedreno_perfcntr.h"
31 #include "fd5_format.h"
32
33 #define REG(_x) REG_A5XX_ ## _x
34
35 #define COUNTER(_sel, _lo, _hi) { \
36 .select_reg = REG(_sel), \
37 .counter_reg_lo = REG(_lo), \
38 .counter_reg_hi = REG(_hi), \
39 }
40
41 #define COUNTER2(_sel, _lo, _hi, _en, _clr) { \
42 .select_reg = REG(_sel), \
43 .counter_reg_lo = REG(_lo), \
44 .counter_reg_hi = REG(_hi), \
45 .enable = REG(_en), \
46 .clear = REG(_clr), \
47 }
48
49 #define COUNTABLE(_selector, _query_type, _result_type) { \
50 .name = #_selector, \
51 .selector = _selector, \
52 .query_type = PIPE_DRIVER_QUERY_TYPE_ ## _query_type, \
53 .result_type = PIPE_DRIVER_QUERY_RESULT_TYPE_ ## _result_type, \
54 }
55
56 #define GROUP(_name, _counters, _countables) { \
57 .name = _name, \
58 .num_counters = ARRAY_SIZE(_counters), \
59 .counters = _counters, \
60 .num_countables = ARRAY_SIZE(_countables), \
61 .countables = _countables, \
62 }
63
64 static const struct fd_perfcntr_counter cp_counters[] = {
65 //RESERVED: for kernel
66 // COUNTER(CP_PERFCTR_CP_SEL_0, RBBM_PERFCTR_CP_0_LO, RBBM_PERFCTR_CP_0_HI),
67 COUNTER(CP_PERFCTR_CP_SEL_1, RBBM_PERFCTR_CP_1_LO, RBBM_PERFCTR_CP_1_HI),
68 COUNTER(CP_PERFCTR_CP_SEL_2, RBBM_PERFCTR_CP_2_LO, RBBM_PERFCTR_CP_2_HI),
69 COUNTER(CP_PERFCTR_CP_SEL_3, RBBM_PERFCTR_CP_3_LO, RBBM_PERFCTR_CP_3_HI),
70 COUNTER(CP_PERFCTR_CP_SEL_4, RBBM_PERFCTR_CP_4_LO, RBBM_PERFCTR_CP_4_HI),
71 COUNTER(CP_PERFCTR_CP_SEL_5, RBBM_PERFCTR_CP_5_LO, RBBM_PERFCTR_CP_5_HI),
72 COUNTER(CP_PERFCTR_CP_SEL_6, RBBM_PERFCTR_CP_6_LO, RBBM_PERFCTR_CP_6_HI),
73 COUNTER(CP_PERFCTR_CP_SEL_7, RBBM_PERFCTR_CP_7_LO, RBBM_PERFCTR_CP_7_HI),
74 };
75
76 static const struct fd_perfcntr_countable cp_countables[] = {
77 COUNTABLE(PERF_CP_ALWAYS_COUNT, UINT64, AVERAGE),
78 COUNTABLE(PERF_CP_BUSY_GFX_CORE_IDLE, UINT64, AVERAGE),
79 COUNTABLE(PERF_CP_BUSY_CYCLES, UINT64, AVERAGE),
80 COUNTABLE(PERF_CP_PFP_IDLE, UINT64, AVERAGE),
81 COUNTABLE(PERF_CP_PFP_BUSY_WORKING, UINT64, AVERAGE),
82 COUNTABLE(PERF_CP_PFP_STALL_CYCLES_ANY, UINT64, AVERAGE),
83 COUNTABLE(PERF_CP_PFP_STARVE_CYCLES_ANY, UINT64, AVERAGE),
84 COUNTABLE(PERF_CP_PFP_ICACHE_MISS, UINT64, AVERAGE),
85 COUNTABLE(PERF_CP_PFP_ICACHE_HIT, UINT64, AVERAGE),
86 COUNTABLE(PERF_CP_PFP_MATCH_PM4_PKT_PROFILE, UINT64, AVERAGE),
87 COUNTABLE(PERF_CP_ME_BUSY_WORKING, UINT64, AVERAGE),
88 COUNTABLE(PERF_CP_ME_IDLE, UINT64, AVERAGE),
89 COUNTABLE(PERF_CP_ME_STARVE_CYCLES_ANY, UINT64, AVERAGE),
90 COUNTABLE(PERF_CP_ME_FIFO_EMPTY_PFP_IDLE, UINT64, AVERAGE),
91 COUNTABLE(PERF_CP_ME_FIFO_EMPTY_PFP_BUSY, UINT64, AVERAGE),
92 COUNTABLE(PERF_CP_ME_FIFO_FULL_ME_BUSY, UINT64, AVERAGE),
93 COUNTABLE(PERF_CP_ME_FIFO_FULL_ME_NON_WORKING, UINT64, AVERAGE),
94 COUNTABLE(PERF_CP_ME_STALL_CYCLES_ANY, UINT64, AVERAGE),
95 COUNTABLE(PERF_CP_ME_ICACHE_MISS, UINT64, AVERAGE),
96 COUNTABLE(PERF_CP_ME_ICACHE_HIT, UINT64, AVERAGE),
97 COUNTABLE(PERF_CP_NUM_PREEMPTIONS, UINT64, AVERAGE),
98 COUNTABLE(PERF_CP_PREEMPTION_REACTION_DELAY, UINT64, AVERAGE),
99 COUNTABLE(PERF_CP_PREEMPTION_SWITCH_OUT_TIME, UINT64, AVERAGE),
100 COUNTABLE(PERF_CP_PREEMPTION_SWITCH_IN_TIME, UINT64, AVERAGE),
101 COUNTABLE(PERF_CP_DEAD_DRAWS_IN_BIN_RENDER, UINT64, AVERAGE),
102 COUNTABLE(PERF_CP_PREDICATED_DRAWS_KILLED, UINT64, AVERAGE),
103 COUNTABLE(PERF_CP_MODE_SWITCH, UINT64, AVERAGE),
104 COUNTABLE(PERF_CP_ZPASS_DONE, UINT64, AVERAGE),
105 COUNTABLE(PERF_CP_CONTEXT_DONE, UINT64, AVERAGE),
106 COUNTABLE(PERF_CP_CACHE_FLUSH, UINT64, AVERAGE),
107 COUNTABLE(PERF_CP_LONG_PREEMPTIONS, UINT64, AVERAGE),
108 };
109
110 static const struct fd_perfcntr_counter ccu_counters[] = {
111 COUNTER(RB_PERFCTR_CCU_SEL_0, RBBM_PERFCTR_CCU_0_LO, RBBM_PERFCTR_CCU_0_HI),
112 COUNTER(RB_PERFCTR_CCU_SEL_1, RBBM_PERFCTR_CCU_1_LO, RBBM_PERFCTR_CCU_1_HI),
113 COUNTER(RB_PERFCTR_CCU_SEL_2, RBBM_PERFCTR_CCU_2_LO, RBBM_PERFCTR_CCU_2_HI),
114 COUNTER(RB_PERFCTR_CCU_SEL_3, RBBM_PERFCTR_CCU_3_LO, RBBM_PERFCTR_CCU_3_HI),
115 };
116
117 static const struct fd_perfcntr_countable ccu_countables[] = {
118 COUNTABLE(PERF_CCU_BUSY_CYCLES, UINT64, AVERAGE),
119 COUNTABLE(PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN, UINT64, AVERAGE),
120 COUNTABLE(PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN, UINT64, AVERAGE),
121 COUNTABLE(PERF_CCU_STARVE_CYCLES_FLAG_RETURN, UINT64, AVERAGE),
122 COUNTABLE(PERF_CCU_DEPTH_BLOCKS, UINT64, AVERAGE),
123 COUNTABLE(PERF_CCU_COLOR_BLOCKS, UINT64, AVERAGE),
124 COUNTABLE(PERF_CCU_DEPTH_BLOCK_HIT, UINT64, AVERAGE),
125 COUNTABLE(PERF_CCU_COLOR_BLOCK_HIT, UINT64, AVERAGE),
126 COUNTABLE(PERF_CCU_PARTIAL_BLOCK_READ, UINT64, AVERAGE),
127 COUNTABLE(PERF_CCU_GMEM_READ, UINT64, AVERAGE),
128 COUNTABLE(PERF_CCU_GMEM_WRITE, UINT64, AVERAGE),
129 COUNTABLE(PERF_CCU_DEPTH_READ_FLAG0_COUNT, UINT64, AVERAGE),
130 COUNTABLE(PERF_CCU_DEPTH_READ_FLAG1_COUNT, UINT64, AVERAGE),
131 COUNTABLE(PERF_CCU_DEPTH_READ_FLAG2_COUNT, UINT64, AVERAGE),
132 COUNTABLE(PERF_CCU_DEPTH_READ_FLAG3_COUNT, UINT64, AVERAGE),
133 COUNTABLE(PERF_CCU_DEPTH_READ_FLAG4_COUNT, UINT64, AVERAGE),
134 COUNTABLE(PERF_CCU_COLOR_READ_FLAG0_COUNT, UINT64, AVERAGE),
135 COUNTABLE(PERF_CCU_COLOR_READ_FLAG1_COUNT, UINT64, AVERAGE),
136 COUNTABLE(PERF_CCU_COLOR_READ_FLAG2_COUNT, UINT64, AVERAGE),
137 COUNTABLE(PERF_CCU_COLOR_READ_FLAG3_COUNT, UINT64, AVERAGE),
138 COUNTABLE(PERF_CCU_COLOR_READ_FLAG4_COUNT, UINT64, AVERAGE),
139 COUNTABLE(PERF_CCU_2D_BUSY_CYCLES, UINT64, AVERAGE),
140 COUNTABLE(PERF_CCU_2D_RD_REQ, UINT64, AVERAGE),
141 COUNTABLE(PERF_CCU_2D_WR_REQ, UINT64, AVERAGE),
142 COUNTABLE(PERF_CCU_2D_REORDER_STARVE_CYCLES, UINT64, AVERAGE),
143 COUNTABLE(PERF_CCU_2D_PIXELS, UINT64, AVERAGE),
144 };
145
146 static const struct fd_perfcntr_counter tse_counters[] = {
147 COUNTER(GRAS_PERFCTR_TSE_SEL_0, RBBM_PERFCTR_TSE_0_LO, RBBM_PERFCTR_TSE_0_HI),
148 COUNTER(GRAS_PERFCTR_TSE_SEL_1, RBBM_PERFCTR_TSE_1_LO, RBBM_PERFCTR_TSE_1_HI),
149 COUNTER(GRAS_PERFCTR_TSE_SEL_2, RBBM_PERFCTR_TSE_2_LO, RBBM_PERFCTR_TSE_2_HI),
150 COUNTER(GRAS_PERFCTR_TSE_SEL_3, RBBM_PERFCTR_TSE_3_LO, RBBM_PERFCTR_TSE_3_HI),
151 };
152
153 static const struct fd_perfcntr_countable tse_countables[] = {
154 COUNTABLE(PERF_TSE_BUSY_CYCLES, UINT64, AVERAGE),
155 COUNTABLE(PERF_TSE_CLIPPING_CYCLES, UINT64, AVERAGE),
156 COUNTABLE(PERF_TSE_STALL_CYCLES_RAS, UINT64, AVERAGE),
157 COUNTABLE(PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE, UINT64, AVERAGE),
158 COUNTABLE(PERF_TSE_STALL_CYCLES_LRZ_ZPLANE, UINT64, AVERAGE),
159 COUNTABLE(PERF_TSE_STARVE_CYCLES_PC, UINT64, AVERAGE),
160 COUNTABLE(PERF_TSE_INPUT_PRIM, UINT64, AVERAGE),
161 COUNTABLE(PERF_TSE_INPUT_NULL_PRIM, UINT64, AVERAGE),
162 COUNTABLE(PERF_TSE_TRIVAL_REJ_PRIM, UINT64, AVERAGE),
163 COUNTABLE(PERF_TSE_CLIPPED_PRIM, UINT64, AVERAGE),
164 COUNTABLE(PERF_TSE_ZERO_AREA_PRIM, UINT64, AVERAGE),
165 COUNTABLE(PERF_TSE_FACENESS_CULLED_PRIM, UINT64, AVERAGE),
166 COUNTABLE(PERF_TSE_ZERO_PIXEL_PRIM, UINT64, AVERAGE),
167 COUNTABLE(PERF_TSE_OUTPUT_NULL_PRIM, UINT64, AVERAGE),
168 COUNTABLE(PERF_TSE_OUTPUT_VISIBLE_PRIM, UINT64, AVERAGE),
169 COUNTABLE(PERF_TSE_CINVOCATION, UINT64, AVERAGE),
170 COUNTABLE(PERF_TSE_CPRIMITIVES, UINT64, AVERAGE),
171 COUNTABLE(PERF_TSE_2D_INPUT_PRIM, UINT64, AVERAGE),
172 COUNTABLE(PERF_TSE_2D_ALIVE_CLCLES, UINT64, AVERAGE),
173 };
174
175 static const struct fd_perfcntr_counter ras_counters[] = {
176 COUNTER(GRAS_PERFCTR_RAS_SEL_0, RBBM_PERFCTR_RAS_0_LO, RBBM_PERFCTR_RAS_0_HI),
177 COUNTER(GRAS_PERFCTR_RAS_SEL_1, RBBM_PERFCTR_RAS_1_LO, RBBM_PERFCTR_RAS_1_HI),
178 COUNTER(GRAS_PERFCTR_RAS_SEL_2, RBBM_PERFCTR_RAS_2_LO, RBBM_PERFCTR_RAS_2_HI),
179 COUNTER(GRAS_PERFCTR_RAS_SEL_3, RBBM_PERFCTR_RAS_3_LO, RBBM_PERFCTR_RAS_3_HI),
180 };
181
182 static const struct fd_perfcntr_countable ras_countables[] = {
183 COUNTABLE(PERF_RAS_BUSY_CYCLES, UINT64, AVERAGE),
184 COUNTABLE(PERF_RAS_SUPERTILE_ACTIVE_CYCLES, UINT64, AVERAGE),
185 COUNTABLE(PERF_RAS_STALL_CYCLES_LRZ, UINT64, AVERAGE),
186 COUNTABLE(PERF_RAS_STARVE_CYCLES_TSE, UINT64, AVERAGE),
187 COUNTABLE(PERF_RAS_SUPER_TILES, UINT64, AVERAGE),
188 COUNTABLE(PERF_RAS_8X4_TILES, UINT64, AVERAGE),
189 COUNTABLE(PERF_RAS_MASKGEN_ACTIVE, UINT64, AVERAGE),
190 COUNTABLE(PERF_RAS_FULLY_COVERED_SUPER_TILES, UINT64, AVERAGE),
191 COUNTABLE(PERF_RAS_FULLY_COVERED_8X4_TILES, UINT64, AVERAGE),
192 COUNTABLE(PERF_RAS_PRIM_KILLED_INVISILBE, UINT64, AVERAGE),
193 };
194
195 static const struct fd_perfcntr_counter lrz_counters[] = {
196 COUNTER(GRAS_PERFCTR_LRZ_SEL_0, RBBM_PERFCTR_LRZ_0_LO, RBBM_PERFCTR_LRZ_0_HI),
197 COUNTER(GRAS_PERFCTR_LRZ_SEL_1, RBBM_PERFCTR_LRZ_1_LO, RBBM_PERFCTR_LRZ_1_HI),
198 COUNTER(GRAS_PERFCTR_LRZ_SEL_2, RBBM_PERFCTR_LRZ_2_LO, RBBM_PERFCTR_LRZ_2_HI),
199 COUNTER(GRAS_PERFCTR_LRZ_SEL_3, RBBM_PERFCTR_LRZ_3_LO, RBBM_PERFCTR_LRZ_3_HI),
200 };
201
202 static const struct fd_perfcntr_countable lrz_countables[] = {
203 COUNTABLE(PERF_LRZ_BUSY_CYCLES, UINT64, AVERAGE),
204 COUNTABLE(PERF_LRZ_STARVE_CYCLES_RAS, UINT64, AVERAGE),
205 COUNTABLE(PERF_LRZ_STALL_CYCLES_RB, UINT64, AVERAGE),
206 COUNTABLE(PERF_LRZ_STALL_CYCLES_VSC, UINT64, AVERAGE),
207 COUNTABLE(PERF_LRZ_STALL_CYCLES_VPC, UINT64, AVERAGE),
208 COUNTABLE(PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH, UINT64, AVERAGE),
209 COUNTABLE(PERF_LRZ_STALL_CYCLES_UCHE, UINT64, AVERAGE),
210 COUNTABLE(PERF_LRZ_LRZ_READ, UINT64, AVERAGE),
211 COUNTABLE(PERF_LRZ_LRZ_WRITE, UINT64, AVERAGE),
212 COUNTABLE(PERF_LRZ_READ_LATENCY, UINT64, AVERAGE),
213 COUNTABLE(PERF_LRZ_MERGE_CACHE_UPDATING, UINT64, AVERAGE),
214 COUNTABLE(PERF_LRZ_PRIM_KILLED_BY_MASKGEN, UINT64, AVERAGE),
215 COUNTABLE(PERF_LRZ_PRIM_KILLED_BY_LRZ, UINT64, AVERAGE),
216 COUNTABLE(PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ, UINT64, AVERAGE),
217 COUNTABLE(PERF_LRZ_FULL_8X8_TILES, UINT64, AVERAGE),
218 COUNTABLE(PERF_LRZ_PARTIAL_8X8_TILES, UINT64, AVERAGE),
219 COUNTABLE(PERF_LRZ_TILE_KILLED, UINT64, AVERAGE),
220 COUNTABLE(PERF_LRZ_TOTAL_PIXEL, UINT64, AVERAGE),
221 COUNTABLE(PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ, UINT64, AVERAGE),
222 };
223
224 static const struct fd_perfcntr_counter hlsq_counters[] = {
225 COUNTER(HLSQ_PERFCTR_HLSQ_SEL_0, RBBM_PERFCTR_HLSQ_0_LO, RBBM_PERFCTR_HLSQ_0_HI),
226 COUNTER(HLSQ_PERFCTR_HLSQ_SEL_1, RBBM_PERFCTR_HLSQ_1_LO, RBBM_PERFCTR_HLSQ_1_HI),
227 COUNTER(HLSQ_PERFCTR_HLSQ_SEL_2, RBBM_PERFCTR_HLSQ_2_LO, RBBM_PERFCTR_HLSQ_2_HI),
228 COUNTER(HLSQ_PERFCTR_HLSQ_SEL_3, RBBM_PERFCTR_HLSQ_3_LO, RBBM_PERFCTR_HLSQ_3_HI),
229 COUNTER(HLSQ_PERFCTR_HLSQ_SEL_4, RBBM_PERFCTR_HLSQ_4_LO, RBBM_PERFCTR_HLSQ_4_HI),
230 COUNTER(HLSQ_PERFCTR_HLSQ_SEL_5, RBBM_PERFCTR_HLSQ_5_LO, RBBM_PERFCTR_HLSQ_5_HI),
231 COUNTER(HLSQ_PERFCTR_HLSQ_SEL_6, RBBM_PERFCTR_HLSQ_6_LO, RBBM_PERFCTR_HLSQ_6_HI),
232 COUNTER(HLSQ_PERFCTR_HLSQ_SEL_7, RBBM_PERFCTR_HLSQ_7_LO, RBBM_PERFCTR_HLSQ_7_HI),
233 };
234
235 static const struct fd_perfcntr_countable hlsq_countables[] = {
236 COUNTABLE(PERF_HLSQ_BUSY_CYCLES, UINT64, AVERAGE),
237 COUNTABLE(PERF_HLSQ_STALL_CYCLES_UCHE, UINT64, AVERAGE),
238 COUNTABLE(PERF_HLSQ_STALL_CYCLES_SP_STATE, UINT64, AVERAGE),
239 COUNTABLE(PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE, UINT64, AVERAGE),
240 COUNTABLE(PERF_HLSQ_UCHE_LATENCY_CYCLES, UINT64, AVERAGE),
241 COUNTABLE(PERF_HLSQ_UCHE_LATENCY_COUNT, UINT64, AVERAGE),
242 COUNTABLE(PERF_HLSQ_FS_STAGE_32_WAVES, UINT64, AVERAGE),
243 COUNTABLE(PERF_HLSQ_FS_STAGE_64_WAVES, UINT64, AVERAGE),
244 COUNTABLE(PERF_HLSQ_QUADS, UINT64, AVERAGE),
245 COUNTABLE(PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE, UINT64, AVERAGE),
246 COUNTABLE(PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE, UINT64, AVERAGE),
247 COUNTABLE(PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE, UINT64, AVERAGE),
248 COUNTABLE(PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE, UINT64, AVERAGE),
249 COUNTABLE(PERF_HLSQ_CS_INVOCATIONS, UINT64, AVERAGE),
250 COUNTABLE(PERF_HLSQ_COMPUTE_DRAWCALLS, UINT64, AVERAGE),
251 };
252
253 static const struct fd_perfcntr_counter pc_counters[] = {
254 COUNTER(PC_PERFCTR_PC_SEL_0, RBBM_PERFCTR_PC_0_LO, RBBM_PERFCTR_PC_0_HI),
255 COUNTER(PC_PERFCTR_PC_SEL_1, RBBM_PERFCTR_PC_1_LO, RBBM_PERFCTR_PC_1_HI),
256 COUNTER(PC_PERFCTR_PC_SEL_2, RBBM_PERFCTR_PC_2_LO, RBBM_PERFCTR_PC_2_HI),
257 COUNTER(PC_PERFCTR_PC_SEL_3, RBBM_PERFCTR_PC_3_LO, RBBM_PERFCTR_PC_3_HI),
258 COUNTER(PC_PERFCTR_PC_SEL_4, RBBM_PERFCTR_PC_4_LO, RBBM_PERFCTR_PC_4_HI),
259 COUNTER(PC_PERFCTR_PC_SEL_5, RBBM_PERFCTR_PC_5_LO, RBBM_PERFCTR_PC_5_HI),
260 COUNTER(PC_PERFCTR_PC_SEL_6, RBBM_PERFCTR_PC_6_LO, RBBM_PERFCTR_PC_6_HI),
261 COUNTER(PC_PERFCTR_PC_SEL_7, RBBM_PERFCTR_PC_7_LO, RBBM_PERFCTR_PC_7_HI),
262 };
263
264 static const struct fd_perfcntr_countable pc_countables[] = {
265 COUNTABLE(PERF_PC_BUSY_CYCLES, UINT64, AVERAGE),
266 COUNTABLE(PERF_PC_WORKING_CYCLES, UINT64, AVERAGE),
267 COUNTABLE(PERF_PC_STALL_CYCLES_VFD, UINT64, AVERAGE),
268 COUNTABLE(PERF_PC_STALL_CYCLES_TSE, UINT64, AVERAGE),
269 COUNTABLE(PERF_PC_STALL_CYCLES_VPC, UINT64, AVERAGE),
270 COUNTABLE(PERF_PC_STALL_CYCLES_UCHE, UINT64, AVERAGE),
271 COUNTABLE(PERF_PC_STALL_CYCLES_TESS, UINT64, AVERAGE),
272 COUNTABLE(PERF_PC_STALL_CYCLES_TSE_ONLY, UINT64, AVERAGE),
273 COUNTABLE(PERF_PC_STALL_CYCLES_VPC_ONLY, UINT64, AVERAGE),
274 COUNTABLE(PERF_PC_PASS1_TF_STALL_CYCLES, UINT64, AVERAGE),
275 COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_INDEX, UINT64, AVERAGE),
276 COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR, UINT64, AVERAGE),
277 COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM, UINT64, AVERAGE),
278 COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_POSITION, UINT64, AVERAGE),
279 COUNTABLE(PERF_PC_STARVE_CYCLES_DI, UINT64, AVERAGE),
280 COUNTABLE(PERF_PC_VIS_STREAMS_LOADED, UINT64, AVERAGE),
281 COUNTABLE(PERF_PC_INSTANCES, UINT64, AVERAGE),
282 COUNTABLE(PERF_PC_VPC_PRIMITIVES, UINT64, AVERAGE),
283 COUNTABLE(PERF_PC_DEAD_PRIM, UINT64, AVERAGE),
284 COUNTABLE(PERF_PC_LIVE_PRIM, UINT64, AVERAGE),
285 COUNTABLE(PERF_PC_VERTEX_HITS, UINT64, AVERAGE),
286 COUNTABLE(PERF_PC_IA_VERTICES, UINT64, AVERAGE),
287 COUNTABLE(PERF_PC_IA_PRIMITIVES, UINT64, AVERAGE),
288 COUNTABLE(PERF_PC_GS_PRIMITIVES, UINT64, AVERAGE),
289 COUNTABLE(PERF_PC_HS_INVOCATIONS, UINT64, AVERAGE),
290 COUNTABLE(PERF_PC_DS_INVOCATIONS, UINT64, AVERAGE),
291 COUNTABLE(PERF_PC_VS_INVOCATIONS, UINT64, AVERAGE),
292 COUNTABLE(PERF_PC_GS_INVOCATIONS, UINT64, AVERAGE),
293 COUNTABLE(PERF_PC_DS_PRIMITIVES, UINT64, AVERAGE),
294 COUNTABLE(PERF_PC_VPC_POS_DATA_TRANSACTION, UINT64, AVERAGE),
295 COUNTABLE(PERF_PC_3D_DRAWCALLS, UINT64, AVERAGE),
296 COUNTABLE(PERF_PC_2D_DRAWCALLS, UINT64, AVERAGE),
297 COUNTABLE(PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS, UINT64, AVERAGE),
298 COUNTABLE(PERF_TESS_BUSY_CYCLES, UINT64, AVERAGE),
299 COUNTABLE(PERF_TESS_WORKING_CYCLES, UINT64, AVERAGE),
300 COUNTABLE(PERF_TESS_STALL_CYCLES_PC, UINT64, AVERAGE),
301 COUNTABLE(PERF_TESS_STARVE_CYCLES_PC, UINT64, AVERAGE),
302 };
303
304 static const struct fd_perfcntr_counter rb_counters[] = {
305 COUNTER(RB_PERFCTR_RB_SEL_0, RBBM_PERFCTR_RB_0_LO, RBBM_PERFCTR_RB_0_HI),
306 COUNTER(RB_PERFCTR_RB_SEL_1, RBBM_PERFCTR_RB_1_LO, RBBM_PERFCTR_RB_1_HI),
307 COUNTER(RB_PERFCTR_RB_SEL_2, RBBM_PERFCTR_RB_2_LO, RBBM_PERFCTR_RB_2_HI),
308 COUNTER(RB_PERFCTR_RB_SEL_3, RBBM_PERFCTR_RB_3_LO, RBBM_PERFCTR_RB_3_HI),
309 COUNTER(RB_PERFCTR_RB_SEL_4, RBBM_PERFCTR_RB_4_LO, RBBM_PERFCTR_RB_4_HI),
310 COUNTER(RB_PERFCTR_RB_SEL_5, RBBM_PERFCTR_RB_5_LO, RBBM_PERFCTR_RB_5_HI),
311 COUNTER(RB_PERFCTR_RB_SEL_6, RBBM_PERFCTR_RB_6_LO, RBBM_PERFCTR_RB_6_HI),
312 COUNTER(RB_PERFCTR_RB_SEL_7, RBBM_PERFCTR_RB_7_LO, RBBM_PERFCTR_RB_7_HI),
313 };
314
315 static const struct fd_perfcntr_countable rb_countables[] = {
316 COUNTABLE(PERF_RB_BUSY_CYCLES, UINT64, AVERAGE),
317 COUNTABLE(PERF_RB_STALL_CYCLES_CCU, UINT64, AVERAGE),
318 COUNTABLE(PERF_RB_STALL_CYCLES_HLSQ, UINT64, AVERAGE),
319 COUNTABLE(PERF_RB_STALL_CYCLES_FIFO0_FULL, UINT64, AVERAGE),
320 COUNTABLE(PERF_RB_STALL_CYCLES_FIFO1_FULL, UINT64, AVERAGE),
321 COUNTABLE(PERF_RB_STALL_CYCLES_FIFO2_FULL, UINT64, AVERAGE),
322 COUNTABLE(PERF_RB_STARVE_CYCLES_SP, UINT64, AVERAGE),
323 COUNTABLE(PERF_RB_STARVE_CYCLES_LRZ_TILE, UINT64, AVERAGE),
324 COUNTABLE(PERF_RB_STARVE_CYCLES_CCU, UINT64, AVERAGE),
325 COUNTABLE(PERF_RB_STARVE_CYCLES_Z_PLANE, UINT64, AVERAGE),
326 COUNTABLE(PERF_RB_STARVE_CYCLES_BARY_PLANE, UINT64, AVERAGE),
327 COUNTABLE(PERF_RB_Z_WORKLOAD, UINT64, AVERAGE),
328 COUNTABLE(PERF_RB_HLSQ_ACTIVE, UINT64, AVERAGE),
329 COUNTABLE(PERF_RB_Z_READ, UINT64, AVERAGE),
330 COUNTABLE(PERF_RB_Z_WRITE, UINT64, AVERAGE),
331 COUNTABLE(PERF_RB_C_READ, UINT64, AVERAGE),
332 COUNTABLE(PERF_RB_C_WRITE, UINT64, AVERAGE),
333 COUNTABLE(PERF_RB_TOTAL_PASS, UINT64, AVERAGE),
334 COUNTABLE(PERF_RB_Z_PASS, UINT64, AVERAGE),
335 COUNTABLE(PERF_RB_Z_FAIL, UINT64, AVERAGE),
336 COUNTABLE(PERF_RB_S_FAIL, UINT64, AVERAGE),
337 COUNTABLE(PERF_RB_BLENDED_FXP_COMPONENTS, UINT64, AVERAGE),
338 COUNTABLE(PERF_RB_BLENDED_FP16_COMPONENTS, UINT64, AVERAGE),
339 COUNTABLE(RB_RESERVED, UINT64, AVERAGE),
340 COUNTABLE(PERF_RB_2D_ALIVE_CYCLES, UINT64, AVERAGE),
341 COUNTABLE(PERF_RB_2D_STALL_CYCLES_A2D, UINT64, AVERAGE),
342 COUNTABLE(PERF_RB_2D_STARVE_CYCLES_SRC, UINT64, AVERAGE),
343 COUNTABLE(PERF_RB_2D_STARVE_CYCLES_SP, UINT64, AVERAGE),
344 COUNTABLE(PERF_RB_2D_STARVE_CYCLES_DST, UINT64, AVERAGE),
345 COUNTABLE(PERF_RB_2D_VALID_PIXELS, UINT64, AVERAGE),
346 };
347
348 static const struct fd_perfcntr_counter rbbm_counters[] = {
349 //RESERVED: for kernel
350 // COUNTER(RBBM_PERFCTR_RBBM_SEL_0, RBBM_PERFCTR_RBBM_0_LO, RBBM_PERFCTR_RBBM_0_HI),
351 COUNTER(RBBM_PERFCTR_RBBM_SEL_1, RBBM_PERFCTR_RBBM_1_LO, RBBM_PERFCTR_RBBM_1_HI),
352 COUNTER(RBBM_PERFCTR_RBBM_SEL_2, RBBM_PERFCTR_RBBM_2_LO, RBBM_PERFCTR_RBBM_2_HI),
353 COUNTER(RBBM_PERFCTR_RBBM_SEL_3, RBBM_PERFCTR_RBBM_3_LO, RBBM_PERFCTR_RBBM_3_HI),
354 };
355
356 static const struct fd_perfcntr_countable rbbm_countables[] = {
357 COUNTABLE(PERF_RBBM_ALWAYS_COUNT, UINT64, AVERAGE),
358 COUNTABLE(PERF_RBBM_ALWAYS_ON, UINT64, AVERAGE),
359 COUNTABLE(PERF_RBBM_TSE_BUSY, UINT64, AVERAGE),
360 COUNTABLE(PERF_RBBM_RAS_BUSY, UINT64, AVERAGE),
361 COUNTABLE(PERF_RBBM_PC_DCALL_BUSY, UINT64, AVERAGE),
362 COUNTABLE(PERF_RBBM_PC_VSD_BUSY, UINT64, AVERAGE),
363 COUNTABLE(PERF_RBBM_STATUS_MASKED, UINT64, AVERAGE),
364 COUNTABLE(PERF_RBBM_COM_BUSY, UINT64, AVERAGE),
365 COUNTABLE(PERF_RBBM_DCOM_BUSY, UINT64, AVERAGE),
366 COUNTABLE(PERF_RBBM_VBIF_BUSY, UINT64, AVERAGE),
367 COUNTABLE(PERF_RBBM_VSC_BUSY, UINT64, AVERAGE),
368 COUNTABLE(PERF_RBBM_TESS_BUSY, UINT64, AVERAGE),
369 COUNTABLE(PERF_RBBM_UCHE_BUSY, UINT64, AVERAGE),
370 COUNTABLE(PERF_RBBM_HLSQ_BUSY, UINT64, AVERAGE),
371 };
372
373 static const struct fd_perfcntr_counter sp_counters[] = {
374 //RESERVED: for kernel
375 // COUNTER(SP_PERFCTR_SP_SEL_0, RBBM_PERFCTR_SP_0_LO, RBBM_PERFCTR_SP_0_HI),
376 COUNTER(SP_PERFCTR_SP_SEL_1, RBBM_PERFCTR_SP_1_LO, RBBM_PERFCTR_SP_1_HI),
377 COUNTER(SP_PERFCTR_SP_SEL_2, RBBM_PERFCTR_SP_2_LO, RBBM_PERFCTR_SP_2_HI),
378 COUNTER(SP_PERFCTR_SP_SEL_3, RBBM_PERFCTR_SP_3_LO, RBBM_PERFCTR_SP_3_HI),
379 COUNTER(SP_PERFCTR_SP_SEL_4, RBBM_PERFCTR_SP_4_LO, RBBM_PERFCTR_SP_4_HI),
380 COUNTER(SP_PERFCTR_SP_SEL_5, RBBM_PERFCTR_SP_5_LO, RBBM_PERFCTR_SP_5_HI),
381 COUNTER(SP_PERFCTR_SP_SEL_6, RBBM_PERFCTR_SP_6_LO, RBBM_PERFCTR_SP_6_HI),
382 COUNTER(SP_PERFCTR_SP_SEL_7, RBBM_PERFCTR_SP_7_LO, RBBM_PERFCTR_SP_7_HI),
383 COUNTER(SP_PERFCTR_SP_SEL_8, RBBM_PERFCTR_SP_8_LO, RBBM_PERFCTR_SP_8_HI),
384 COUNTER(SP_PERFCTR_SP_SEL_9, RBBM_PERFCTR_SP_9_LO, RBBM_PERFCTR_SP_9_HI),
385 COUNTER(SP_PERFCTR_SP_SEL_10, RBBM_PERFCTR_SP_10_LO, RBBM_PERFCTR_SP_10_HI),
386 COUNTER(SP_PERFCTR_SP_SEL_11, RBBM_PERFCTR_SP_11_LO, RBBM_PERFCTR_SP_11_HI),
387 };
388
389 static const struct fd_perfcntr_countable sp_countables[] = {
390 COUNTABLE(PERF_SP_BUSY_CYCLES, UINT64, AVERAGE),
391 COUNTABLE(PERF_SP_ALU_WORKING_CYCLES, UINT64, AVERAGE),
392 COUNTABLE(PERF_SP_EFU_WORKING_CYCLES, UINT64, AVERAGE),
393 COUNTABLE(PERF_SP_STALL_CYCLES_VPC, UINT64, AVERAGE),
394 COUNTABLE(PERF_SP_STALL_CYCLES_TP, UINT64, AVERAGE),
395 COUNTABLE(PERF_SP_STALL_CYCLES_UCHE, UINT64, AVERAGE),
396 COUNTABLE(PERF_SP_STALL_CYCLES_RB, UINT64, AVERAGE),
397 COUNTABLE(PERF_SP_SCHEDULER_NON_WORKING, UINT64, AVERAGE),
398 COUNTABLE(PERF_SP_WAVE_CONTEXTS, UINT64, AVERAGE),
399 COUNTABLE(PERF_SP_WAVE_CONTEXT_CYCLES, UINT64, AVERAGE),
400 COUNTABLE(PERF_SP_FS_STAGE_WAVE_CYCLES, UINT64, AVERAGE),
401 COUNTABLE(PERF_SP_FS_STAGE_WAVE_SAMPLES, UINT64, AVERAGE),
402 COUNTABLE(PERF_SP_VS_STAGE_WAVE_CYCLES, UINT64, AVERAGE),
403 COUNTABLE(PERF_SP_VS_STAGE_WAVE_SAMPLES, UINT64, AVERAGE),
404 COUNTABLE(PERF_SP_FS_STAGE_DURATION_CYCLES, UINT64, AVERAGE),
405 COUNTABLE(PERF_SP_VS_STAGE_DURATION_CYCLES, UINT64, AVERAGE),
406 COUNTABLE(PERF_SP_WAVE_CTRL_CYCLES, UINT64, AVERAGE),
407 COUNTABLE(PERF_SP_WAVE_LOAD_CYCLES, UINT64, AVERAGE),
408 COUNTABLE(PERF_SP_WAVE_EMIT_CYCLES, UINT64, AVERAGE),
409 COUNTABLE(PERF_SP_WAVE_NOP_CYCLES, UINT64, AVERAGE),
410 COUNTABLE(PERF_SP_WAVE_WAIT_CYCLES, UINT64, AVERAGE),
411 COUNTABLE(PERF_SP_WAVE_FETCH_CYCLES, UINT64, AVERAGE),
412 COUNTABLE(PERF_SP_WAVE_IDLE_CYCLES, UINT64, AVERAGE),
413 COUNTABLE(PERF_SP_WAVE_END_CYCLES, UINT64, AVERAGE),
414 COUNTABLE(PERF_SP_WAVE_LONG_SYNC_CYCLES, UINT64, AVERAGE),
415 COUNTABLE(PERF_SP_WAVE_SHORT_SYNC_CYCLES, UINT64, AVERAGE),
416 COUNTABLE(PERF_SP_WAVE_JOIN_CYCLES, UINT64, AVERAGE),
417 COUNTABLE(PERF_SP_LM_LOAD_INSTRUCTIONS, UINT64, AVERAGE),
418 COUNTABLE(PERF_SP_LM_STORE_INSTRUCTIONS, UINT64, AVERAGE),
419 COUNTABLE(PERF_SP_LM_ATOMICS, UINT64, AVERAGE),
420 COUNTABLE(PERF_SP_GM_LOAD_INSTRUCTIONS, UINT64, AVERAGE),
421 COUNTABLE(PERF_SP_GM_STORE_INSTRUCTIONS, UINT64, AVERAGE),
422 COUNTABLE(PERF_SP_GM_ATOMICS, UINT64, AVERAGE),
423 COUNTABLE(PERF_SP_VS_STAGE_TEX_INSTRUCTIONS, UINT64, AVERAGE),
424 COUNTABLE(PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS, UINT64, AVERAGE),
425 COUNTABLE(PERF_SP_VS_STAGE_EFU_INSTRUCTIONS, UINT64, AVERAGE),
426 COUNTABLE(PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS, UINT64, AVERAGE),
427 COUNTABLE(PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS, UINT64, AVERAGE),
428 COUNTABLE(PERF_SP_FS_STAGE_TEX_INSTRUCTIONS, UINT64, AVERAGE),
429 COUNTABLE(PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS, UINT64, AVERAGE),
430 COUNTABLE(PERF_SP_FS_STAGE_EFU_INSTRUCTIONS, UINT64, AVERAGE),
431 COUNTABLE(PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS, UINT64, AVERAGE),
432 COUNTABLE(PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS, UINT64, AVERAGE),
433 COUNTABLE(PERF_SP_FS_STAGE_BARY_INSTRUCTIONS, UINT64, AVERAGE),
434 COUNTABLE(PERF_SP_VS_INSTRUCTIONS, UINT64, AVERAGE),
435 COUNTABLE(PERF_SP_FS_INSTRUCTIONS, UINT64, AVERAGE),
436 COUNTABLE(PERF_SP_ADDR_LOCK_COUNT, UINT64, AVERAGE),
437 COUNTABLE(PERF_SP_UCHE_READ_TRANS, UINT64, AVERAGE),
438 COUNTABLE(PERF_SP_UCHE_WRITE_TRANS, UINT64, AVERAGE),
439 COUNTABLE(PERF_SP_EXPORT_VPC_TRANS, UINT64, AVERAGE),
440 COUNTABLE(PERF_SP_EXPORT_RB_TRANS, UINT64, AVERAGE),
441 COUNTABLE(PERF_SP_PIXELS_KILLED, UINT64, AVERAGE),
442 COUNTABLE(PERF_SP_ICL1_REQUESTS, UINT64, AVERAGE),
443 COUNTABLE(PERF_SP_ICL1_MISSES, UINT64, AVERAGE),
444 COUNTABLE(PERF_SP_ICL0_REQUESTS, UINT64, AVERAGE),
445 COUNTABLE(PERF_SP_ICL0_MISSES, UINT64, AVERAGE),
446 COUNTABLE(PERF_SP_HS_INSTRUCTIONS, UINT64, AVERAGE),
447 COUNTABLE(PERF_SP_DS_INSTRUCTIONS, UINT64, AVERAGE),
448 COUNTABLE(PERF_SP_GS_INSTRUCTIONS, UINT64, AVERAGE),
449 COUNTABLE(PERF_SP_CS_INSTRUCTIONS, UINT64, AVERAGE),
450 COUNTABLE(PERF_SP_GPR_READ, UINT64, AVERAGE),
451 COUNTABLE(PERF_SP_GPR_WRITE, UINT64, AVERAGE),
452 COUNTABLE(PERF_SP_LM_CH0_REQUESTS, UINT64, AVERAGE),
453 COUNTABLE(PERF_SP_LM_CH1_REQUESTS, UINT64, AVERAGE),
454 COUNTABLE(PERF_SP_LM_BANK_CONFLICTS, UINT64, AVERAGE),
455 };
456
457 static const struct fd_perfcntr_counter tp_counters[] = {
458 COUNTER(TPL1_PERFCTR_TP_SEL_0, RBBM_PERFCTR_TP_0_LO, RBBM_PERFCTR_TP_0_HI),
459 COUNTER(TPL1_PERFCTR_TP_SEL_1, RBBM_PERFCTR_TP_1_LO, RBBM_PERFCTR_TP_1_HI),
460 COUNTER(TPL1_PERFCTR_TP_SEL_2, RBBM_PERFCTR_TP_2_LO, RBBM_PERFCTR_TP_2_HI),
461 COUNTER(TPL1_PERFCTR_TP_SEL_3, RBBM_PERFCTR_TP_3_LO, RBBM_PERFCTR_TP_3_HI),
462 COUNTER(TPL1_PERFCTR_TP_SEL_4, RBBM_PERFCTR_TP_4_LO, RBBM_PERFCTR_TP_4_HI),
463 COUNTER(TPL1_PERFCTR_TP_SEL_5, RBBM_PERFCTR_TP_5_LO, RBBM_PERFCTR_TP_5_HI),
464 COUNTER(TPL1_PERFCTR_TP_SEL_6, RBBM_PERFCTR_TP_6_LO, RBBM_PERFCTR_TP_6_HI),
465 COUNTER(TPL1_PERFCTR_TP_SEL_7, RBBM_PERFCTR_TP_7_LO, RBBM_PERFCTR_TP_7_HI),
466 };
467
468 static const struct fd_perfcntr_countable tp_countables[] = {
469 COUNTABLE(PERF_TP_BUSY_CYCLES, UINT64, AVERAGE),
470 COUNTABLE(PERF_TP_STALL_CYCLES_UCHE, UINT64, AVERAGE),
471 COUNTABLE(PERF_TP_LATENCY_CYCLES, UINT64, AVERAGE),
472 COUNTABLE(PERF_TP_LATENCY_TRANS, UINT64, AVERAGE),
473 COUNTABLE(PERF_TP_FLAG_CACHE_REQUEST_SAMPLES, UINT64, AVERAGE),
474 COUNTABLE(PERF_TP_FLAG_CACHE_REQUEST_LATENCY, UINT64, AVERAGE),
475 COUNTABLE(PERF_TP_L1_CACHELINE_REQUESTS, UINT64, AVERAGE),
476 COUNTABLE(PERF_TP_L1_CACHELINE_MISSES, UINT64, AVERAGE),
477 COUNTABLE(PERF_TP_SP_TP_TRANS, UINT64, AVERAGE),
478 COUNTABLE(PERF_TP_TP_SP_TRANS, UINT64, AVERAGE),
479 COUNTABLE(PERF_TP_OUTPUT_PIXELS, UINT64, AVERAGE),
480 COUNTABLE(PERF_TP_FILTER_WORKLOAD_16BIT, UINT64, AVERAGE),
481 COUNTABLE(PERF_TP_FILTER_WORKLOAD_32BIT, UINT64, AVERAGE),
482 COUNTABLE(PERF_TP_QUADS_RECEIVED, UINT64, AVERAGE),
483 COUNTABLE(PERF_TP_QUADS_OFFSET, UINT64, AVERAGE),
484 COUNTABLE(PERF_TP_QUADS_SHADOW, UINT64, AVERAGE),
485 COUNTABLE(PERF_TP_QUADS_ARRAY, UINT64, AVERAGE),
486 COUNTABLE(PERF_TP_QUADS_GRADIENT, UINT64, AVERAGE),
487 COUNTABLE(PERF_TP_QUADS_1D, UINT64, AVERAGE),
488 COUNTABLE(PERF_TP_QUADS_2D, UINT64, AVERAGE),
489 COUNTABLE(PERF_TP_QUADS_BUFFER, UINT64, AVERAGE),
490 COUNTABLE(PERF_TP_QUADS_3D, UINT64, AVERAGE),
491 COUNTABLE(PERF_TP_QUADS_CUBE, UINT64, AVERAGE),
492 COUNTABLE(PERF_TP_STATE_CACHE_REQUESTS, UINT64, AVERAGE),
493 COUNTABLE(PERF_TP_STATE_CACHE_MISSES, UINT64, AVERAGE),
494 COUNTABLE(PERF_TP_DIVERGENT_QUADS_RECEIVED, UINT64, AVERAGE),
495 COUNTABLE(PERF_TP_BINDLESS_STATE_CACHE_REQUESTS, UINT64, AVERAGE),
496 COUNTABLE(PERF_TP_BINDLESS_STATE_CACHE_MISSES, UINT64, AVERAGE),
497 COUNTABLE(PERF_TP_PRT_NON_RESIDENT_EVENTS, UINT64, AVERAGE),
498 COUNTABLE(PERF_TP_OUTPUT_PIXELS_POINT, UINT64, AVERAGE),
499 COUNTABLE(PERF_TP_OUTPUT_PIXELS_BILINEAR, UINT64, AVERAGE),
500 COUNTABLE(PERF_TP_OUTPUT_PIXELS_MIP, UINT64, AVERAGE),
501 COUNTABLE(PERF_TP_OUTPUT_PIXELS_ANISO, UINT64, AVERAGE),
502 COUNTABLE(PERF_TP_OUTPUT_PIXELS_ZERO_LOD, UINT64, AVERAGE),
503 COUNTABLE(PERF_TP_FLAG_CACHE_REQUESTS, UINT64, AVERAGE),
504 COUNTABLE(PERF_TP_FLAG_CACHE_MISSES, UINT64, AVERAGE),
505 COUNTABLE(PERF_TP_L1_5_L2_REQUESTS, UINT64, AVERAGE),
506 COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS, UINT64, AVERAGE),
507 COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS_POINT, UINT64, AVERAGE),
508 COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS_BILINEAR, UINT64, AVERAGE),
509 COUNTABLE(PERF_TP_2D_FILTER_WORKLOAD_16BIT, UINT64, AVERAGE),
510 COUNTABLE(PERF_TP_2D_FILTER_WORKLOAD_32BIT, UINT64, AVERAGE),
511 };
512
513 static const struct fd_perfcntr_counter uche_counters[] = {
514 COUNTER(UCHE_PERFCTR_UCHE_SEL_0, RBBM_PERFCTR_UCHE_0_LO, RBBM_PERFCTR_UCHE_0_HI),
515 COUNTER(UCHE_PERFCTR_UCHE_SEL_1, RBBM_PERFCTR_UCHE_1_LO, RBBM_PERFCTR_UCHE_1_HI),
516 COUNTER(UCHE_PERFCTR_UCHE_SEL_2, RBBM_PERFCTR_UCHE_2_LO, RBBM_PERFCTR_UCHE_2_HI),
517 COUNTER(UCHE_PERFCTR_UCHE_SEL_3, RBBM_PERFCTR_UCHE_3_LO, RBBM_PERFCTR_UCHE_3_HI),
518 COUNTER(UCHE_PERFCTR_UCHE_SEL_4, RBBM_PERFCTR_UCHE_4_LO, RBBM_PERFCTR_UCHE_4_HI),
519 COUNTER(UCHE_PERFCTR_UCHE_SEL_5, RBBM_PERFCTR_UCHE_5_LO, RBBM_PERFCTR_UCHE_5_HI),
520 COUNTER(UCHE_PERFCTR_UCHE_SEL_6, RBBM_PERFCTR_UCHE_6_LO, RBBM_PERFCTR_UCHE_6_HI),
521 COUNTER(UCHE_PERFCTR_UCHE_SEL_7, RBBM_PERFCTR_UCHE_7_LO, RBBM_PERFCTR_UCHE_7_HI),
522 };
523
524 static const struct fd_perfcntr_countable uche_countables[] = {
525 COUNTABLE(PERF_UCHE_BUSY_CYCLES, UINT64, AVERAGE),
526 COUNTABLE(PERF_UCHE_STALL_CYCLES_VBIF, UINT64, AVERAGE),
527 COUNTABLE(PERF_UCHE_VBIF_LATENCY_CYCLES, UINT64, AVERAGE),
528 COUNTABLE(PERF_UCHE_VBIF_LATENCY_SAMPLES, UINT64, AVERAGE),
529 COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_TP, UINT64, AVERAGE),
530 COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_VFD, UINT64, AVERAGE),
531 COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_HLSQ, UINT64, AVERAGE),
532 COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_LRZ, UINT64, AVERAGE),
533 COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_SP, UINT64, AVERAGE),
534 COUNTABLE(PERF_UCHE_READ_REQUESTS_TP, UINT64, AVERAGE),
535 COUNTABLE(PERF_UCHE_READ_REQUESTS_VFD, UINT64, AVERAGE),
536 COUNTABLE(PERF_UCHE_READ_REQUESTS_HLSQ, UINT64, AVERAGE),
537 COUNTABLE(PERF_UCHE_READ_REQUESTS_LRZ, UINT64, AVERAGE),
538 COUNTABLE(PERF_UCHE_READ_REQUESTS_SP, UINT64, AVERAGE),
539 COUNTABLE(PERF_UCHE_WRITE_REQUESTS_LRZ, UINT64, AVERAGE),
540 COUNTABLE(PERF_UCHE_WRITE_REQUESTS_SP, UINT64, AVERAGE),
541 COUNTABLE(PERF_UCHE_WRITE_REQUESTS_VPC, UINT64, AVERAGE),
542 COUNTABLE(PERF_UCHE_WRITE_REQUESTS_VSC, UINT64, AVERAGE),
543 COUNTABLE(PERF_UCHE_EVICTS, UINT64, AVERAGE),
544 COUNTABLE(PERF_UCHE_BANK_REQ0, UINT64, AVERAGE),
545 COUNTABLE(PERF_UCHE_BANK_REQ1, UINT64, AVERAGE),
546 COUNTABLE(PERF_UCHE_BANK_REQ2, UINT64, AVERAGE),
547 COUNTABLE(PERF_UCHE_BANK_REQ3, UINT64, AVERAGE),
548 COUNTABLE(PERF_UCHE_BANK_REQ4, UINT64, AVERAGE),
549 COUNTABLE(PERF_UCHE_BANK_REQ5, UINT64, AVERAGE),
550 COUNTABLE(PERF_UCHE_BANK_REQ6, UINT64, AVERAGE),
551 COUNTABLE(PERF_UCHE_BANK_REQ7, UINT64, AVERAGE),
552 COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_CH0, UINT64, AVERAGE),
553 COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_CH1, UINT64, AVERAGE),
554 COUNTABLE(PERF_UCHE_GMEM_READ_BEATS, UINT64, AVERAGE),
555 COUNTABLE(PERF_UCHE_FLAG_COUNT, UINT64, AVERAGE),
556 };
557
558 static const struct fd_perfcntr_counter vfd_counters[] = {
559 COUNTER(VFD_PERFCTR_VFD_SEL_0, RBBM_PERFCTR_VFD_0_LO, RBBM_PERFCTR_VFD_0_HI),
560 COUNTER(VFD_PERFCTR_VFD_SEL_1, RBBM_PERFCTR_VFD_1_LO, RBBM_PERFCTR_VFD_1_HI),
561 COUNTER(VFD_PERFCTR_VFD_SEL_2, RBBM_PERFCTR_VFD_2_LO, RBBM_PERFCTR_VFD_2_HI),
562 COUNTER(VFD_PERFCTR_VFD_SEL_3, RBBM_PERFCTR_VFD_3_LO, RBBM_PERFCTR_VFD_3_HI),
563 COUNTER(VFD_PERFCTR_VFD_SEL_4, RBBM_PERFCTR_VFD_4_LO, RBBM_PERFCTR_VFD_4_HI),
564 COUNTER(VFD_PERFCTR_VFD_SEL_5, RBBM_PERFCTR_VFD_5_LO, RBBM_PERFCTR_VFD_5_HI),
565 COUNTER(VFD_PERFCTR_VFD_SEL_6, RBBM_PERFCTR_VFD_6_LO, RBBM_PERFCTR_VFD_6_HI),
566 COUNTER(VFD_PERFCTR_VFD_SEL_7, RBBM_PERFCTR_VFD_7_LO, RBBM_PERFCTR_VFD_7_HI),
567 };
568
569 static const struct fd_perfcntr_countable vfd_countables[] = {
570 COUNTABLE(PERF_VFD_BUSY_CYCLES, UINT64, AVERAGE),
571 COUNTABLE(PERF_VFD_STALL_CYCLES_UCHE, UINT64, AVERAGE),
572 COUNTABLE(PERF_VFD_STALL_CYCLES_VPC_ALLOC, UINT64, AVERAGE),
573 COUNTABLE(PERF_VFD_STALL_CYCLES_MISS_VB, UINT64, AVERAGE),
574 COUNTABLE(PERF_VFD_STALL_CYCLES_MISS_Q, UINT64, AVERAGE),
575 COUNTABLE(PERF_VFD_STALL_CYCLES_SP_INFO, UINT64, AVERAGE),
576 COUNTABLE(PERF_VFD_STALL_CYCLES_SP_ATTR, UINT64, AVERAGE),
577 COUNTABLE(PERF_VFD_STALL_CYCLES_VFDP_VB, UINT64, AVERAGE),
578 COUNTABLE(PERF_VFD_STALL_CYCLES_VFDP_Q, UINT64, AVERAGE),
579 COUNTABLE(PERF_VFD_DECODER_PACKER_STALL, UINT64, AVERAGE),
580 COUNTABLE(PERF_VFD_STARVE_CYCLES_UCHE, UINT64, AVERAGE),
581 COUNTABLE(PERF_VFD_RBUFFER_FULL, UINT64, AVERAGE),
582 COUNTABLE(PERF_VFD_ATTR_INFO_FIFO_FULL, UINT64, AVERAGE),
583 COUNTABLE(PERF_VFD_DECODED_ATTRIBUTE_BYTES, UINT64, AVERAGE),
584 COUNTABLE(PERF_VFD_NUM_ATTRIBUTES, UINT64, AVERAGE),
585 COUNTABLE(PERF_VFD_INSTRUCTIONS, UINT64, AVERAGE),
586 COUNTABLE(PERF_VFD_UPPER_SHADER_FIBERS, UINT64, AVERAGE),
587 COUNTABLE(PERF_VFD_LOWER_SHADER_FIBERS, UINT64, AVERAGE),
588 COUNTABLE(PERF_VFD_MODE_0_FIBERS, UINT64, AVERAGE),
589 COUNTABLE(PERF_VFD_MODE_1_FIBERS, UINT64, AVERAGE),
590 COUNTABLE(PERF_VFD_MODE_2_FIBERS, UINT64, AVERAGE),
591 COUNTABLE(PERF_VFD_MODE_3_FIBERS, UINT64, AVERAGE),
592 COUNTABLE(PERF_VFD_MODE_4_FIBERS, UINT64, AVERAGE),
593 COUNTABLE(PERF_VFD_TOTAL_VERTICES, UINT64, AVERAGE),
594 COUNTABLE(PERF_VFD_NUM_ATTR_MISS, UINT64, AVERAGE),
595 COUNTABLE(PERF_VFD_1_BURST_REQ, UINT64, AVERAGE),
596 COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD, UINT64, AVERAGE),
597 COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD_INDEX, UINT64, AVERAGE),
598 COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD_PROG, UINT64, AVERAGE),
599 COUNTABLE(PERF_VFDP_STARVE_CYCLES_PC, UINT64, AVERAGE),
600 COUNTABLE(PERF_VFDP_VS_STAGE_32_WAVES, UINT64, AVERAGE),
601 };
602
603 static const struct fd_perfcntr_counter vpc_counters[] = {
604 COUNTER(VPC_PERFCTR_VPC_SEL_0, RBBM_PERFCTR_VPC_0_LO, RBBM_PERFCTR_VPC_0_HI),
605 COUNTER(VPC_PERFCTR_VPC_SEL_1, RBBM_PERFCTR_VPC_1_LO, RBBM_PERFCTR_VPC_1_HI),
606 COUNTER(VPC_PERFCTR_VPC_SEL_2, RBBM_PERFCTR_VPC_2_LO, RBBM_PERFCTR_VPC_2_HI),
607 COUNTER(VPC_PERFCTR_VPC_SEL_3, RBBM_PERFCTR_VPC_3_LO, RBBM_PERFCTR_VPC_3_HI),
608 };
609
610 static const struct fd_perfcntr_countable vpc_countables[] = {
611 COUNTABLE(PERF_VPC_BUSY_CYCLES, UINT64, AVERAGE),
612 COUNTABLE(PERF_VPC_WORKING_CYCLES, UINT64, AVERAGE),
613 COUNTABLE(PERF_VPC_STALL_CYCLES_UCHE, UINT64, AVERAGE),
614 COUNTABLE(PERF_VPC_STALL_CYCLES_VFD_WACK, UINT64, AVERAGE),
615 COUNTABLE(PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC, UINT64, AVERAGE),
616 COUNTABLE(PERF_VPC_STALL_CYCLES_PC, UINT64, AVERAGE),
617 COUNTABLE(PERF_VPC_STALL_CYCLES_SP_LM, UINT64, AVERAGE),
618 COUNTABLE(PERF_VPC_POS_EXPORT_STALL_CYCLES, UINT64, AVERAGE),
619 COUNTABLE(PERF_VPC_STARVE_CYCLES_SP, UINT64, AVERAGE),
620 COUNTABLE(PERF_VPC_STARVE_CYCLES_LRZ, UINT64, AVERAGE),
621 COUNTABLE(PERF_VPC_PC_PRIMITIVES, UINT64, AVERAGE),
622 COUNTABLE(PERF_VPC_SP_COMPONENTS, UINT64, AVERAGE),
623 COUNTABLE(PERF_VPC_SP_LM_PRIMITIVES, UINT64, AVERAGE),
624 COUNTABLE(PERF_VPC_SP_LM_COMPONENTS, UINT64, AVERAGE),
625 COUNTABLE(PERF_VPC_SP_LM_DWORDS, UINT64, AVERAGE),
626 COUNTABLE(PERF_VPC_STREAMOUT_COMPONENTS, UINT64, AVERAGE),
627 COUNTABLE(PERF_VPC_GRANT_PHASES, UINT64, AVERAGE),
628 };
629
630 static const struct fd_perfcntr_counter vsc_counters[] = {
631 COUNTER(VSC_PERFCTR_VSC_SEL_0, RBBM_PERFCTR_VSC_0_LO, RBBM_PERFCTR_VSC_0_HI),
632 COUNTER(VSC_PERFCTR_VSC_SEL_1, RBBM_PERFCTR_VSC_1_LO, RBBM_PERFCTR_VSC_1_HI),
633 };
634
635 static const struct fd_perfcntr_countable vsc_countables[] = {
636 COUNTABLE(PERF_VSC_BUSY_CYCLES, UINT64, AVERAGE),
637 COUNTABLE(PERF_VSC_WORKING_CYCLES, UINT64, AVERAGE),
638 COUNTABLE(PERF_VSC_STALL_CYCLES_UCHE, UINT64, AVERAGE),
639 COUNTABLE(PERF_VSC_EOT_NUM, UINT64, AVERAGE),
640 };
641
642 /* VBIF counters probably not too userful for userspace, and they make
643 * frameretrace take many more passes to collect all the metrics, so
644 * for now let's hide them.
645 */
646 #if 0
647 /* VBIF counters break the pattern a bit, with enable and clear regs: */
648 static const struct fd_perfcntr_counter vbif_counters[] = {
649 COUNTER2(VBIF_PERF_CNT_SEL0, VBIF_PERF_CNT_LOW0, VBIF_PERF_CNT_HIGH0, VBIF_PERF_CNT_EN0, VBIF_PERF_CNT_CLR0),
650 COUNTER2(VBIF_PERF_CNT_SEL1, VBIF_PERF_CNT_LOW1, VBIF_PERF_CNT_HIGH1, VBIF_PERF_CNT_EN1, VBIF_PERF_CNT_CLR1),
651 COUNTER2(VBIF_PERF_CNT_SEL2, VBIF_PERF_CNT_LOW2, VBIF_PERF_CNT_HIGH2, VBIF_PERF_CNT_EN2, VBIF_PERF_CNT_CLR2),
652 COUNTER2(VBIF_PERF_CNT_SEL3, VBIF_PERF_CNT_LOW3, VBIF_PERF_CNT_HIGH3, VBIF_PERF_CNT_EN3, VBIF_PERF_CNT_CLR3),
653 };
654
655 static const struct fd_perfcntr_countable vbif_countables[] = {
656 COUNTABLE(AXI_READ_REQUESTS_ID_0, UINT64, AVERAGE),
657 COUNTABLE(AXI_READ_REQUESTS_ID_1, UINT64, AVERAGE),
658 COUNTABLE(AXI_READ_REQUESTS_ID_2, UINT64, AVERAGE),
659 COUNTABLE(AXI_READ_REQUESTS_ID_3, UINT64, AVERAGE),
660 COUNTABLE(AXI_READ_REQUESTS_ID_4, UINT64, AVERAGE),
661 COUNTABLE(AXI_READ_REQUESTS_ID_5, UINT64, AVERAGE),
662 COUNTABLE(AXI_READ_REQUESTS_ID_6, UINT64, AVERAGE),
663 COUNTABLE(AXI_READ_REQUESTS_ID_7, UINT64, AVERAGE),
664 COUNTABLE(AXI_READ_REQUESTS_ID_8, UINT64, AVERAGE),
665 COUNTABLE(AXI_READ_REQUESTS_ID_9, UINT64, AVERAGE),
666 COUNTABLE(AXI_READ_REQUESTS_ID_10, UINT64, AVERAGE),
667 COUNTABLE(AXI_READ_REQUESTS_ID_11, UINT64, AVERAGE),
668 COUNTABLE(AXI_READ_REQUESTS_ID_12, UINT64, AVERAGE),
669 COUNTABLE(AXI_READ_REQUESTS_ID_13, UINT64, AVERAGE),
670 COUNTABLE(AXI_READ_REQUESTS_ID_14, UINT64, AVERAGE),
671 COUNTABLE(AXI_READ_REQUESTS_ID_15, UINT64, AVERAGE),
672 COUNTABLE(AXI0_READ_REQUESTS_TOTAL, UINT64, AVERAGE),
673 COUNTABLE(AXI1_READ_REQUESTS_TOTAL, UINT64, AVERAGE),
674 COUNTABLE(AXI2_READ_REQUESTS_TOTAL, UINT64, AVERAGE),
675 COUNTABLE(AXI3_READ_REQUESTS_TOTAL, UINT64, AVERAGE),
676 COUNTABLE(AXI_READ_REQUESTS_TOTAL, UINT64, AVERAGE),
677 COUNTABLE(AXI_WRITE_REQUESTS_ID_0, UINT64, AVERAGE),
678 COUNTABLE(AXI_WRITE_REQUESTS_ID_1, UINT64, AVERAGE),
679 COUNTABLE(AXI_WRITE_REQUESTS_ID_2, UINT64, AVERAGE),
680 COUNTABLE(AXI_WRITE_REQUESTS_ID_3, UINT64, AVERAGE),
681 COUNTABLE(AXI_WRITE_REQUESTS_ID_4, UINT64, AVERAGE),
682 COUNTABLE(AXI_WRITE_REQUESTS_ID_5, UINT64, AVERAGE),
683 COUNTABLE(AXI_WRITE_REQUESTS_ID_6, UINT64, AVERAGE),
684 COUNTABLE(AXI_WRITE_REQUESTS_ID_7, UINT64, AVERAGE),
685 COUNTABLE(AXI_WRITE_REQUESTS_ID_8, UINT64, AVERAGE),
686 COUNTABLE(AXI_WRITE_REQUESTS_ID_9, UINT64, AVERAGE),
687 COUNTABLE(AXI_WRITE_REQUESTS_ID_10, UINT64, AVERAGE),
688 COUNTABLE(AXI_WRITE_REQUESTS_ID_11, UINT64, AVERAGE),
689 COUNTABLE(AXI_WRITE_REQUESTS_ID_12, UINT64, AVERAGE),
690 COUNTABLE(AXI_WRITE_REQUESTS_ID_13, UINT64, AVERAGE),
691 COUNTABLE(AXI_WRITE_REQUESTS_ID_14, UINT64, AVERAGE),
692 COUNTABLE(AXI_WRITE_REQUESTS_ID_15, UINT64, AVERAGE),
693 COUNTABLE(AXI0_WRITE_REQUESTS_TOTAL, UINT64, AVERAGE),
694 COUNTABLE(AXI1_WRITE_REQUESTS_TOTAL, UINT64, AVERAGE),
695 COUNTABLE(AXI2_WRITE_REQUESTS_TOTAL, UINT64, AVERAGE),
696 COUNTABLE(AXI3_WRITE_REQUESTS_TOTAL, UINT64, AVERAGE),
697 COUNTABLE(AXI_WRITE_REQUESTS_TOTAL, UINT64, AVERAGE),
698 COUNTABLE(AXI_TOTAL_REQUESTS, UINT64, AVERAGE),
699 COUNTABLE(AXI_READ_DATA_BEATS_ID_0, UINT64, AVERAGE),
700 COUNTABLE(AXI_READ_DATA_BEATS_ID_1, UINT64, AVERAGE),
701 COUNTABLE(AXI_READ_DATA_BEATS_ID_2, UINT64, AVERAGE),
702 COUNTABLE(AXI_READ_DATA_BEATS_ID_3, UINT64, AVERAGE),
703 COUNTABLE(AXI_READ_DATA_BEATS_ID_4, UINT64, AVERAGE),
704 COUNTABLE(AXI_READ_DATA_BEATS_ID_5, UINT64, AVERAGE),
705 COUNTABLE(AXI_READ_DATA_BEATS_ID_6, UINT64, AVERAGE),
706 COUNTABLE(AXI_READ_DATA_BEATS_ID_7, UINT64, AVERAGE),
707 COUNTABLE(AXI_READ_DATA_BEATS_ID_8, UINT64, AVERAGE),
708 COUNTABLE(AXI_READ_DATA_BEATS_ID_9, UINT64, AVERAGE),
709 COUNTABLE(AXI_READ_DATA_BEATS_ID_10, UINT64, AVERAGE),
710 COUNTABLE(AXI_READ_DATA_BEATS_ID_11, UINT64, AVERAGE),
711 COUNTABLE(AXI_READ_DATA_BEATS_ID_12, UINT64, AVERAGE),
712 COUNTABLE(AXI_READ_DATA_BEATS_ID_13, UINT64, AVERAGE),
713 COUNTABLE(AXI_READ_DATA_BEATS_ID_14, UINT64, AVERAGE),
714 COUNTABLE(AXI_READ_DATA_BEATS_ID_15, UINT64, AVERAGE),
715 COUNTABLE(AXI0_READ_DATA_BEATS_TOTAL, UINT64, AVERAGE),
716 COUNTABLE(AXI1_READ_DATA_BEATS_TOTAL, UINT64, AVERAGE),
717 COUNTABLE(AXI2_READ_DATA_BEATS_TOTAL, UINT64, AVERAGE),
718 COUNTABLE(AXI3_READ_DATA_BEATS_TOTAL, UINT64, AVERAGE),
719 COUNTABLE(AXI_READ_DATA_BEATS_TOTAL, UINT64, AVERAGE),
720 COUNTABLE(AXI_WRITE_DATA_BEATS_ID_0, UINT64, AVERAGE),
721 COUNTABLE(AXI_WRITE_DATA_BEATS_ID_1, UINT64, AVERAGE),
722 COUNTABLE(AXI_WRITE_DATA_BEATS_ID_2, UINT64, AVERAGE),
723 COUNTABLE(AXI_WRITE_DATA_BEATS_ID_3, UINT64, AVERAGE),
724 COUNTABLE(AXI_WRITE_DATA_BEATS_ID_4, UINT64, AVERAGE),
725 COUNTABLE(AXI_WRITE_DATA_BEATS_ID_5, UINT64, AVERAGE),
726 COUNTABLE(AXI_WRITE_DATA_BEATS_ID_6, UINT64, AVERAGE),
727 COUNTABLE(AXI_WRITE_DATA_BEATS_ID_7, UINT64, AVERAGE),
728 COUNTABLE(AXI_WRITE_DATA_BEATS_ID_8, UINT64, AVERAGE),
729 COUNTABLE(AXI_WRITE_DATA_BEATS_ID_9, UINT64, AVERAGE),
730 COUNTABLE(AXI_WRITE_DATA_BEATS_ID_10, UINT64, AVERAGE),
731 COUNTABLE(AXI_WRITE_DATA_BEATS_ID_11, UINT64, AVERAGE),
732 COUNTABLE(AXI_WRITE_DATA_BEATS_ID_12, UINT64, AVERAGE),
733 COUNTABLE(AXI_WRITE_DATA_BEATS_ID_13, UINT64, AVERAGE),
734 COUNTABLE(AXI_WRITE_DATA_BEATS_ID_14, UINT64, AVERAGE),
735 COUNTABLE(AXI_WRITE_DATA_BEATS_ID_15, UINT64, AVERAGE),
736 COUNTABLE(AXI0_WRITE_DATA_BEATS_TOTAL, UINT64, AVERAGE),
737 COUNTABLE(AXI1_WRITE_DATA_BEATS_TOTAL, UINT64, AVERAGE),
738 COUNTABLE(AXI2_WRITE_DATA_BEATS_TOTAL, UINT64, AVERAGE),
739 COUNTABLE(AXI3_WRITE_DATA_BEATS_TOTAL, UINT64, AVERAGE),
740 COUNTABLE(AXI_WRITE_DATA_BEATS_TOTAL, UINT64, AVERAGE),
741 COUNTABLE(AXI_DATA_BEATS_TOTAL, UINT64, AVERAGE),
742 };
743 #endif
744
745 const struct fd_perfcntr_group a5xx_perfcntr_groups[] = {
746 GROUP("CP", cp_counters, cp_countables),
747 GROUP("CCU", ccu_counters, ccu_countables),
748 GROUP("TSE", tse_counters, tse_countables),
749 GROUP("RAS", ras_counters, ras_countables),
750 GROUP("LRZ", lrz_counters, lrz_countables),
751 GROUP("HLSQ", hlsq_counters, hlsq_countables),
752 GROUP("PC", pc_counters, pc_countables),
753 GROUP("RB", rb_counters, rb_countables),
754 GROUP("RBBM", rbbm_counters, rbbm_countables),
755 GROUP("SP", sp_counters, sp_countables),
756 GROUP("TP", tp_counters, tp_countables),
757 GROUP("UCHE", uche_counters, uche_countables),
758 GROUP("VFD", vfd_counters, vfd_countables),
759 GROUP("VPC", vpc_counters, vpc_countables),
760 GROUP("VSC", vsc_counters, vsc_countables),
761 // GROUP("VBIF", vbif_counters, vbif_countables),
762 };
763
764 const unsigned a5xx_num_perfcntr_groups = ARRAY_SIZE(a5xx_perfcntr_groups);
765
766 #endif /* FD5_PERFCNTR_H_ */