2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/u_format.h"
32 #include "util/bitset.h"
34 #include "freedreno_program.h"
36 #include "fd5_program.h"
38 #include "fd5_texture.h"
39 #include "fd5_format.h"
41 static struct ir3_shader
*
42 create_shader_stateobj(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
,
45 struct fd_context
*ctx
= fd_context(pctx
);
46 struct ir3_compiler
*compiler
= ctx
->screen
->compiler
;
47 return ir3_shader_create(compiler
, cso
, type
, &ctx
->debug
);
51 fd5_fp_state_create(struct pipe_context
*pctx
,
52 const struct pipe_shader_state
*cso
)
54 return create_shader_stateobj(pctx
, cso
, SHADER_FRAGMENT
);
58 fd5_fp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
60 struct ir3_shader
*so
= hwcso
;
61 ir3_shader_destroy(so
);
65 fd5_vp_state_create(struct pipe_context
*pctx
,
66 const struct pipe_shader_state
*cso
)
68 return create_shader_stateobj(pctx
, cso
, SHADER_VERTEX
);
72 fd5_vp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
74 struct ir3_shader
*so
= hwcso
;
75 ir3_shader_destroy(so
);
79 fd5_emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
81 const struct ir3_info
*si
= &so
->info
;
82 enum a4xx_state_block sb
= fd4_stage2shadersb(so
->type
);
83 enum a4xx_state_src src
;
86 if (fd_mesa_debug
& FD_DBG_DIRECT
) {
89 bin
= fd_bo_map(so
->bo
);
96 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + sz
);
97 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
98 CP_LOAD_STATE4_0_STATE_SRC(src
) |
99 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
100 CP_LOAD_STATE4_0_NUM_UNIT(so
->instrlen
));
102 OUT_RING(ring
, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
103 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER
));
104 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
106 OUT_RELOC(ring
, so
->bo
, 0,
107 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER
), 0);
110 /* for how clever coverity is, it is sometimes rather dull, and
111 * doesn't realize that the only case where bin==NULL, sz==0:
113 assume(bin
|| (sz
== 0));
115 for (i
= 0; i
< sz
; i
++) {
116 OUT_RING(ring
, bin
[i
]);
120 /* Add any missing varyings needed for stream-out. Otherwise varyings not
121 * used by fragment shader will be stripped out.
124 link_stream_out(struct ir3_shader_linkage
*l
, const struct ir3_shader_variant
*v
)
126 const struct pipe_stream_output_info
*strmout
= &v
->shader
->stream_output
;
129 * First, any stream-out varyings not already in linkage map (ie. also
130 * consumed by frag shader) need to be added:
132 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
133 const struct pipe_stream_output
*out
= &strmout
->output
[i
];
134 unsigned k
= out
->register_index
;
136 (1 << (out
->num_components
+ out
->start_component
)) - 1;
137 unsigned idx
, nextloc
= 0;
139 /* psize/pos need to be the last entries in linkage map, and will
140 * get added link_stream_out, so skip over them:
142 if ((v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
) ||
143 (v
->outputs
[k
].slot
== VARYING_SLOT_POS
))
146 for (idx
= 0; idx
< l
->cnt
; idx
++) {
147 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
149 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
152 /* add if not already in linkage map: */
154 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
156 /* expand component-mask if needed, ie streaming out all components
157 * but frag shader doesn't consume all components:
159 if (compmask
& ~l
->var
[idx
].compmask
) {
160 l
->var
[idx
].compmask
|= compmask
;
161 l
->max_loc
= MAX2(l
->max_loc
,
162 l
->var
[idx
].loc
+ util_last_bit(l
->var
[idx
].compmask
));
167 /* TODO maybe some of this we could pre-compute once rather than having
168 * so much draw-time logic?
171 emit_stream_out(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*v
,
172 struct ir3_shader_linkage
*l
)
174 const struct pipe_stream_output_info
*strmout
= &v
->shader
->stream_output
;
175 unsigned ncomp
[PIPE_MAX_SO_BUFFERS
] = {0};
176 unsigned prog
[align(l
->max_loc
, 2) / 2];
178 memset(prog
, 0, sizeof(prog
));
180 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
181 const struct pipe_stream_output
*out
= &strmout
->output
[i
];
182 unsigned k
= out
->register_index
;
185 ncomp
[out
->output_buffer
] += out
->num_components
;
187 /* linkage map sorted by order frag shader wants things, so
188 * a bit less ideal here..
190 for (idx
= 0; idx
< l
->cnt
; idx
++)
191 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
194 debug_assert(idx
< l
->cnt
);
196 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
197 unsigned c
= j
+ out
->start_component
;
198 unsigned loc
= l
->var
[idx
].loc
+ c
;
199 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
202 prog
[loc
/2] |= A5XX_VPC_SO_PROG_B_EN
|
203 A5XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
204 A5XX_VPC_SO_PROG_B_OFF(off
* 4);
206 prog
[loc
/2] |= A5XX_VPC_SO_PROG_A_EN
|
207 A5XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
208 A5XX_VPC_SO_PROG_A_OFF(off
* 4);
213 OUT_PKT7(ring
, CP_CONTEXT_REG_BUNCH
, 12 + (2 * ARRAY_SIZE(prog
)));
214 OUT_RING(ring
, REG_A5XX_VPC_SO_BUF_CNTL
);
215 OUT_RING(ring
, A5XX_VPC_SO_BUF_CNTL_ENABLE
|
216 COND(ncomp
[0] > 0, A5XX_VPC_SO_BUF_CNTL_BUF0
) |
217 COND(ncomp
[1] > 0, A5XX_VPC_SO_BUF_CNTL_BUF1
) |
218 COND(ncomp
[2] > 0, A5XX_VPC_SO_BUF_CNTL_BUF2
) |
219 COND(ncomp
[3] > 0, A5XX_VPC_SO_BUF_CNTL_BUF3
));
220 OUT_RING(ring
, REG_A5XX_VPC_SO_NCOMP(0));
221 OUT_RING(ring
, ncomp
[0]);
222 OUT_RING(ring
, REG_A5XX_VPC_SO_NCOMP(1));
223 OUT_RING(ring
, ncomp
[1]);
224 OUT_RING(ring
, REG_A5XX_VPC_SO_NCOMP(2));
225 OUT_RING(ring
, ncomp
[2]);
226 OUT_RING(ring
, REG_A5XX_VPC_SO_NCOMP(3));
227 OUT_RING(ring
, ncomp
[3]);
228 OUT_RING(ring
, REG_A5XX_VPC_SO_CNTL
);
229 OUT_RING(ring
, A5XX_VPC_SO_CNTL_ENABLE
);
230 for (unsigned i
= 0; i
< ARRAY_SIZE(prog
); i
++) {
231 OUT_RING(ring
, REG_A5XX_VPC_SO_PROG
);
232 OUT_RING(ring
, prog
[i
]);
237 const struct ir3_shader_variant
*v
;
238 const struct ir3_info
*i
;
239 /* const sizes are in units of 4 * vec4 */
242 /* instr sizes are in units of 16 instructions */
257 setup_stages(struct fd5_emit
*emit
, struct stage
*s
)
261 s
[VS
].v
= fd5_emit_get_vp(emit
);
262 s
[FS
].v
= fd5_emit_get_fp(emit
);
264 s
[HS
].v
= s
[DS
].v
= s
[GS
].v
= NULL
; /* for now */
266 for (i
= 0; i
< MAX_STAGES
; i
++) {
268 s
[i
].i
= &s
[i
].v
->info
;
269 /* constlen is in units of 4 * vec4: */
270 s
[i
].constlen
= align(s
[i
].v
->constlen
, 4) / 4;
271 /* instrlen is already in units of 16 instr.. although
272 * probably we should ditch that and not make the compiler
273 * care about instruction group size of a3xx vs a5xx
275 s
[i
].instrlen
= s
[i
].v
->instrlen
;
283 /* NOTE: at least for gles2, blob partitions VS at bottom of const
284 * space and FS taking entire remaining space. We probably don't
285 * need to do that the same way, but for now mimic what the blob
286 * does to make it easier to diff against register values from blob
288 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
289 * is run from external memory.
291 if ((s
[VS
].instrlen
+ s
[FS
].instrlen
) > 64) {
292 /* prioritize FS for internal memory: */
293 if (s
[FS
].instrlen
< 64) {
294 /* if FS can fit, kick VS out to external memory: */
296 } else if (s
[VS
].instrlen
< 64) {
297 /* otherwise if VS can fit, kick out FS: */
300 /* neither can fit, run both from external memory: */
306 unsigned constoff
= 0;
307 for (i
= 0; i
< MAX_STAGES
; i
++) {
308 s
[i
].constoff
= constoff
;
309 constoff
+= s
[i
].constlen
;
313 s
[FS
].instroff
= 64 - s
[FS
].instrlen
;
314 s
[HS
].instroff
= s
[DS
].instroff
= s
[GS
].instroff
= s
[FS
].instroff
;
318 fd5_program_emit(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
319 struct fd5_emit
*emit
)
321 struct stage s
[MAX_STAGES
];
322 uint32_t pos_regid
, psize_regid
, color_regid
[8];
323 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
, samp_mask_regid
;
324 uint32_t vcoord_regid
, vertex_regid
, instance_regid
;
325 enum a3xx_threadsize fssz
;
326 uint8_t psize_loc
= ~0;
329 setup_stages(emit
, s
);
331 fssz
= (s
[FS
].i
->max_reg
>= 24) ? TWO_QUADS
: FOUR_QUADS
;
333 pos_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_POS
);
334 psize_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_PSIZ
);
335 vertex_regid
= ir3_find_sysval_regid(s
[VS
].v
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
336 instance_regid
= ir3_find_sysval_regid(s
[VS
].v
, SYSTEM_VALUE_INSTANCE_ID
);
338 if (s
[FS
].v
->color0_mrt
) {
339 color_regid
[0] = color_regid
[1] = color_regid
[2] = color_regid
[3] =
340 color_regid
[4] = color_regid
[5] = color_regid
[6] = color_regid
[7] =
341 ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_COLOR
);
343 color_regid
[0] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA0
);
344 color_regid
[1] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA1
);
345 color_regid
[2] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA2
);
346 color_regid
[3] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA3
);
347 color_regid
[4] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA4
);
348 color_regid
[5] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA5
);
349 color_regid
[6] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA6
);
350 color_regid
[7] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA7
);
353 samp_id_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_SAMPLE_ID
);
354 samp_mask_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
355 face_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_FRONT_FACE
);
356 coord_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_FRAG_COORD
);
357 zwcoord_regid
= (coord_regid
== regid(63,0)) ? regid(63,0) : (coord_regid
+ 2);
358 vcoord_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_VARYING_COORD
);
360 /* we could probably divide this up into things that need to be
361 * emitted if frag-prog is dirty vs if vert-prog is dirty..
364 OUT_PKT4(ring
, REG_A5XX_HLSQ_VS_CONFIG
, 5);
365 OUT_RING(ring
, A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(s
[VS
].constoff
) |
366 A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(s
[VS
].instroff
) |
367 COND(s
[VS
].v
, A5XX_HLSQ_VS_CONFIG_ENABLED
));
368 OUT_RING(ring
, A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(s
[FS
].constoff
) |
369 A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(s
[FS
].instroff
) |
370 COND(s
[FS
].v
, A5XX_HLSQ_FS_CONFIG_ENABLED
));
371 OUT_RING(ring
, A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(s
[HS
].constoff
) |
372 A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(s
[HS
].instroff
) |
373 COND(s
[HS
].v
, A5XX_HLSQ_HS_CONFIG_ENABLED
));
374 OUT_RING(ring
, A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(s
[DS
].constoff
) |
375 A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(s
[DS
].instroff
) |
376 COND(s
[DS
].v
, A5XX_HLSQ_DS_CONFIG_ENABLED
));
377 OUT_RING(ring
, A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(s
[GS
].constoff
) |
378 A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(s
[GS
].instroff
) |
379 COND(s
[GS
].v
, A5XX_HLSQ_GS_CONFIG_ENABLED
));
381 OUT_PKT4(ring
, REG_A5XX_HLSQ_CS_CONFIG
, 1);
382 OUT_RING(ring
, 0x00000000);
384 OUT_PKT4(ring
, REG_A5XX_HLSQ_VS_CNTL
, 5);
385 OUT_RING(ring
, A5XX_HLSQ_VS_CNTL_INSTRLEN(s
[VS
].instrlen
) |
386 COND(s
[VS
].v
&& s
[VS
].v
->has_ssbo
, A5XX_HLSQ_VS_CNTL_SSBO_ENABLE
));
387 OUT_RING(ring
, A5XX_HLSQ_FS_CNTL_INSTRLEN(s
[FS
].instrlen
) |
388 COND(s
[FS
].v
&& s
[FS
].v
->has_ssbo
, A5XX_HLSQ_FS_CNTL_SSBO_ENABLE
));
389 OUT_RING(ring
, A5XX_HLSQ_HS_CNTL_INSTRLEN(s
[HS
].instrlen
) |
390 COND(s
[HS
].v
&& s
[HS
].v
->has_ssbo
, A5XX_HLSQ_HS_CNTL_SSBO_ENABLE
));
391 OUT_RING(ring
, A5XX_HLSQ_DS_CNTL_INSTRLEN(s
[DS
].instrlen
) |
392 COND(s
[DS
].v
&& s
[DS
].v
->has_ssbo
, A5XX_HLSQ_DS_CNTL_SSBO_ENABLE
));
393 OUT_RING(ring
, A5XX_HLSQ_GS_CNTL_INSTRLEN(s
[GS
].instrlen
) |
394 COND(s
[GS
].v
&& s
[GS
].v
->has_ssbo
, A5XX_HLSQ_GS_CNTL_SSBO_ENABLE
));
396 OUT_PKT4(ring
, REG_A5XX_SP_VS_CONFIG
, 5);
397 OUT_RING(ring
, A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(s
[VS
].constoff
) |
398 A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(s
[VS
].instroff
) |
399 COND(s
[VS
].v
, A5XX_SP_VS_CONFIG_ENABLED
));
400 OUT_RING(ring
, A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(s
[FS
].constoff
) |
401 A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(s
[FS
].instroff
) |
402 COND(s
[FS
].v
, A5XX_SP_FS_CONFIG_ENABLED
));
403 OUT_RING(ring
, A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(s
[HS
].constoff
) |
404 A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(s
[HS
].instroff
) |
405 COND(s
[HS
].v
, A5XX_SP_HS_CONFIG_ENABLED
));
406 OUT_RING(ring
, A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(s
[DS
].constoff
) |
407 A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(s
[DS
].instroff
) |
408 COND(s
[DS
].v
, A5XX_SP_DS_CONFIG_ENABLED
));
409 OUT_RING(ring
, A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(s
[GS
].constoff
) |
410 A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(s
[GS
].instroff
) |
411 COND(s
[GS
].v
, A5XX_SP_GS_CONFIG_ENABLED
));
413 OUT_PKT4(ring
, REG_A5XX_SP_CS_CONFIG
, 1);
414 OUT_RING(ring
, 0x00000000);
416 OUT_PKT4(ring
, REG_A5XX_HLSQ_VS_CONSTLEN
, 2);
417 OUT_RING(ring
, s
[VS
].constlen
); /* HLSQ_VS_CONSTLEN */
418 OUT_RING(ring
, s
[VS
].instrlen
); /* HLSQ_VS_INSTRLEN */
420 OUT_PKT4(ring
, REG_A5XX_HLSQ_FS_CONSTLEN
, 2);
421 OUT_RING(ring
, s
[FS
].constlen
); /* HLSQ_FS_CONSTLEN */
422 OUT_RING(ring
, s
[FS
].instrlen
); /* HLSQ_FS_INSTRLEN */
424 OUT_PKT4(ring
, REG_A5XX_HLSQ_HS_CONSTLEN
, 2);
425 OUT_RING(ring
, s
[HS
].constlen
); /* HLSQ_HS_CONSTLEN */
426 OUT_RING(ring
, s
[HS
].instrlen
); /* HLSQ_HS_INSTRLEN */
428 OUT_PKT4(ring
, REG_A5XX_HLSQ_DS_CONSTLEN
, 2);
429 OUT_RING(ring
, s
[DS
].constlen
); /* HLSQ_DS_CONSTLEN */
430 OUT_RING(ring
, s
[DS
].instrlen
); /* HLSQ_DS_INSTRLEN */
432 OUT_PKT4(ring
, REG_A5XX_HLSQ_GS_CONSTLEN
, 2);
433 OUT_RING(ring
, s
[GS
].constlen
); /* HLSQ_GS_CONSTLEN */
434 OUT_RING(ring
, s
[GS
].instrlen
); /* HLSQ_GS_INSTRLEN */
436 OUT_PKT4(ring
, REG_A5XX_HLSQ_CS_CONSTLEN
, 2);
437 OUT_RING(ring
, 0x00000000); /* HLSQ_CS_CONSTLEN */
438 OUT_RING(ring
, 0x00000000); /* HLSQ_CS_INSTRLEN */
440 OUT_PKT4(ring
, REG_A5XX_SP_VS_CTRL_REG0
, 1);
441 OUT_RING(ring
, A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s
[VS
].i
->max_half_reg
+ 1) |
442 A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s
[VS
].i
->max_reg
+ 1) |
443 0x6 | /* XXX seems to be always set? */
444 A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
445 COND(s
[VS
].v
->has_samp
, A5XX_SP_VS_CTRL_REG0_PIXLODENABLE
));
447 struct ir3_shader_linkage l
= {0};
448 ir3_link_shaders(&l
, s
[VS
].v
, s
[FS
].v
);
450 if ((s
[VS
].v
->shader
->stream_output
.num_outputs
> 0) &&
451 !emit
->key
.binning_pass
)
452 link_stream_out(&l
, s
[VS
].v
);
454 BITSET_DECLARE(varbs
, 128) = {0};
455 uint32_t *varmask
= (uint32_t *)varbs
;
457 for (i
= 0; i
< l
.cnt
; i
++)
458 for (j
= 0; j
< util_last_bit(l
.var
[i
].compmask
); j
++)
459 BITSET_SET(varbs
, l
.var
[i
].loc
+ j
);
461 OUT_PKT4(ring
, REG_A5XX_VPC_VAR_DISABLE(0), 4);
462 OUT_RING(ring
, ~varmask
[0]); /* VPC_VAR[0].DISABLE */
463 OUT_RING(ring
, ~varmask
[1]); /* VPC_VAR[1].DISABLE */
464 OUT_RING(ring
, ~varmask
[2]); /* VPC_VAR[2].DISABLE */
465 OUT_RING(ring
, ~varmask
[3]); /* VPC_VAR[3].DISABLE */
467 /* a5xx appends pos/psize to end of the linkage map: */
468 if (pos_regid
!= regid(63,0))
469 ir3_link_add(&l
, pos_regid
, 0xf, l
.max_loc
);
471 if (psize_regid
!= regid(63,0)) {
472 psize_loc
= l
.max_loc
;
473 ir3_link_add(&l
, psize_regid
, 0x1, l
.max_loc
);
476 if ((s
[VS
].v
->shader
->stream_output
.num_outputs
> 0) &&
477 !emit
->key
.binning_pass
) {
478 emit_stream_out(ring
, s
[VS
].v
, &l
);
480 OUT_PKT4(ring
, REG_A5XX_VPC_SO_OVERRIDE
, 1);
481 OUT_RING(ring
, 0x00000000);
483 OUT_PKT4(ring
, REG_A5XX_VPC_SO_OVERRIDE
, 1);
484 OUT_RING(ring
, A5XX_VPC_SO_OVERRIDE_SO_DISABLE
);
487 for (i
= 0, j
= 0; (i
< 16) && (j
< l
.cnt
); i
++) {
490 OUT_PKT4(ring
, REG_A5XX_SP_VS_OUT_REG(i
), 1);
492 reg
|= A5XX_SP_VS_OUT_REG_A_REGID(l
.var
[j
].regid
);
493 reg
|= A5XX_SP_VS_OUT_REG_A_COMPMASK(l
.var
[j
].compmask
);
496 reg
|= A5XX_SP_VS_OUT_REG_B_REGID(l
.var
[j
].regid
);
497 reg
|= A5XX_SP_VS_OUT_REG_B_COMPMASK(l
.var
[j
].compmask
);
503 for (i
= 0, j
= 0; (i
< 8) && (j
< l
.cnt
); i
++) {
506 OUT_PKT4(ring
, REG_A5XX_SP_VS_VPC_DST_REG(i
), 1);
508 reg
|= A5XX_SP_VS_VPC_DST_REG_OUTLOC0(l
.var
[j
++].loc
);
509 reg
|= A5XX_SP_VS_VPC_DST_REG_OUTLOC1(l
.var
[j
++].loc
);
510 reg
|= A5XX_SP_VS_VPC_DST_REG_OUTLOC2(l
.var
[j
++].loc
);
511 reg
|= A5XX_SP_VS_VPC_DST_REG_OUTLOC3(l
.var
[j
++].loc
);
516 OUT_PKT4(ring
, REG_A5XX_SP_VS_OBJ_START_LO
, 2);
517 OUT_RELOC(ring
, s
[VS
].v
->bo
, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
520 fd5_emit_shader(ring
, s
[VS
].v
);
522 // TODO depending on other bits in this reg (if any) set somewhere else?
523 OUT_PKT4(ring
, REG_A5XX_PC_PRIM_VTX_CNTL
, 1);
524 OUT_RING(ring
, COND(s
[VS
].v
->writes_psize
, A5XX_PC_PRIM_VTX_CNTL_PSIZE
));
526 OUT_PKT4(ring
, REG_A5XX_SP_PRIMITIVE_CNTL
, 1);
527 OUT_RING(ring
, A5XX_SP_PRIMITIVE_CNTL_VSOUT(l
.cnt
));
529 OUT_PKT4(ring
, REG_A5XX_VPC_CNTL_0
, 1);
530 OUT_RING(ring
, A5XX_VPC_CNTL_0_STRIDE_IN_VPC(l
.max_loc
) |
531 COND(s
[FS
].v
->total_in
> 0, A5XX_VPC_CNTL_0_VARYING
) |
532 COND(s
[FS
].v
->frag_coord
, A5XX_VPC_CNTL_0_VARYING
) |
535 fd5_context(ctx
)->max_loc
= l
.max_loc
;
537 if (emit
->key
.binning_pass
) {
538 OUT_PKT4(ring
, REG_A5XX_SP_FS_OBJ_START_LO
, 2);
539 OUT_RING(ring
, 0x00000000); /* SP_FS_OBJ_START_LO */
540 OUT_RING(ring
, 0x00000000); /* SP_FS_OBJ_START_HI */
542 OUT_PKT4(ring
, REG_A5XX_SP_FS_OBJ_START_LO
, 2);
543 OUT_RELOC(ring
, s
[FS
].v
->bo
, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
546 OUT_PKT4(ring
, REG_A5XX_HLSQ_CONTROL_0_REG
, 5);
547 OUT_RING(ring
, A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz
) |
548 A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(TWO_QUADS
) |
549 0x00000880); /* XXX HLSQ_CONTROL_0 */
550 OUT_RING(ring
, A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(63));
551 OUT_RING(ring
, A5XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
552 A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
553 A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samp_mask_regid
) |
554 0xfc000000); /* XXX */
555 OUT_RING(ring
, A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(vcoord_regid
) |
556 0xfcfcfc00); /* XXX */
557 OUT_RING(ring
, A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
558 A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
559 0x0000fcfc); /* XXX */
561 OUT_PKT4(ring
, REG_A5XX_SP_FS_CTRL_REG0
, 1);
562 OUT_RING(ring
, COND(s
[FS
].v
->total_in
> 0, A5XX_SP_FS_CTRL_REG0_VARYING
) |
563 COND(s
[FS
].v
->frag_coord
, A5XX_SP_FS_CTRL_REG0_VARYING
) |
564 0x40006 | /* XXX set pretty much everywhere */
565 A5XX_SP_FS_CTRL_REG0_THREADSIZE(fssz
) |
566 A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s
[FS
].i
->max_half_reg
+ 1) |
567 A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s
[FS
].i
->max_reg
+ 1) |
568 A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
569 COND(s
[FS
].v
->has_samp
, A5XX_SP_FS_CTRL_REG0_PIXLODENABLE
));
571 OUT_PKT4(ring
, REG_A5XX_HLSQ_UPDATE_CNTL
, 1);
572 OUT_RING(ring
, 0x020fffff); /* XXX */
574 OUT_PKT4(ring
, REG_A5XX_VPC_GS_SIV_CNTL
, 1);
575 OUT_RING(ring
, 0x0000ffff); /* XXX */
577 OUT_PKT4(ring
, REG_A5XX_SP_SP_CNTL
, 1);
578 OUT_RING(ring
, 0x00000010); /* XXX */
580 OUT_PKT4(ring
, REG_A5XX_GRAS_CNTL
, 1);
581 OUT_RING(ring
, COND(s
[FS
].v
->total_in
> 0, A5XX_GRAS_CNTL_VARYING
) |
582 COND(s
[FS
].v
->frag_coord
, A5XX_GRAS_CNTL_XCOORD
|
583 A5XX_GRAS_CNTL_YCOORD
|
584 A5XX_GRAS_CNTL_ZCOORD
|
585 A5XX_GRAS_CNTL_WCOORD
|
586 A5XX_GRAS_CNTL_UNK3
) |
587 COND(s
[FS
].v
->frag_face
, A5XX_GRAS_CNTL_UNK3
));
589 OUT_PKT4(ring
, REG_A5XX_RB_RENDER_CONTROL0
, 2);
590 OUT_RING(ring
, COND(s
[FS
].v
->total_in
> 0, A5XX_RB_RENDER_CONTROL0_VARYING
) |
591 COND(s
[FS
].v
->frag_coord
, A5XX_RB_RENDER_CONTROL0_XCOORD
|
592 A5XX_RB_RENDER_CONTROL0_YCOORD
|
593 A5XX_RB_RENDER_CONTROL0_ZCOORD
|
594 A5XX_RB_RENDER_CONTROL0_WCOORD
|
595 A5XX_RB_RENDER_CONTROL0_UNK3
) |
596 COND(s
[FS
].v
->frag_face
, A5XX_RB_RENDER_CONTROL0_UNK3
));
598 COND(samp_mask_regid
!= regid(63, 0),
599 A5XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
600 COND(s
[FS
].v
->frag_face
, A5XX_RB_RENDER_CONTROL1_FACENESS
) |
601 COND(samp_id_regid
!= regid(63, 0),
602 A5XX_RB_RENDER_CONTROL1_SAMPLEID
));
604 OUT_PKT4(ring
, REG_A5XX_SP_FS_OUTPUT_REG(0), 8);
605 for (i
= 0; i
< 8; i
++) {
606 OUT_RING(ring
, A5XX_SP_FS_OUTPUT_REG_REGID(color_regid
[i
]) |
607 COND(emit
->key
.half_precision
,
608 A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION
));
612 OUT_PKT4(ring
, REG_A5XX_VPC_PACK
, 1);
613 OUT_RING(ring
, A5XX_VPC_PACK_NUMNONPOSVAR(s
[FS
].v
->total_in
) |
614 A5XX_VPC_PACK_PSIZELOC(psize_loc
));
616 if (!emit
->key
.binning_pass
) {
617 uint32_t vinterp
[8], vpsrepl
[8];
619 memset(vinterp
, 0, sizeof(vinterp
));
620 memset(vpsrepl
, 0, sizeof(vpsrepl
));
622 /* looks like we need to do int varyings in the frag
623 * shader on a5xx (no flatshad reg? or a420.0 bug?):
626 * (sy)ldlv.u32 r0.x,l[r0.x], 1
627 * ldlv.u32 r0.y,l[r0.x+1], 1
628 * (ss)bary.f (ei)r63.x, 0, r0.x
629 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
631 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
633 * Possibly on later a5xx variants we'll be able to use
634 * something like the code below instead of workaround
637 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
638 for (j
= -1; (j
= ir3_next_varying(s
[FS
].v
, j
)) < (int)s
[FS
].v
->inputs_count
; ) {
639 /* NOTE: varyings are packed, so if compmask is 0xb
640 * then first, third, and fourth component occupy
641 * three consecutive varying slots:
643 unsigned compmask
= s
[FS
].v
->inputs
[j
].compmask
;
645 uint32_t inloc
= s
[FS
].v
->inputs
[j
].inloc
;
647 if ((s
[FS
].v
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) ||
648 (s
[FS
].v
->inputs
[j
].rasterflat
&& emit
->rasterflat
)) {
649 uint32_t loc
= inloc
;
651 for (i
= 0; i
< 4; i
++) {
652 if (compmask
& (1 << i
)) {
653 vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
654 //flatshade[loc / 32] |= 1 << (loc % 32);
660 gl_varying_slot slot
= s
[FS
].v
->inputs
[j
].slot
;
662 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
663 if (slot
>= VARYING_SLOT_VAR0
) {
664 unsigned texmask
= 1 << (slot
- VARYING_SLOT_VAR0
);
665 /* Replace the .xy coordinates with S/T from the point sprite. Set
666 * interpolation bits for .zw such that they become .01
668 if (emit
->sprite_coord_enable
& texmask
) {
669 /* mask is two 2-bit fields, where:
672 * '11' -> 1 - T (flip mode)
674 unsigned mask
= emit
->sprite_coord_mode
? 0b1101 : 0b1001;
675 uint32_t loc
= inloc
;
676 if (compmask
& 0x1) {
677 vpsrepl
[loc
/ 16] |= ((mask
>> 0) & 0x3) << ((loc
% 16) * 2);
680 if (compmask
& 0x2) {
681 vpsrepl
[loc
/ 16] |= ((mask
>> 2) & 0x3) << ((loc
% 16) * 2);
684 if (compmask
& 0x4) {
686 vinterp
[loc
/ 16] |= 0b10 << ((loc
% 16) * 2);
689 if (compmask
& 0x8) {
691 vinterp
[loc
/ 16] |= 0b11 << ((loc
% 16) * 2);
698 OUT_PKT4(ring
, REG_A5XX_VPC_VARYING_INTERP_MODE(0), 8);
699 for (i
= 0; i
< 8; i
++)
700 OUT_RING(ring
, vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
702 OUT_PKT4(ring
, REG_A5XX_VPC_VARYING_PS_REPL_MODE(0), 8);
703 for (i
= 0; i
< 8; i
++)
704 OUT_RING(ring
, vpsrepl
[i
]); /* VPC_VARYING_PS_REPL[i] */
707 if (!emit
->key
.binning_pass
)
709 fd5_emit_shader(ring
, s
[FS
].v
);
711 OUT_PKT4(ring
, REG_A5XX_VFD_CONTROL_1
, 5);
712 OUT_RING(ring
, A5XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
713 A5XX_VFD_CONTROL_1_REGID4INST(instance_regid
) |
715 OUT_RING(ring
, 0x0000fcfc); /* VFD_CONTROL_2 */
716 OUT_RING(ring
, 0x0000fcfc); /* VFD_CONTROL_3 */
717 OUT_RING(ring
, 0x000000fc); /* VFD_CONTROL_4 */
718 OUT_RING(ring
, 0x00000000); /* VFD_CONTROL_5 */
722 fd5_prog_init(struct pipe_context
*pctx
)
724 pctx
->create_fs_state
= fd5_fp_state_create
;
725 pctx
->delete_fs_state
= fd5_fp_state_delete
;
727 pctx
->create_vs_state
= fd5_vp_state_create
;
728 pctx
->delete_vs_state
= fd5_vp_state_delete
;