src/gallium/drivers/freedreno/a5xx/fd5_texture.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "pipe/p_state.h"
  28 #include "util/u_string.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_inlines.h"
  31 #include "util/format/u_format.h"
  32
  33 #include "fd5_texture.h"
  34 #include "fd5_format.h"
  35
  36 static enum a5xx_tex_clamp
  37 tex_clamp(unsigned wrap, bool clamp_to_edge, bool *needs_border)
  38 {
  39         /* Hardware does not support _CLAMP, but we emulate it: */
  40         if (wrap == PIPE_TEX_WRAP_CLAMP) {
  41                 wrap = (clamp_to_edge) ?
  42                         PIPE_TEX_WRAP_CLAMP_TO_EDGE : PIPE_TEX_WRAP_CLAMP_TO_BORDER;
  43         }
  44
  45         switch (wrap) {
  46         case PIPE_TEX_WRAP_REPEAT:
  47                 return A5XX_TEX_REPEAT;
  48         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
  49                 return A5XX_TEX_CLAMP_TO_EDGE;
  50         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
  51                 *needs_border = true;
  52                 return A5XX_TEX_CLAMP_TO_BORDER;
  53         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
  54                 /* only works for PoT.. need to emulate otherwise! */
  55                 return A5XX_TEX_MIRROR_CLAMP;
  56         case PIPE_TEX_WRAP_MIRROR_REPEAT:
  57                 return A5XX_TEX_MIRROR_REPEAT;
  58         case PIPE_TEX_WRAP_MIRROR_CLAMP:
  59         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
  60                 /* these two we could perhaps emulate, but we currently
  61                  * just don't advertise PIPE_CAP_TEXTURE_MIRROR_CLAMP
  62                  */
  63         default:
  64                 DBG("invalid wrap: %u", wrap);
  65                 return 0;
  66         }
  67 }
  68
  69 static enum a5xx_tex_filter
  70 tex_filter(unsigned filter, bool aniso)
  71 {
  72         switch (filter) {
  73         case PIPE_TEX_FILTER_NEAREST:
  74                 return A5XX_TEX_NEAREST;
  75         case PIPE_TEX_FILTER_LINEAR:
  76                 return aniso ? A5XX_TEX_ANISO : A5XX_TEX_LINEAR;
  77         default:
  78                 DBG("invalid filter: %u", filter);
  79                 return 0;
  80         }
  81 }
  82
  83 static void *
  84 fd5_sampler_state_create(struct pipe_context *pctx,
  85                 const struct pipe_sampler_state *cso)
  86 {
  87         struct fd5_sampler_stateobj *so = CALLOC_STRUCT(fd5_sampler_stateobj);
  88         unsigned aniso = util_last_bit(MIN2(cso->max_anisotropy >> 1, 8));
  89         bool miplinear = false;
  90         bool clamp_to_edge;
  91
  92         if (!so)
  93                 return NULL;
  94
  95         so->base = *cso;
  96
  97         if (cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR)
  98                 miplinear = true;
  99
 100         /*
 101          * For nearest filtering, _CLAMP means _CLAMP_TO_EDGE;  for linear
 102          * filtering, _CLAMP means _CLAMP_TO_BORDER while additionally
 103          * clamping the texture coordinates to [0.0, 1.0].
 104          *
 105          * The clamping will be taken care of in the shaders.  There are two
 106          * filters here, but let the minification one has a say.
 107          */
 108         clamp_to_edge = (cso->min_img_filter == PIPE_TEX_FILTER_NEAREST);
 109         if (!clamp_to_edge) {
 110                 so->saturate_s = (cso->wrap_s == PIPE_TEX_WRAP_CLAMP);
 111                 so->saturate_t = (cso->wrap_t == PIPE_TEX_WRAP_CLAMP);
 112                 so->saturate_r = (cso->wrap_r == PIPE_TEX_WRAP_CLAMP);
 113         }
 114
 115         so->needs_border = false;
 116         so->texsamp0 =
 117                 COND(miplinear, A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR) |
 118                 A5XX_TEX_SAMP_0_XY_MAG(tex_filter(cso->mag_img_filter, aniso)) |
 119                 A5XX_TEX_SAMP_0_XY_MIN(tex_filter(cso->min_img_filter, aniso)) |
 120                 A5XX_TEX_SAMP_0_ANISO(aniso) |
 121                 A5XX_TEX_SAMP_0_WRAP_S(tex_clamp(cso->wrap_s, clamp_to_edge, &so->needs_border)) |
 122                 A5XX_TEX_SAMP_0_WRAP_T(tex_clamp(cso->wrap_t, clamp_to_edge, &so->needs_border)) |
 123                 A5XX_TEX_SAMP_0_WRAP_R(tex_clamp(cso->wrap_r, clamp_to_edge, &so->needs_border));
 124
 125         so->texsamp1 =
 126                 COND(!cso->seamless_cube_map, A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF) |
 127                 COND(!cso->normalized_coords, A5XX_TEX_SAMP_1_UNNORM_COORDS);
 128
 129         so->texsamp0 |= A5XX_TEX_SAMP_0_LOD_BIAS(cso->lod_bias);
 130
 131         if (cso->min_mip_filter != PIPE_TEX_MIPFILTER_NONE) {
 132                 so->texsamp1 |=
 133                         A5XX_TEX_SAMP_1_MIN_LOD(cso->min_lod) |
 134                         A5XX_TEX_SAMP_1_MAX_LOD(cso->max_lod);
 135         } else {
 136                 /* If we're not doing mipmap filtering, we still need a slightly > 0
 137                  * LOD clamp so the HW can decide between min and mag filtering of
 138                  * level 0.
 139                  */
 140                 so->texsamp1 |=
 141                         A5XX_TEX_SAMP_1_MIN_LOD(MIN2(cso->min_lod, 0.125)) |
 142                         A5XX_TEX_SAMP_1_MAX_LOD(MIN2(cso->max_lod, 0.125));
 143         }
 144
 145         if (cso->compare_mode)
 146                 so->texsamp1 |= A5XX_TEX_SAMP_1_COMPARE_FUNC(cso->compare_func); /* maps 1:1 */
 147
 148         return so;
 149 }
 150
 151 static void
 152 fd5_sampler_states_bind(struct pipe_context *pctx,
 153                 enum pipe_shader_type shader, unsigned start,
 154                 unsigned nr, void **hwcso)
 155 {
 156         struct fd_context *ctx = fd_context(pctx);
 157         struct fd5_context *fd5_ctx = fd5_context(ctx);
 158         uint16_t saturate_s = 0, saturate_t = 0, saturate_r = 0;
 159         unsigned i;
 160
 161         if (!hwcso)
 162                 nr = 0;
 163
 164         for (i = 0; i < nr; i++) {
 165                 if (hwcso[i]) {
 166                         struct fd5_sampler_stateobj *sampler =
 167                                         fd5_sampler_stateobj(hwcso[i]);
 168                         if (sampler->saturate_s)
 169                                 saturate_s |= (1 << i);
 170                         if (sampler->saturate_t)
 171                                 saturate_t |= (1 << i);
 172                         if (sampler->saturate_r)
 173                                 saturate_r |= (1 << i);
 174                 }
 175         }
 176
 177         fd_sampler_states_bind(pctx, shader, start, nr, hwcso);
 178
 179         if (shader == PIPE_SHADER_FRAGMENT) {
 180                 fd5_ctx->fsaturate =
 181                         (saturate_s != 0) ||
 182                         (saturate_t != 0) ||
 183                         (saturate_r != 0);
 184                 fd5_ctx->fsaturate_s = saturate_s;
 185                 fd5_ctx->fsaturate_t = saturate_t;
 186                 fd5_ctx->fsaturate_r = saturate_r;
 187         } else if (shader == PIPE_SHADER_VERTEX) {
 188                 fd5_ctx->vsaturate =
 189                         (saturate_s != 0) ||
 190                         (saturate_t != 0) ||
 191                         (saturate_r != 0);
 192                 fd5_ctx->vsaturate_s = saturate_s;
 193                 fd5_ctx->vsaturate_t = saturate_t;
 194                 fd5_ctx->vsaturate_r = saturate_r;
 195         }
 196 }
 197
 198 static bool
 199 use_astc_srgb_workaround(struct pipe_context *pctx, enum pipe_format format)
 200 {
 201         return false;  // TODO check if this is still needed on a5xx
 202 }
 203
 204 static struct pipe_sampler_view *
 205 fd5_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 206                 const struct pipe_sampler_view *cso)
 207 {
 208         struct fd5_pipe_sampler_view *so = CALLOC_STRUCT(fd5_pipe_sampler_view);
 209         struct fd_resource *rsc = fd_resource(prsc);
 210         struct fdl_slice *slice = NULL;
 211         enum pipe_format format = cso->format;
 212         unsigned lvl, layers = 0;
 213
 214         if (!so)
 215                 return NULL;
 216
 217         if (format == PIPE_FORMAT_X32_S8X24_UINT) {
 218                 rsc = rsc->stencil;
 219                 format = rsc->base.format;
 220         }
 221
 222         so->base = *cso;
 223         pipe_reference(NULL, &prsc->reference);
 224         so->base.texture = prsc;
 225         so->base.reference.count = 1;
 226         so->base.context = pctx;
 227
 228         so->texconst0 =
 229                 A5XX_TEX_CONST_0_FMT(fd5_pipe2tex(format)) |
 230                 A5XX_TEX_CONST_0_SAMPLES(fd_msaa_samples(prsc->nr_samples)) |
 231                 fd5_tex_swiz(format, cso->swizzle_r, cso->swizzle_g,
 232                                 cso->swizzle_b, cso->swizzle_a);
 233
 234         /* NOTE: since we sample z24s8 using 8888_UINT format, the swizzle
 235          * we get isn't quite right.  Use SWAP(XYZW) as a cheap and cheerful
 236          * way to re-arrange things so stencil component is where the swiz
 237          * expects.
 238          *
 239          * Note that gallium expects stencil sampler to return (s,s,s,s)
 240          * which isn't quite true.  To make that happen we'd have to massage
 241          * the swizzle.  But in practice only the .x component is used.
 242          */
 243         if (format == PIPE_FORMAT_X24S8_UINT) {
 244                 so->texconst0 |= A5XX_TEX_CONST_0_SWAP(XYZW);
 245         }
 246
 247         if (util_format_is_srgb(format)) {
 248                 if (use_astc_srgb_workaround(pctx, format))
 249                         so->astc_srgb = true;
 250                 so->texconst0 |= A5XX_TEX_CONST_0_SRGB;
 251         }
 252
 253         if (cso->target == PIPE_BUFFER) {
 254                 unsigned elements = cso->u.buf.size / util_format_get_blocksize(format);
 255
 256                 lvl = 0;
 257                 so->texconst1 =
 258                         A5XX_TEX_CONST_1_WIDTH(elements) |
 259                         A5XX_TEX_CONST_1_HEIGHT(1);
 260                 so->texconst2 =
 261                         A5XX_TEX_CONST_2_FETCHSIZE(fd5_pipe2fetchsize(format)) |
 262                         A5XX_TEX_CONST_2_PITCH(elements * rsc->layout.cpp);
 263                 so->offset = cso->u.buf.offset;
 264         } else {
 265                 unsigned miplevels;
 266
 267                 lvl = fd_sampler_first_level(cso);
 268                 slice = fd_resource_slice(rsc, lvl);
 269                 miplevels = fd_sampler_last_level(cso) - lvl;
 270                 layers = cso->u.tex.last_layer - cso->u.tex.first_layer + 1;
 271
 272                 so->texconst0 |= A5XX_TEX_CONST_0_MIPLVLS(miplevels);
 273                 so->texconst1 =
 274                         A5XX_TEX_CONST_1_WIDTH(u_minify(prsc->width0, lvl)) |
 275                         A5XX_TEX_CONST_1_HEIGHT(u_minify(prsc->height0, lvl));
 276                 so->texconst2 =
 277                         A5XX_TEX_CONST_2_FETCHSIZE(fd5_pipe2fetchsize(format)) |
 278                         A5XX_TEX_CONST_2_PITCH(slice->pitch);
 279                 so->offset = fd_resource_offset(rsc, lvl, cso->u.tex.first_layer);
 280         }
 281
 282         so->texconst2 |= A5XX_TEX_CONST_2_TYPE(fd5_tex_type(cso->target));
 283
 284         switch (cso->target) {
 285         case PIPE_TEXTURE_RECT:
 286         case PIPE_TEXTURE_1D:
 287         case PIPE_TEXTURE_2D:
 288                 so->texconst3 =
 289                         A5XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size);
 290                 so->texconst5 =
 291                         A5XX_TEX_CONST_5_DEPTH(1);
 292                 break;
 293         case PIPE_TEXTURE_1D_ARRAY:
 294         case PIPE_TEXTURE_2D_ARRAY:
 295                 so->texconst3 =
 296                         A5XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size);
 297                 so->texconst5 =
 298                         A5XX_TEX_CONST_5_DEPTH(layers);
 299                 break;
 300         case PIPE_TEXTURE_CUBE:
 301         case PIPE_TEXTURE_CUBE_ARRAY:
 302                 so->texconst3 =
 303                         A5XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size);
 304                 so->texconst5 =
 305                         A5XX_TEX_CONST_5_DEPTH(layers / 6);
 306                 break;
 307         case PIPE_TEXTURE_3D:
 308                 so->texconst3 =
 309                         A5XX_TEX_CONST_3_ARRAY_PITCH(slice->size0);
 310                 so->texconst5 =
 311                         A5XX_TEX_CONST_5_DEPTH(u_minify(prsc->depth0, lvl));
 312                 break;
 313         default:
 314                 so->texconst3 = 0x00000000;
 315                 break;
 316         }
 317
 318         return &so->base;
 319 }
 320
 321 static void
 322 fd5_set_sampler_views(struct pipe_context *pctx, enum pipe_shader_type shader,
 323                 unsigned start, unsigned nr,
 324                 struct pipe_sampler_view **views)
 325 {
 326         struct fd_context *ctx = fd_context(pctx);
 327         struct fd5_context *fd5_ctx = fd5_context(ctx);
 328         uint16_t astc_srgb = 0;
 329         unsigned i;
 330
 331         for (i = 0; i < nr; i++) {
 332                 if (views[i]) {
 333                         struct fd5_pipe_sampler_view *view =
 334                                         fd5_pipe_sampler_view(views[i]);
 335                         if (view->astc_srgb)
 336                                 astc_srgb |= (1 << i);
 337                 }
 338         }
 339
 340         fd_set_sampler_views(pctx, shader, start, nr, views);
 341
 342         if (shader == PIPE_SHADER_FRAGMENT) {
 343                 fd5_ctx->fastc_srgb = astc_srgb;
 344         } else if (shader == PIPE_SHADER_VERTEX) {
 345                 fd5_ctx->vastc_srgb = astc_srgb;
 346         }
 347 }
 348
 349 void
 350 fd5_texture_init(struct pipe_context *pctx)
 351 {
 352         pctx->create_sampler_state = fd5_sampler_state_create;
 353         pctx->bind_sampler_states = fd5_sampler_states_bind;
 354         pctx->create_sampler_view = fd5_sampler_view_create;
 355         pctx->set_sampler_views = fd5_set_sampler_views;
 356 }