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freedreno: add screen lock wrappers
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_blitter.c
1 /*
2 * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "util/u_dump.h"
29 #include "util/half_float.h"
30
31 #include "freedreno_blitter.h"
32 #include "freedreno_fence.h"
33 #include "freedreno_log.h"
34 #include "freedreno_resource.h"
35
36 #include "fd6_blitter.h"
37 #include "fd6_format.h"
38 #include "fd6_emit.h"
39 #include "fd6_resource.h"
40 #include "fd6_pack.h"
41
42 /* Make sure none of the requested dimensions extend beyond the size of the
43 * resource. Not entirely sure why this happens, but sometimes it does, and
44 * w/ 2d blt doesn't have wrap modes like a sampler, so force those cases
45 * back to u_blitter
46 */
47 static bool
48 ok_dims(const struct pipe_resource *r, const struct pipe_box *b, int lvl)
49 {
50 int last_layer =
51 r->target == PIPE_TEXTURE_3D ? u_minify(r->depth0, lvl)
52 : r->array_size;
53
54 return (b->x >= 0) && (b->x + b->width <= u_minify(r->width0, lvl)) &&
55 (b->y >= 0) && (b->y + b->height <= u_minify(r->height0, lvl)) &&
56 (b->z >= 0) && (b->z + b->depth <= last_layer);
57 }
58
59 static bool
60 ok_format(enum pipe_format pfmt)
61 {
62 enum a6xx_format fmt = fd6_pipe2color(pfmt);
63
64 switch (pfmt) {
65 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
66 case PIPE_FORMAT_Z24X8_UNORM:
67 case PIPE_FORMAT_Z16_UNORM:
68 case PIPE_FORMAT_Z32_UNORM:
69 case PIPE_FORMAT_Z32_FLOAT:
70 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
71 case PIPE_FORMAT_S8_UINT:
72 return true;
73 default:
74 break;
75 }
76
77 if (fmt == ~0)
78 return false;
79
80 if (fd6_ifmt(fmt) == 0)
81 return false;
82
83 return true;
84 }
85
86 #define DEBUG_BLIT 0
87 #define DEBUG_BLIT_FALLBACK 0
88
89 #define fail_if(cond) \
90 do { \
91 if (cond) { \
92 if (DEBUG_BLIT_FALLBACK) { \
93 fprintf(stderr, "falling back: %s for blit:\n", #cond); \
94 util_dump_blit_info(stderr, info); \
95 fprintf(stderr, "\nsrc: "); \
96 util_dump_resource(stderr, info->src.resource); \
97 fprintf(stderr, "\ndst: "); \
98 util_dump_resource(stderr, info->dst.resource); \
99 fprintf(stderr, "\n"); \
100 } \
101 return false; \
102 } \
103 } while (0)
104
105 static bool
106 can_do_blit(const struct pipe_blit_info *info)
107 {
108 /* I think we can do scaling, but not in z dimension since that would
109 * require blending..
110 */
111 fail_if(info->dst.box.depth != info->src.box.depth);
112
113 /* Fail if unsupported format: */
114 fail_if(!ok_format(info->src.format));
115 fail_if(!ok_format(info->dst.format));
116
117 debug_assert(!util_format_is_compressed(info->src.format));
118 debug_assert(!util_format_is_compressed(info->dst.format));
119
120 fail_if(!ok_dims(info->src.resource, &info->src.box, info->src.level));
121
122 fail_if(!ok_dims(info->dst.resource, &info->dst.box, info->dst.level));
123
124 debug_assert(info->dst.box.width >= 0);
125 debug_assert(info->dst.box.height >= 0);
126 debug_assert(info->dst.box.depth >= 0);
127
128 fail_if(info->dst.resource->nr_samples > 1);
129
130 fail_if(info->window_rectangle_include);
131
132 const struct util_format_description *src_desc =
133 util_format_description(info->src.format);
134 const struct util_format_description *dst_desc =
135 util_format_description(info->dst.format);
136 const int common_channels = MIN2(src_desc->nr_channels, dst_desc->nr_channels);
137
138 if (info->mask & PIPE_MASK_RGBA) {
139 for (int i = 0; i < common_channels; i++) {
140 fail_if(memcmp(&src_desc->channel[i],
141 &dst_desc->channel[i],
142 sizeof(src_desc->channel[0])));
143 }
144 }
145
146 fail_if(info->alpha_blend);
147
148 return true;
149 }
150
151 static void
152 emit_setup(struct fd_batch *batch)
153 {
154 struct fd_ringbuffer *ring = batch->draw;
155
156 fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
157 fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
158 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
159 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_DEPTH, false);
160
161 /* normal BLIT_OP_SCALE operation needs bypass RB_CCU_CNTL */
162 OUT_WFI5(ring);
163 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
164 OUT_RING(ring, fd6_context(batch->ctx)->magic.RB_CCU_CNTL_bypass);
165 }
166
167 static uint32_t
168 blit_control(enum a6xx_format fmt, bool is_srgb)
169 {
170 enum a6xx_2d_ifmt ifmt = fd6_ifmt(fmt);
171
172 if (is_srgb) {
173 assert(ifmt == R2D_UNORM8);
174 ifmt = R2D_UNORM8_SRGB;
175 }
176
177 return A6XX_RB_2D_BLIT_CNTL_MASK(0xf) |
178 A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(fmt) |
179 A6XX_RB_2D_BLIT_CNTL_IFMT(ifmt);
180 }
181
182 /* buffers need to be handled specially since x/width can exceed the bounds
183 * supported by hw.. if necessary decompose into (potentially) two 2D blits
184 */
185 static void
186 emit_blit_buffer(struct fd_context *ctx, struct fd_ringbuffer *ring,
187 const struct pipe_blit_info *info)
188 {
189 const struct pipe_box *sbox = &info->src.box;
190 const struct pipe_box *dbox = &info->dst.box;
191 struct fd_resource *src, *dst;
192 unsigned sshift, dshift;
193
194 if (DEBUG_BLIT) {
195 fprintf(stderr, "buffer blit: ");
196 util_dump_blit_info(stderr, info);
197 fprintf(stderr, "\ndst resource: ");
198 util_dump_resource(stderr, info->dst.resource);
199 fprintf(stderr, "\nsrc resource: ");
200 util_dump_resource(stderr, info->src.resource);
201 fprintf(stderr, "\n");
202 }
203
204 src = fd_resource(info->src.resource);
205 dst = fd_resource(info->dst.resource);
206
207 debug_assert(src->layout.cpp == 1);
208 debug_assert(dst->layout.cpp == 1);
209 debug_assert(info->src.resource->format == info->dst.resource->format);
210 debug_assert((sbox->y == 0) && (sbox->height == 1));
211 debug_assert((dbox->y == 0) && (dbox->height == 1));
212 debug_assert((sbox->z == 0) && (sbox->depth == 1));
213 debug_assert((dbox->z == 0) && (dbox->depth == 1));
214 debug_assert(sbox->width == dbox->width);
215 debug_assert(info->src.level == 0);
216 debug_assert(info->dst.level == 0);
217
218 /*
219 * Buffers can have dimensions bigger than max width, remap into
220 * multiple 1d blits to fit within max dimension
221 *
222 * Note that blob uses .ARRAY_PITCH=128 for blitting buffers, which
223 * seems to prevent overfetch related faults. Not quite sure what
224 * the deal is there.
225 *
226 * Low 6 bits of SRC/DST addresses need to be zero (ie. address
227 * aligned to 64) so we need to shift src/dst x1/x2 to make up the
228 * difference. On top of already splitting up the blit so width
229 * isn't > 16k.
230 *
231 * We perhaps could do a bit better, if src and dst are aligned but
232 * in the worst case this means we have to split the copy up into
233 * 16k (0x4000) minus 64 (0x40).
234 */
235
236 sshift = sbox->x & 0x3f;
237 dshift = dbox->x & 0x3f;
238
239 OUT_PKT7(ring, CP_SET_MARKER, 1);
240 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
241
242 uint32_t blit_cntl = blit_control(FMT6_8_UNORM, false) | 0x20000000;
243 OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
244 OUT_RING(ring, blit_cntl);
245
246 OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
247 OUT_RING(ring, blit_cntl);
248
249 for (unsigned off = 0; off < sbox->width; off += (0x4000 - 0x40)) {
250 unsigned soff, doff, w, p;
251
252 soff = (sbox->x + off) & ~0x3f;
253 doff = (dbox->x + off) & ~0x3f;
254
255 w = MIN2(sbox->width - off, (0x4000 - 0x40));
256 p = align(w, 64);
257
258 debug_assert((soff + w) <= fd_bo_size(src->bo));
259 debug_assert((doff + w) <= fd_bo_size(dst->bo));
260
261 /*
262 * Emit source:
263 */
264 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 10);
265 OUT_RING(ring, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(FMT6_8_UNORM) |
266 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(TILE6_LINEAR) |
267 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(WZYX) |
268 0x500000);
269 OUT_RING(ring, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(sshift + w) |
270 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(1)); /* SP_PS_2D_SRC_SIZE */
271 OUT_RELOC(ring, src->bo, soff, 0, 0); /* SP_PS_2D_SRC_LO/HI */
272 OUT_RING(ring, A6XX_SP_PS_2D_SRC_PITCH_PITCH(p));
273
274 OUT_RING(ring, 0x00000000);
275 OUT_RING(ring, 0x00000000);
276 OUT_RING(ring, 0x00000000);
277 OUT_RING(ring, 0x00000000);
278 OUT_RING(ring, 0x00000000);
279
280 /*
281 * Emit destination:
282 */
283 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
284 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(FMT6_8_UNORM) |
285 A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
286 A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
287 OUT_RELOCW(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
288 OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(p));
289 OUT_RING(ring, 0x00000000);
290 OUT_RING(ring, 0x00000000);
291 OUT_RING(ring, 0x00000000);
292 OUT_RING(ring, 0x00000000);
293 OUT_RING(ring, 0x00000000);
294
295 /*
296 * Blit command:
297 */
298 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
299 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(sshift));
300 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(sshift + w - 1));
301 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(0));
302 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(0));
303
304 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
305 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dshift) | A6XX_GRAS_2D_DST_TL_Y(0));
306 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dshift + w - 1) | A6XX_GRAS_2D_DST_BR_Y(0));
307
308 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
309 OUT_RING(ring, 0x3f);
310 OUT_WFI5(ring);
311
312 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
313 OUT_RING(ring, 0);
314
315 OUT_PKT4(ring, REG_A6XX_SP_2D_SRC_FORMAT, 1);
316 OUT_RING(ring, 0xf180);
317
318 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
319 OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
320
321 OUT_PKT7(ring, CP_BLIT, 1);
322 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
323
324 OUT_WFI5(ring);
325
326 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
327 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
328 }
329 }
330
331 static void
332 emit_blit_or_clear_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
333 const struct pipe_blit_info *info, union pipe_color_union *color)
334 {
335 const struct pipe_box *sbox = &info->src.box;
336 const struct pipe_box *dbox = &info->dst.box;
337 struct fd_resource *src, *dst;
338 struct fdl_slice *sslice, *dslice;
339 enum a6xx_format sfmt, dfmt;
340 enum a6xx_tile_mode stile, dtile;
341 enum a3xx_color_swap sswap, dswap;
342 int sx1, sy1, sx2, sy2;
343 int dx1, dy1, dx2, dy2;
344
345 if (DEBUG_BLIT) {
346 fprintf(stderr, "texture blit: ");
347 util_dump_blit_info(stderr, info);
348 fprintf(stderr, "\ndst resource: ");
349 util_dump_resource(stderr, info->dst.resource);
350 fprintf(stderr, "\nsrc resource: ");
351 util_dump_resource(stderr, info->src.resource);
352 fprintf(stderr, "\n");
353 }
354
355 src = fd_resource(info->src.resource);
356 dst = fd_resource(info->dst.resource);
357
358 sslice = fd_resource_slice(src, info->src.level);
359 dslice = fd_resource_slice(dst, info->dst.level);
360
361 sfmt = fd6_pipe2color(info->src.format);
362 dfmt = fd6_pipe2color(info->dst.format);
363
364 stile = fd_resource_tile_mode(info->src.resource, info->src.level);
365 dtile = fd_resource_tile_mode(info->dst.resource, info->dst.level);
366
367 /* Linear levels of a tiled resource are always WZYX, so look at
368 * rsc->tile_mode to determine the swap.
369 */
370 sswap = fd6_resource_swap(src, info->src.format);
371 dswap = fd6_resource_swap(dst, info->dst.format);
372
373 uint32_t nr_samples = fd_resource_nr_samples(&dst->base);
374 sx1 = sbox->x * nr_samples;
375 sy1 = sbox->y;
376 sx2 = (sbox->x + sbox->width) * nr_samples - 1;
377 sy2 = sbox->y + sbox->height - 1;
378
379 dx1 = dbox->x * nr_samples;
380 dy1 = dbox->y;
381 dx2 = (dbox->x + dbox->width) * nr_samples - 1;
382 dy2 = dbox->y + dbox->height - 1;
383
384 uint32_t width = u_minify(src->base.width0, info->src.level) * nr_samples;
385 uint32_t height = u_minify(src->base.height0, info->src.level);
386
387 OUT_PKT7(ring, CP_SET_MARKER, 1);
388 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
389
390 uint32_t blit_cntl = blit_control(dfmt, util_format_is_srgb(info->dst.format));
391
392 if (color) {
393 blit_cntl |= A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR;
394
395 switch (info->dst.format) {
396 case PIPE_FORMAT_Z24X8_UNORM:
397 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
398 case PIPE_FORMAT_X24S8_UINT: {
399 uint32_t depth_unorm24 = color->f[0] * ((1u << 24) - 1);
400 uint8_t stencil = color->ui[1];
401 color->ui[0] = depth_unorm24 & 0xff;
402 color->ui[1] = (depth_unorm24 >> 8) & 0xff;
403 color->ui[2] = (depth_unorm24 >> 16) & 0xff;
404 color->ui[3] = stencil;
405
406 dfmt = FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
407 break;
408 }
409 case PIPE_FORMAT_B5G6R5_UNORM:
410 case PIPE_FORMAT_B5G5R5A1_UNORM:
411 case PIPE_FORMAT_B5G5R5X1_UNORM:
412 case PIPE_FORMAT_B4G4R4A4_UNORM:
413 color->ui[0] = float_to_ubyte(color->f[0]);
414 color->ui[1] = float_to_ubyte(color->f[1]);
415 color->ui[2] = float_to_ubyte(color->f[2]);
416 color->ui[3] = float_to_ubyte(color->f[3]);
417 break;
418 default:
419 break;
420 }
421
422 OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
423
424 switch (fd6_ifmt(dfmt)) {
425 case R2D_UNORM8:
426 case R2D_UNORM8_SRGB:
427 OUT_RING(ring, float_to_ubyte(color->f[0]));
428 OUT_RING(ring, float_to_ubyte(color->f[1]));
429 OUT_RING(ring, float_to_ubyte(color->f[2]));
430 OUT_RING(ring, float_to_ubyte(color->f[3]));
431 break;
432 case R2D_FLOAT16:
433 OUT_RING(ring, _mesa_float_to_half(color->f[0]));
434 OUT_RING(ring, _mesa_float_to_half(color->f[1]));
435 OUT_RING(ring, _mesa_float_to_half(color->f[2]));
436 OUT_RING(ring, _mesa_float_to_half(color->f[3]));
437 sfmt = FMT6_16_16_16_16_FLOAT;
438 break;
439
440 case R2D_FLOAT32:
441 case R2D_INT32:
442 case R2D_INT16:
443 case R2D_INT8:
444 case R2D_RAW:
445 default:
446 OUT_RING(ring, color->ui[0]);
447 OUT_RING(ring, color->ui[1]);
448 OUT_RING(ring, color->ui[2]);
449 OUT_RING(ring, color->ui[3]);
450 break;
451 }
452 }
453
454 if (dtile != stile)
455 blit_cntl |= 0x20000000;
456
457 if (info->scissor_enable) {
458 OUT_PKT4(ring, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
459 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(info->scissor.minx) |
460 A6XX_GRAS_RESOLVE_CNTL_1_Y(info->scissor.miny));
461 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(info->scissor.maxx - 1) |
462 A6XX_GRAS_RESOLVE_CNTL_1_Y(info->scissor.maxy - 1));
463 blit_cntl |= A6XX_RB_2D_BLIT_CNTL_SCISSOR;
464 }
465
466 OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
467 OUT_RING(ring, blit_cntl);
468
469 OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
470 OUT_RING(ring, blit_cntl);
471
472 for (unsigned i = 0; i < info->dst.box.depth; i++) {
473 unsigned soff = fd_resource_offset(src, info->src.level, sbox->z + i);
474 unsigned doff = fd_resource_offset(dst, info->dst.level, dbox->z + i);
475 bool subwc_enabled = fd_resource_ubwc_enabled(src, info->src.level);
476 bool dubwc_enabled = fd_resource_ubwc_enabled(dst, info->dst.level);
477
478 /*
479 * Emit source:
480 */
481 uint32_t filter = 0;
482 if (info->filter == PIPE_TEX_FILTER_LINEAR)
483 filter = A6XX_SP_PS_2D_SRC_INFO_FILTER;
484
485 enum a3xx_msaa_samples samples = fd_msaa_samples(src->base.nr_samples);
486
487 if (sfmt == FMT6_10_10_10_2_UNORM_DEST)
488 sfmt = FMT6_10_10_10_2_UNORM;
489
490 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 10);
491 OUT_RING(ring, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(sfmt) |
492 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(stile) |
493 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(sswap) |
494 A6XX_SP_PS_2D_SRC_INFO_SAMPLES(samples) |
495 COND(samples > MSAA_ONE && (info->mask & PIPE_MASK_RGBA),
496 A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE) |
497 COND(subwc_enabled, A6XX_SP_PS_2D_SRC_INFO_FLAGS) |
498 COND(util_format_is_srgb(info->src.format), A6XX_SP_PS_2D_SRC_INFO_SRGB) |
499 0x500000 | filter);
500 OUT_RING(ring, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(width) |
501 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(height)); /* SP_PS_2D_SRC_SIZE */
502 OUT_RELOC(ring, src->bo, soff, 0, 0); /* SP_PS_2D_SRC_LO/HI */
503 OUT_RING(ring, A6XX_SP_PS_2D_SRC_PITCH_PITCH(sslice->pitch));
504
505 OUT_RING(ring, 0x00000000);
506 OUT_RING(ring, 0x00000000);
507 OUT_RING(ring, 0x00000000);
508 OUT_RING(ring, 0x00000000);
509 OUT_RING(ring, 0x00000000);
510
511 if (subwc_enabled) {
512 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_FLAGS_LO, 6);
513 fd6_emit_flag_reference(ring, src, info->src.level, sbox->z + i);
514 OUT_RING(ring, 0x00000000);
515 OUT_RING(ring, 0x00000000);
516 OUT_RING(ring, 0x00000000);
517 }
518
519 /*
520 * Emit destination:
521 */
522 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
523 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(dfmt) |
524 A6XX_RB_2D_DST_INFO_TILE_MODE(dtile) |
525 A6XX_RB_2D_DST_INFO_COLOR_SWAP(dswap) |
526 COND(util_format_is_srgb(info->dst.format), A6XX_RB_2D_DST_INFO_SRGB) |
527 COND(dubwc_enabled, A6XX_RB_2D_DST_INFO_FLAGS));
528 OUT_RELOCW(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
529 OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(dslice->pitch));
530 OUT_RING(ring, 0x00000000);
531 OUT_RING(ring, 0x00000000);
532 OUT_RING(ring, 0x00000000);
533 OUT_RING(ring, 0x00000000);
534 OUT_RING(ring, 0x00000000);
535
536 if (dubwc_enabled) {
537 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_FLAGS_LO, 6);
538 fd6_emit_flag_reference(ring, dst, info->dst.level, dbox->z + i);
539 OUT_RING(ring, 0x00000000);
540 OUT_RING(ring, 0x00000000);
541 OUT_RING(ring, 0x00000000);
542 }
543
544 /*
545 * Blit command:
546 */
547 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
548 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(sx1));
549 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(sx2));
550 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(sy1));
551 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(sy2));
552
553 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
554 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dx1) | A6XX_GRAS_2D_DST_TL_Y(dy1));
555 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dx2) | A6XX_GRAS_2D_DST_BR_Y(dy2));
556
557 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
558 OUT_RING(ring, 0x3f);
559 OUT_WFI5(ring);
560
561 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
562 OUT_RING(ring, 0);
563
564 if (dfmt == FMT6_10_10_10_2_UNORM_DEST)
565 sfmt = FMT6_16_16_16_16_FLOAT;
566
567 /* This register is probably badly named... it seems that it's
568 * controlling the internal/accumulator format or something like
569 * that. It's certainly not tied to only the src format.
570 */
571 OUT_PKT4(ring, REG_A6XX_SP_2D_SRC_FORMAT, 1);
572 OUT_RING(ring, A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT(sfmt) |
573 COND(util_format_is_pure_sint(info->src.format),
574 A6XX_SP_2D_SRC_FORMAT_SINT) |
575 COND(util_format_is_pure_uint(info->src.format),
576 A6XX_SP_2D_SRC_FORMAT_UINT) |
577 COND(util_format_is_snorm(info->src.format),
578 A6XX_SP_2D_SRC_FORMAT_SINT |
579 A6XX_SP_2D_SRC_FORMAT_NORM) |
580 COND(util_format_is_unorm(info->src.format),
581 // TODO sometimes blob uses UINT+NORM but dEQP seems unhappy about that
582 // A6XX_SP_2D_SRC_FORMAT_UINT |
583 A6XX_SP_2D_SRC_FORMAT_NORM) |
584 COND(util_format_is_srgb(info->dst.format), A6XX_SP_2D_SRC_FORMAT_SRGB) |
585 A6XX_SP_2D_SRC_FORMAT_MASK(0xf));
586
587 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
588 OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
589
590 OUT_PKT7(ring, CP_BLIT, 1);
591 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
592
593 OUT_WFI5(ring);
594
595 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
596 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
597 }
598 }
599
600 void
601 fd6_clear_surface(struct fd_context *ctx,
602 struct fd_ringbuffer *ring, struct pipe_surface *psurf,
603 uint32_t width, uint32_t height, union pipe_color_union *color)
604 {
605 struct pipe_blit_info info = {};
606
607 info.dst.resource = psurf->texture;
608 info.dst.level = psurf->u.tex.level;
609 info.dst.box.x = 0;
610 info.dst.box.y = 0;
611 info.dst.box.z = psurf->u.tex.first_layer;
612 info.dst.box.width = width;
613 info.dst.box.height = height;
614 info.dst.box.depth = psurf->u.tex.last_layer + 1 - psurf->u.tex.first_layer;
615 info.dst.format = psurf->format;
616 info.src = info.dst;
617 info.mask = util_format_get_mask(psurf->format);
618 info.filter = PIPE_TEX_FILTER_NEAREST;
619 info.scissor_enable = 0;
620
621 emit_blit_or_clear_texture(ctx, ring, &info, color);
622 }
623
624 static bool
625 handle_rgba_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
626 {
627 struct fd_batch *batch;
628
629 debug_assert(!(info->mask & PIPE_MASK_ZS));
630
631 if (!can_do_blit(info))
632 return false;
633
634 fd_fence_ref(&ctx->last_fence, NULL);
635
636 batch = fd_bc_alloc_batch(&ctx->screen->batch_cache, ctx, true);
637
638 fd6_emit_restore(batch, batch->draw);
639 fd6_emit_lrz_flush(batch->draw);
640
641 fd_screen_lock(ctx->screen);
642
643 fd_batch_resource_used(batch, fd_resource(info->src.resource), false);
644 fd_batch_resource_used(batch, fd_resource(info->dst.resource), true);
645
646 fd_screen_unlock(ctx->screen);
647
648 fd_batch_set_stage(batch, FD_STAGE_BLIT);
649
650 fd_log_stream(batch, stream, util_dump_blit_info(stream, info));
651
652 emit_setup(batch);
653
654 if ((info->src.resource->target == PIPE_BUFFER) &&
655 (info->dst.resource->target == PIPE_BUFFER)) {
656 assert(fd_resource(info->src.resource)->layout.tile_mode == TILE6_LINEAR);
657 assert(fd_resource(info->dst.resource)->layout.tile_mode == TILE6_LINEAR);
658 fd_log(batch, "START BLIT (BUFFER)");
659 emit_blit_buffer(ctx, batch->draw, info);
660 fd_log(batch, "END BLIT (BUFFER)");
661 } else {
662 /* I don't *think* we need to handle blits between buffer <-> !buffer */
663 debug_assert(info->src.resource->target != PIPE_BUFFER);
664 debug_assert(info->dst.resource->target != PIPE_BUFFER);
665 fd_log(batch, "START BLIT (TEXTURE)");
666 emit_blit_or_clear_texture(ctx, batch->draw, info, NULL);
667 fd_log(batch, "END BLIT (TEXTURE)");
668 }
669
670 fd6_event_write(batch, batch->draw, PC_CCU_FLUSH_COLOR_TS, true);
671 fd6_event_write(batch, batch->draw, PC_CCU_FLUSH_DEPTH_TS, true);
672 fd6_event_write(batch, batch->draw, CACHE_FLUSH_TS, true);
673 fd6_cache_inv(batch, batch->draw);
674
675 fd_resource(info->dst.resource)->valid = true;
676 batch->needs_flush = true;
677
678 fd_batch_flush(batch);
679 fd_batch_reference(&batch, NULL);
680
681 return true;
682 }
683
684 /**
685 * Re-written z/s blits can still fail for various reasons (for example MSAA).
686 * But we want to do the fallback blit with the re-written pipe_blit_info,
687 * in particular as u_blitter cannot blit stencil. So handle the fallback
688 * ourself and never "fail".
689 */
690 static bool
691 do_rewritten_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
692 {
693 bool success = handle_rgba_blit(ctx, info);
694 if (!success)
695 success = fd_blitter_blit(ctx, info);
696 debug_assert(success); /* fallback should never fail! */
697 return success;
698 }
699
700 /**
701 * Handle depth/stencil blits either via u_blitter and/or re-writing the
702 * blit into an equivilant format that we can handle
703 */
704 static bool
705 handle_zs_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
706 {
707 struct pipe_blit_info blit = *info;
708
709 if (DEBUG_BLIT) {
710 fprintf(stderr, "---- handle_zs_blit: ");
711 util_dump_blit_info(stderr, info);
712 fprintf(stderr, "\ndst resource: ");
713 util_dump_resource(stderr, info->dst.resource);
714 fprintf(stderr, "\nsrc resource: ");
715 util_dump_resource(stderr, info->src.resource);
716 fprintf(stderr, "\n");
717 }
718
719 switch (info->dst.format) {
720 case PIPE_FORMAT_S8_UINT:
721 debug_assert(info->mask == PIPE_MASK_S);
722 blit.mask = PIPE_MASK_R;
723 blit.src.format = PIPE_FORMAT_R8_UINT;
724 blit.dst.format = PIPE_FORMAT_R8_UINT;
725 return do_rewritten_blit(ctx, &blit);
726
727 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
728 if (info->mask & PIPE_MASK_Z) {
729 blit.mask = PIPE_MASK_R;
730 blit.src.format = PIPE_FORMAT_R32_FLOAT;
731 blit.dst.format = PIPE_FORMAT_R32_FLOAT;
732 do_rewritten_blit(ctx, &blit);
733 }
734
735 if (info->mask & PIPE_MASK_S) {
736 blit.mask = PIPE_MASK_R;
737 blit.src.format = PIPE_FORMAT_R8_UINT;
738 blit.dst.format = PIPE_FORMAT_R8_UINT;
739 blit.src.resource = &fd_resource(info->src.resource)->stencil->base;
740 blit.dst.resource = &fd_resource(info->dst.resource)->stencil->base;
741 do_rewritten_blit(ctx, &blit);
742 }
743
744 return true;
745
746 case PIPE_FORMAT_Z16_UNORM:
747 blit.mask = PIPE_MASK_R;
748 blit.src.format = PIPE_FORMAT_R16_UNORM;
749 blit.dst.format = PIPE_FORMAT_R16_UNORM;
750 return do_rewritten_blit(ctx, &blit);
751
752 case PIPE_FORMAT_Z32_UNORM:
753 case PIPE_FORMAT_Z32_FLOAT:
754 debug_assert(info->mask == PIPE_MASK_Z);
755 blit.mask = PIPE_MASK_R;
756 blit.src.format = PIPE_FORMAT_R32_UINT;
757 blit.dst.format = PIPE_FORMAT_R32_UINT;
758 return do_rewritten_blit(ctx, &blit);
759
760 case PIPE_FORMAT_Z24X8_UNORM:
761 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
762 blit.mask = 0;
763 if (info->mask & PIPE_MASK_Z)
764 blit.mask |= PIPE_MASK_R | PIPE_MASK_G | PIPE_MASK_B;
765 if (info->mask & PIPE_MASK_S)
766 blit.mask |= PIPE_MASK_A;
767 blit.src.format = PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
768 blit.dst.format = PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
769 return fd_blitter_blit(ctx, &blit);
770
771 default:
772 return false;
773 }
774 }
775
776 static bool
777 handle_compressed_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
778 {
779 struct pipe_blit_info blit = *info;
780
781 if (DEBUG_BLIT) {
782 fprintf(stderr, "---- handle_compressed_blit: ");
783 util_dump_blit_info(stderr, info);
784 fprintf(stderr, "\ndst resource: ");
785 util_dump_resource(stderr, info->dst.resource);
786 fprintf(stderr, "\nsrc resource: ");
787 util_dump_resource(stderr, info->src.resource);
788 fprintf(stderr, "\n");
789 }
790
791 if (info->src.format != info->dst.format)
792 return fd_blitter_blit(ctx, info);
793
794 if (util_format_get_blocksize(info->src.format) == 8) {
795 blit.src.format = blit.dst.format = PIPE_FORMAT_R16G16B16A16_UINT;
796 } else {
797 debug_assert(util_format_get_blocksize(info->src.format) == 16);
798 blit.src.format = blit.dst.format = PIPE_FORMAT_R32G32B32A32_UINT;
799 }
800
801 int bw = util_format_get_blockwidth(info->src.format);
802 int bh = util_format_get_blockheight(info->src.format);
803
804 blit.src.box.x /= bw;
805 blit.src.box.y /= bh;
806 blit.src.box.width /= bw;
807 blit.src.box.height /= bh;
808
809 blit.dst.box.x /= bw;
810 blit.dst.box.y /= bh;
811 blit.dst.box.width /= bw;
812 blit.dst.box.height /= bh;
813
814 return do_rewritten_blit(ctx, &blit);
815 }
816
817 static bool
818 fd6_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
819 {
820 if (info->mask & PIPE_MASK_ZS)
821 return handle_zs_blit(ctx, info);
822 if (util_format_is_compressed(info->src.format) ||
823 util_format_is_compressed(info->dst.format))
824 return handle_compressed_blit(ctx, info);
825
826 return handle_rgba_blit(ctx, info);
827 }
828
829 void
830 fd6_blitter_init(struct pipe_context *pctx)
831 {
832 if (fd_mesa_debug & FD_DBG_NOBLIT)
833 return;
834
835 fd_context(pctx)->blit = fd6_blit;
836 }
837
838 unsigned
839 fd6_tile_mode(const struct pipe_resource *tmpl)
840 {
841 /* if the mipmap level 0 is still too small to be tiled, then don't
842 * bother pretending:
843 */
844 if (fd_resource_level_linear(tmpl, 0))
845 return TILE6_LINEAR;
846
847 /* basically just has to be a format we can blit, so uploads/downloads
848 * via linear staging buffer works:
849 */
850 if (ok_format(tmpl->format))
851 return TILE6_3;
852
853 return TILE6_LINEAR;
854 }