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freedreno/a6xx: Add ARB_depth_clamp and separate clamp support.
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_blitter.c
1 /*
2 * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "util/u_dump.h"
29 #include "util/half_float.h"
30
31 #include "freedreno_blitter.h"
32 #include "freedreno_fence.h"
33 #include "freedreno_log.h"
34 #include "freedreno_resource.h"
35
36 #include "fd6_blitter.h"
37 #include "fd6_format.h"
38 #include "fd6_emit.h"
39 #include "fd6_resource.h"
40
41 static inline enum a6xx_2d_ifmt
42 fd6_ifmt(enum a6xx_format fmt)
43 {
44 switch (fmt) {
45 case FMT6_A8_UNORM:
46 case FMT6_8_UNORM:
47 case FMT6_8_SNORM:
48 case FMT6_8_8_UNORM:
49 case FMT6_8_8_SNORM:
50 case FMT6_8_8_8_8_UNORM:
51 case FMT6_8_8_8_X8_UNORM:
52 case FMT6_8_8_8_8_SNORM:
53 case FMT6_4_4_4_4_UNORM:
54 case FMT6_5_5_5_1_UNORM:
55 case FMT6_5_6_5_UNORM:
56 return R2D_UNORM8;
57
58 case FMT6_32_UINT:
59 case FMT6_32_SINT:
60 case FMT6_32_32_UINT:
61 case FMT6_32_32_SINT:
62 case FMT6_32_32_32_32_UINT:
63 case FMT6_32_32_32_32_SINT:
64 return R2D_INT32;
65
66 case FMT6_16_UINT:
67 case FMT6_16_SINT:
68 case FMT6_16_16_UINT:
69 case FMT6_16_16_SINT:
70 case FMT6_16_16_16_16_UINT:
71 case FMT6_16_16_16_16_SINT:
72 case FMT6_10_10_10_2_UINT:
73 return R2D_INT16;
74
75 case FMT6_8_UINT:
76 case FMT6_8_SINT:
77 case FMT6_8_8_UINT:
78 case FMT6_8_8_SINT:
79 case FMT6_8_8_8_8_UINT:
80 case FMT6_8_8_8_8_SINT:
81 case FMT6_Z24_UNORM_S8_UINT:
82 case FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8:
83 return R2D_INT8;
84
85 case FMT6_16_UNORM:
86 case FMT6_16_SNORM:
87 case FMT6_16_16_UNORM:
88 case FMT6_16_16_SNORM:
89 case FMT6_16_16_16_16_UNORM:
90 case FMT6_16_16_16_16_SNORM:
91 case FMT6_32_FLOAT:
92 case FMT6_32_32_FLOAT:
93 case FMT6_32_32_32_32_FLOAT:
94 return R2D_FLOAT32;
95
96 case FMT6_16_FLOAT:
97 case FMT6_16_16_FLOAT:
98 case FMT6_16_16_16_16_FLOAT:
99 case FMT6_11_11_10_FLOAT:
100 case FMT6_10_10_10_2_UNORM_DEST:
101 return R2D_FLOAT16;
102
103 default:
104 unreachable("bad format");
105 return 0;
106 }
107 }
108
109 /* Make sure none of the requested dimensions extend beyond the size of the
110 * resource. Not entirely sure why this happens, but sometimes it does, and
111 * w/ 2d blt doesn't have wrap modes like a sampler, so force those cases
112 * back to u_blitter
113 */
114 static bool
115 ok_dims(const struct pipe_resource *r, const struct pipe_box *b, int lvl)
116 {
117 int last_layer =
118 r->target == PIPE_TEXTURE_3D ? u_minify(r->depth0, lvl)
119 : r->array_size;
120
121 return (b->x >= 0) && (b->x + b->width <= u_minify(r->width0, lvl)) &&
122 (b->y >= 0) && (b->y + b->height <= u_minify(r->height0, lvl)) &&
123 (b->z >= 0) && (b->z + b->depth <= last_layer);
124 }
125
126 static bool
127 ok_format(enum pipe_format pfmt)
128 {
129 enum a6xx_format fmt = fd6_pipe2color(pfmt);
130
131 if (util_format_is_compressed(pfmt))
132 return true;
133
134 switch (pfmt) {
135 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
136 case PIPE_FORMAT_Z24X8_UNORM:
137 case PIPE_FORMAT_Z16_UNORM:
138 case PIPE_FORMAT_Z32_UNORM:
139 case PIPE_FORMAT_Z32_FLOAT:
140 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
141 case PIPE_FORMAT_S8_UINT:
142 return true;
143 default:
144 break;
145 }
146
147 if (fmt == FMT6_NONE)
148 return false;
149
150 return true;
151 }
152
153 #define DEBUG_BLIT 0
154 #define DEBUG_BLIT_FALLBACK 0
155
156 #define fail_if(cond) \
157 do { \
158 if (cond) { \
159 if (DEBUG_BLIT_FALLBACK) { \
160 fprintf(stderr, "falling back: %s for blit:\n", #cond); \
161 dump_blit_info(info); \
162 } \
163 return false; \
164 } \
165 } while (0)
166
167 static bool
168 is_ubwc(struct pipe_resource *prsc, unsigned level)
169 {
170 return fd_resource_ubwc_enabled(fd_resource(prsc), level);
171 }
172
173 static void
174 dump_blit_info(const struct pipe_blit_info *info)
175 {
176 util_dump_blit_info(stderr, info);
177 fprintf(stderr, "\ndst resource: ");
178 util_dump_resource(stderr, info->dst.resource);
179 if (is_ubwc(info->dst.resource, info->dst.level))
180 fprintf(stderr, " (ubwc)");
181 fprintf(stderr, "\nsrc resource: ");
182 util_dump_resource(stderr, info->src.resource);
183 if (is_ubwc(info->src.resource, info->src.level))
184 fprintf(stderr, " (ubwc)");
185 fprintf(stderr, "\n");
186 }
187
188 static bool
189 can_do_blit(const struct pipe_blit_info *info)
190 {
191 /* I think we can do scaling, but not in z dimension since that would
192 * require blending..
193 */
194 fail_if(info->dst.box.depth != info->src.box.depth);
195
196 /* Fail if unsupported format: */
197 fail_if(!ok_format(info->src.format));
198 fail_if(!ok_format(info->dst.format));
199
200 debug_assert(!util_format_is_compressed(info->src.format));
201 debug_assert(!util_format_is_compressed(info->dst.format));
202
203 fail_if(!ok_dims(info->src.resource, &info->src.box, info->src.level));
204
205 fail_if(!ok_dims(info->dst.resource, &info->dst.box, info->dst.level));
206
207 debug_assert(info->dst.box.width >= 0);
208 debug_assert(info->dst.box.height >= 0);
209 debug_assert(info->dst.box.depth >= 0);
210
211 fail_if(info->dst.resource->nr_samples > 1);
212
213 fail_if(info->window_rectangle_include);
214
215 const struct util_format_description *src_desc =
216 util_format_description(info->src.format);
217 const struct util_format_description *dst_desc =
218 util_format_description(info->dst.format);
219 const int common_channels = MIN2(src_desc->nr_channels, dst_desc->nr_channels);
220
221 if (info->mask & PIPE_MASK_RGBA) {
222 for (int i = 0; i < common_channels; i++) {
223 fail_if(memcmp(&src_desc->channel[i],
224 &dst_desc->channel[i],
225 sizeof(src_desc->channel[0])));
226 }
227 }
228
229 fail_if(info->alpha_blend);
230
231 return true;
232 }
233
234 static void
235 emit_setup(struct fd_batch *batch)
236 {
237 struct fd_ringbuffer *ring = batch->draw;
238
239 fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
240 fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
241 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
242 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_DEPTH, false);
243
244 /* normal BLIT_OP_SCALE operation needs bypass RB_CCU_CNTL */
245 OUT_WFI5(ring);
246 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
247 OUT_RING(ring, fd6_context(batch->ctx)->magic.RB_CCU_CNTL_bypass);
248 }
249
250 static void
251 emit_blit_setup(struct fd_ringbuffer *ring,
252 enum pipe_format pfmt, bool scissor_enable, union pipe_color_union *color)
253 {
254 enum a6xx_format fmt = fd6_pipe2color(pfmt);
255 bool is_srgb = util_format_is_srgb(pfmt);
256 enum a6xx_2d_ifmt ifmt = fd6_ifmt(fmt);
257
258 OUT_PKT7(ring, CP_SET_MARKER, 1);
259 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
260
261 if (is_srgb) {
262 assert(ifmt == R2D_UNORM8);
263 ifmt = R2D_UNORM8_SRGB;
264 }
265
266 uint32_t blit_cntl = A6XX_RB_2D_BLIT_CNTL_MASK(0xf) |
267 A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(fmt) |
268 A6XX_RB_2D_BLIT_CNTL_IFMT(ifmt) |
269 COND(color, A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR) |
270 COND(scissor_enable, A6XX_RB_2D_BLIT_CNTL_SCISSOR);
271
272 OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
273 OUT_RING(ring, blit_cntl);
274
275 OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
276 OUT_RING(ring, blit_cntl);
277
278 if (fmt == FMT6_10_10_10_2_UNORM_DEST)
279 fmt = FMT6_16_16_16_16_FLOAT;
280
281 /* This register is probably badly named... it seems that it's
282 * controlling the internal/accumulator format or something like
283 * that. It's certainly not tied to only the src format.
284 */
285 OUT_PKT4(ring, REG_A6XX_SP_2D_DST_FORMAT, 1);
286 OUT_RING(ring, A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(fmt) |
287 COND(util_format_is_pure_sint(pfmt),
288 A6XX_SP_2D_DST_FORMAT_SINT) |
289 COND(util_format_is_pure_uint(pfmt),
290 A6XX_SP_2D_DST_FORMAT_UINT) |
291 COND(util_format_is_snorm(pfmt),
292 A6XX_SP_2D_DST_FORMAT_SINT |
293 A6XX_SP_2D_DST_FORMAT_NORM) |
294 COND(util_format_is_unorm(pfmt),
295 // TODO sometimes blob uses UINT+NORM but dEQP seems unhappy about that
296 // A6XX_SP_2D_DST_FORMAT_UINT |
297 A6XX_SP_2D_DST_FORMAT_NORM) |
298 COND(is_srgb, A6XX_SP_2D_DST_FORMAT_SRGB) |
299 A6XX_SP_2D_DST_FORMAT_MASK(0xf));
300
301 OUT_PKT4(ring, REG_A6XX_RB_2D_UNKNOWN_8C01, 1);
302 OUT_RING(ring, 0);
303 }
304
305 /* buffers need to be handled specially since x/width can exceed the bounds
306 * supported by hw.. if necessary decompose into (potentially) two 2D blits
307 */
308 static void
309 emit_blit_buffer(struct fd_context *ctx, struct fd_ringbuffer *ring,
310 const struct pipe_blit_info *info)
311 {
312 const struct pipe_box *sbox = &info->src.box;
313 const struct pipe_box *dbox = &info->dst.box;
314 struct fd_resource *src, *dst;
315 unsigned sshift, dshift;
316
317 if (DEBUG_BLIT) {
318 fprintf(stderr, "buffer blit: ");
319 dump_blit_info(info);
320 }
321
322 src = fd_resource(info->src.resource);
323 dst = fd_resource(info->dst.resource);
324
325 debug_assert(src->layout.cpp == 1);
326 debug_assert(dst->layout.cpp == 1);
327 debug_assert(info->src.resource->format == info->dst.resource->format);
328 debug_assert((sbox->y == 0) && (sbox->height == 1));
329 debug_assert((dbox->y == 0) && (dbox->height == 1));
330 debug_assert((sbox->z == 0) && (sbox->depth == 1));
331 debug_assert((dbox->z == 0) && (dbox->depth == 1));
332 debug_assert(sbox->width == dbox->width);
333 debug_assert(info->src.level == 0);
334 debug_assert(info->dst.level == 0);
335
336 /*
337 * Buffers can have dimensions bigger than max width, remap into
338 * multiple 1d blits to fit within max dimension
339 *
340 * Note that blob uses .ARRAY_PITCH=128 for blitting buffers, which
341 * seems to prevent overfetch related faults. Not quite sure what
342 * the deal is there.
343 *
344 * Low 6 bits of SRC/DST addresses need to be zero (ie. address
345 * aligned to 64) so we need to shift src/dst x1/x2 to make up the
346 * difference. On top of already splitting up the blit so width
347 * isn't > 16k.
348 *
349 * We perhaps could do a bit better, if src and dst are aligned but
350 * in the worst case this means we have to split the copy up into
351 * 16k (0x4000) minus 64 (0x40).
352 */
353
354 sshift = sbox->x & 0x3f;
355 dshift = dbox->x & 0x3f;
356
357 emit_blit_setup(ring, PIPE_FORMAT_R8_UNORM, false, NULL);
358
359 for (unsigned off = 0; off < sbox->width; off += (0x4000 - 0x40)) {
360 unsigned soff, doff, w, p;
361
362 soff = (sbox->x + off) & ~0x3f;
363 doff = (dbox->x + off) & ~0x3f;
364
365 w = MIN2(sbox->width - off, (0x4000 - 0x40));
366 p = align(w, 64);
367
368 debug_assert((soff + w) <= fd_bo_size(src->bo));
369 debug_assert((doff + w) <= fd_bo_size(dst->bo));
370
371 /*
372 * Emit source:
373 */
374 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 10);
375 OUT_RING(ring, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(FMT6_8_UNORM) |
376 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(TILE6_LINEAR) |
377 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(WZYX) |
378 0x500000);
379 OUT_RING(ring, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(sshift + w) |
380 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(1)); /* SP_PS_2D_SRC_SIZE */
381 OUT_RELOC(ring, src->bo, soff, 0, 0); /* SP_PS_2D_SRC_LO/HI */
382 OUT_RING(ring, A6XX_SP_PS_2D_SRC_PITCH_PITCH(p));
383
384 OUT_RING(ring, 0x00000000);
385 OUT_RING(ring, 0x00000000);
386 OUT_RING(ring, 0x00000000);
387 OUT_RING(ring, 0x00000000);
388 OUT_RING(ring, 0x00000000);
389
390 /*
391 * Emit destination:
392 */
393 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
394 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(FMT6_8_UNORM) |
395 A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
396 A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
397 OUT_RELOC(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
398 OUT_RING(ring, A6XX_RB_2D_DST_PITCH(p));
399 OUT_RING(ring, 0x00000000);
400 OUT_RING(ring, 0x00000000);
401 OUT_RING(ring, 0x00000000);
402 OUT_RING(ring, 0x00000000);
403 OUT_RING(ring, 0x00000000);
404
405 /*
406 * Blit command:
407 */
408 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
409 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X(sshift));
410 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X(sshift + w - 1));
411 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y(0));
412 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y(0));
413
414 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
415 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dshift) | A6XX_GRAS_2D_DST_TL_Y(0));
416 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dshift + w - 1) | A6XX_GRAS_2D_DST_BR_Y(0));
417
418 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
419 OUT_RING(ring, 0x3f);
420 OUT_WFI5(ring);
421
422 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
423 OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
424
425 OUT_PKT7(ring, CP_BLIT, 1);
426 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
427
428 OUT_WFI5(ring);
429
430 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
431 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
432 }
433 }
434
435 static void
436 fd6_clear_ubwc(struct fd_batch *batch, struct fd_resource *rsc)
437 {
438 struct fd_ringbuffer *ring = fd_batch_get_prologue(batch);
439 union pipe_color_union color = {};
440
441 emit_blit_setup(ring, PIPE_FORMAT_R8_UNORM, false, &color);
442
443 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 13);
444 OUT_RING(ring, 0x00000000);
445 OUT_RING(ring, 0x00000000);
446 OUT_RING(ring, 0x00000000);
447 OUT_RING(ring, 0x00000000);
448 OUT_RING(ring, 0x00000000);
449 OUT_RING(ring, 0x00000000);
450 OUT_RING(ring, 0x00000000);
451 OUT_RING(ring, 0x00000000);
452 OUT_RING(ring, 0x00000000);
453 OUT_RING(ring, 0x00000000);
454 OUT_RING(ring, 0x00000000);
455 OUT_RING(ring, 0x00000000);
456 OUT_RING(ring, 0x00000000);
457
458 OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
459 OUT_RING(ring, 0x00000000);
460 OUT_RING(ring, 0x00000000);
461 OUT_RING(ring, 0x00000000);
462 OUT_RING(ring, 0x00000000);
463
464 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
465 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X(0));
466 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X(0));
467 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y(0));
468 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y(0));
469
470 unsigned size = rsc->layout.slices[0].offset;
471 unsigned offset = 0;
472
473 /* We could be more clever here and realize that we could use a
474 * larger width if the size is aligned to something more than a
475 * single page.. or even use a format larger than r8 in those
476 * cases. But for normal sized textures and even up to 16k x 16k
477 * at <= 4byte/pixel, we'll only go thru the loop once
478 */
479 const unsigned w = 0x1000;
480
481 /* ubwc size should always be page aligned: */
482 assert((size % w) == 0);
483
484 while (size > 0) {
485 const unsigned h = MIN2(0x4000, size / w);
486 /* width is already aligned to a suitable pitch: */
487 const unsigned p = w;
488
489 /*
490 * Emit destination:
491 */
492 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
493 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(FMT6_8_UNORM) |
494 A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
495 A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
496 OUT_RELOC(ring, rsc->bo, offset, 0, 0); /* RB_2D_DST_LO/HI */
497 OUT_RING(ring, A6XX_RB_2D_DST_PITCH(p));
498 OUT_RING(ring, 0x00000000);
499 OUT_RING(ring, 0x00000000);
500 OUT_RING(ring, 0x00000000);
501 OUT_RING(ring, 0x00000000);
502 OUT_RING(ring, 0x00000000);
503
504 /*
505 * Blit command:
506 */
507
508 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
509 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) | A6XX_GRAS_2D_DST_TL_Y(0));
510 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(w - 1) | A6XX_GRAS_2D_DST_BR_Y(h - 1));
511
512 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
513 OUT_RING(ring, 0x3f);
514 OUT_WFI5(ring);
515
516 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
517 OUT_RING(ring, fd6_context(batch->ctx)->magic.RB_UNKNOWN_8E04_blit);
518
519 OUT_PKT7(ring, CP_BLIT, 1);
520 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
521
522 OUT_WFI5(ring);
523
524 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
525 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
526
527 offset += w * h;
528 size -= w * h;
529 }
530
531 fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
532 fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
533 fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
534 fd6_cache_inv(batch, ring);
535 }
536
537 static void
538 emit_blit_dst(struct fd_ringbuffer *ring, struct pipe_resource *prsc, enum pipe_format pfmt, unsigned level, unsigned layer)
539 {
540 struct fd_resource *dst = fd_resource(prsc);
541 enum a6xx_format fmt = fd6_pipe2color(pfmt);
542 enum a6xx_tile_mode tile = fd_resource_tile_mode(prsc, level);
543 enum a3xx_color_swap swap = fd6_resource_swap(dst, pfmt);
544 uint32_t pitch = fd_resource_pitch(dst, level);
545 bool ubwc_enabled = fd_resource_ubwc_enabled(dst, level);
546 unsigned off = fd_resource_offset(dst, level, layer);
547
548 if (fmt == FMT6_Z24_UNORM_S8_UINT)
549 fmt = FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
550
551 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
552 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(fmt) |
553 A6XX_RB_2D_DST_INFO_TILE_MODE(tile) |
554 A6XX_RB_2D_DST_INFO_COLOR_SWAP(swap) |
555 COND(util_format_is_srgb(pfmt), A6XX_RB_2D_DST_INFO_SRGB) |
556 COND(ubwc_enabled, A6XX_RB_2D_DST_INFO_FLAGS));
557 OUT_RELOC(ring, dst->bo, off, 0, 0); /* RB_2D_DST_LO/HI */
558 OUT_RING(ring, A6XX_RB_2D_DST_PITCH(pitch));
559 OUT_RING(ring, 0x00000000);
560 OUT_RING(ring, 0x00000000);
561 OUT_RING(ring, 0x00000000);
562 OUT_RING(ring, 0x00000000);
563 OUT_RING(ring, 0x00000000);
564
565 if (ubwc_enabled) {
566 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_FLAGS_LO, 6);
567 fd6_emit_flag_reference(ring, dst, level, layer);
568 OUT_RING(ring, 0x00000000);
569 OUT_RING(ring, 0x00000000);
570 OUT_RING(ring, 0x00000000);
571 }
572 }
573
574 static void
575 emit_blit_src(struct fd_ringbuffer *ring, const struct pipe_blit_info *info, unsigned layer, unsigned nr_samples)
576 {
577 struct fd_resource *src = fd_resource(info->src.resource);
578 enum a6xx_format sfmt = fd6_pipe2color(info->src.format);
579 enum a6xx_tile_mode stile = fd_resource_tile_mode(info->src.resource, info->src.level);
580 enum a3xx_color_swap sswap = fd6_resource_swap(src, info->src.format);
581 uint32_t pitch = fd_resource_pitch(src, info->src.level);
582 bool subwc_enabled = fd_resource_ubwc_enabled(src, info->src.level);
583 unsigned soff = fd_resource_offset(src, info->src.level, layer);
584 uint32_t width = u_minify(src->base.width0, info->src.level) * nr_samples;
585 uint32_t height = u_minify(src->base.height0, info->src.level);
586 uint32_t filter = 0;
587
588 if (info->filter == PIPE_TEX_FILTER_LINEAR)
589 filter = A6XX_SP_PS_2D_SRC_INFO_FILTER;
590
591 enum a3xx_msaa_samples samples = fd_msaa_samples(src->base.nr_samples);
592
593 if (sfmt == FMT6_10_10_10_2_UNORM_DEST)
594 sfmt = FMT6_10_10_10_2_UNORM;
595
596 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 10);
597 OUT_RING(ring, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(sfmt) |
598 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(stile) |
599 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(sswap) |
600 A6XX_SP_PS_2D_SRC_INFO_SAMPLES(samples) |
601 COND(samples > MSAA_ONE && (info->mask & PIPE_MASK_RGBA),
602 A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE) |
603 COND(subwc_enabled, A6XX_SP_PS_2D_SRC_INFO_FLAGS) |
604 COND(util_format_is_srgb(info->src.format), A6XX_SP_PS_2D_SRC_INFO_SRGB) |
605 0x500000 | filter);
606 OUT_RING(ring, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(width) |
607 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(height)); /* SP_PS_2D_SRC_SIZE */
608 OUT_RELOC(ring, src->bo, soff, 0, 0); /* SP_PS_2D_SRC_LO/HI */
609 OUT_RING(ring, A6XX_SP_PS_2D_SRC_PITCH_PITCH(pitch));
610
611 OUT_RING(ring, 0x00000000);
612 OUT_RING(ring, 0x00000000);
613 OUT_RING(ring, 0x00000000);
614 OUT_RING(ring, 0x00000000);
615 OUT_RING(ring, 0x00000000);
616
617 if (subwc_enabled) {
618 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_FLAGS_LO, 6);
619 fd6_emit_flag_reference(ring, src, info->src.level, layer);
620 OUT_RING(ring, 0x00000000);
621 OUT_RING(ring, 0x00000000);
622 OUT_RING(ring, 0x00000000);
623 }
624 }
625
626 static void
627 emit_blit_texture(struct fd_context *ctx,
628 struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
629 {
630 const struct pipe_box *sbox = &info->src.box;
631 const struct pipe_box *dbox = &info->dst.box;
632 struct fd_resource *dst;
633 int sx1, sy1, sx2, sy2;
634 int dx1, dy1, dx2, dy2;
635
636 if (DEBUG_BLIT) {
637 fprintf(stderr, "texture blit: ");
638 dump_blit_info(info);
639 }
640
641 dst = fd_resource(info->dst.resource);
642
643 uint32_t nr_samples = fd_resource_nr_samples(&dst->base);
644
645 sx1 = sbox->x * nr_samples;
646 sy1 = sbox->y;
647 sx2 = (sbox->x + sbox->width) * nr_samples - 1;
648 sy2 = sbox->y + sbox->height - 1;
649
650 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
651 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X(sx1));
652 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X(sx2));
653 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y(sy1));
654 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y(sy2));
655
656 dx1 = dbox->x * nr_samples;
657 dy1 = dbox->y;
658 dx2 = (dbox->x + dbox->width) * nr_samples - 1;
659 dy2 = dbox->y + dbox->height - 1;
660
661 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
662 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dx1) | A6XX_GRAS_2D_DST_TL_Y(dy1));
663 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dx2) | A6XX_GRAS_2D_DST_BR_Y(dy2));
664
665 if (info->scissor_enable) {
666 OUT_PKT4(ring, REG_A6XX_GRAS_2D_RESOLVE_CNTL_1, 2);
667 OUT_RING(ring, A6XX_GRAS_2D_RESOLVE_CNTL_1_X(info->scissor.minx) |
668 A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(info->scissor.miny));
669 OUT_RING(ring, A6XX_GRAS_2D_RESOLVE_CNTL_1_X(info->scissor.maxx - 1) |
670 A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(info->scissor.maxy - 1));
671 }
672
673 emit_blit_setup(ring, info->dst.format, info->scissor_enable, NULL);
674
675 for (unsigned i = 0; i < info->dst.box.depth; i++) {
676
677 emit_blit_src(ring, info, sbox->z + i, nr_samples);
678 emit_blit_dst(ring, info->dst.resource, info->dst.format, info->dst.level, dbox->z + i);
679
680 /*
681 * Blit command:
682 */
683 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
684 OUT_RING(ring, 0x3f);
685 OUT_WFI5(ring);
686
687 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
688 OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
689
690 OUT_PKT7(ring, CP_BLIT, 1);
691 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
692
693 OUT_WFI5(ring);
694
695 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
696 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
697 }
698 }
699
700 static void
701 emit_clear_color(struct fd_ringbuffer *ring,
702 enum pipe_format pfmt, union pipe_color_union *color)
703 {
704 switch (pfmt) {
705 case PIPE_FORMAT_Z24X8_UNORM:
706 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
707 case PIPE_FORMAT_X24S8_UINT: {
708 uint32_t depth_unorm24 = color->f[0] * ((1u << 24) - 1);
709 uint8_t stencil = color->ui[1];
710 color->ui[0] = depth_unorm24 & 0xff;
711 color->ui[1] = (depth_unorm24 >> 8) & 0xff;
712 color->ui[2] = (depth_unorm24 >> 16) & 0xff;
713 color->ui[3] = stencil;
714 break;
715 }
716 default:
717 break;
718 }
719
720 OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
721 switch (fd6_ifmt(fd6_pipe2color(pfmt))) {
722 case R2D_UNORM8:
723 case R2D_UNORM8_SRGB:
724 OUT_RING(ring, float_to_ubyte(color->f[0]));
725 OUT_RING(ring, float_to_ubyte(color->f[1]));
726 OUT_RING(ring, float_to_ubyte(color->f[2]));
727 OUT_RING(ring, float_to_ubyte(color->f[3]));
728 break;
729 case R2D_FLOAT16:
730 OUT_RING(ring, _mesa_float_to_half(color->f[0]));
731 OUT_RING(ring, _mesa_float_to_half(color->f[1]));
732 OUT_RING(ring, _mesa_float_to_half(color->f[2]));
733 OUT_RING(ring, _mesa_float_to_half(color->f[3]));
734 break;
735 case R2D_FLOAT32:
736 case R2D_INT32:
737 case R2D_INT16:
738 case R2D_INT8:
739 default:
740 OUT_RING(ring, color->ui[0]);
741 OUT_RING(ring, color->ui[1]);
742 OUT_RING(ring, color->ui[2]);
743 OUT_RING(ring, color->ui[3]);
744 break;
745 }
746 }
747
748 void
749 fd6_clear_surface(struct fd_context *ctx,
750 struct fd_ringbuffer *ring, struct pipe_surface *psurf,
751 uint32_t width, uint32_t height, union pipe_color_union *color)
752 {
753 if (DEBUG_BLIT) {
754 fprintf(stderr, "surface clear:\ndst resource: ");
755 util_dump_resource(stderr, psurf->texture);
756 fprintf(stderr, "\n");
757 }
758
759 uint32_t nr_samples = fd_resource_nr_samples(psurf->texture);
760 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
761 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) | A6XX_GRAS_2D_DST_TL_Y(0));
762 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(width * nr_samples - 1) |
763 A6XX_GRAS_2D_DST_BR_Y(height - 1));
764
765 emit_clear_color(ring, psurf->format, color);
766 emit_blit_setup(ring, psurf->format, false, color);
767
768 for (unsigned i = psurf->u.tex.first_layer; i <= psurf->u.tex.last_layer; i++) {
769 emit_blit_dst(ring, psurf->texture, psurf->format, psurf->u.tex.level, i);
770
771 /*
772 * Blit command:
773 */
774 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
775 OUT_RING(ring, 0x3f);
776 OUT_WFI5(ring);
777
778 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
779 OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
780
781 OUT_PKT7(ring, CP_BLIT, 1);
782 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
783
784 OUT_WFI5(ring);
785
786 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
787 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
788 }
789 }
790
791 static bool
792 handle_rgba_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
793 {
794 struct fd_batch *batch;
795
796 debug_assert(!(info->mask & PIPE_MASK_ZS));
797
798 if (!can_do_blit(info))
799 return false;
800
801 batch = fd_bc_alloc_batch(&ctx->screen->batch_cache, ctx, true);
802
803 fd_screen_lock(ctx->screen);
804
805 fd_batch_resource_read(batch, fd_resource(info->src.resource));
806 fd_batch_resource_write(batch, fd_resource(info->dst.resource));
807
808 fd_screen_unlock(ctx->screen);
809
810 /* Clearing last_fence must come after the batch dependency tracking
811 * (resource_read()/resource_write()), as that can trigger a flush,
812 * re-populating last_fence
813 */
814 fd_fence_ref(&ctx->last_fence, NULL);
815
816 fd_batch_set_stage(batch, FD_STAGE_BLIT);
817
818 fd_log_stream(batch, stream, util_dump_blit_info(stream, info));
819
820 emit_setup(batch);
821
822 if ((info->src.resource->target == PIPE_BUFFER) &&
823 (info->dst.resource->target == PIPE_BUFFER)) {
824 assert(fd_resource(info->src.resource)->layout.tile_mode == TILE6_LINEAR);
825 assert(fd_resource(info->dst.resource)->layout.tile_mode == TILE6_LINEAR);
826 fd_log(batch, "START BLIT (BUFFER)");
827 emit_blit_buffer(ctx, batch->draw, info);
828 fd_log(batch, "END BLIT (BUFFER)");
829 } else {
830 /* I don't *think* we need to handle blits between buffer <-> !buffer */
831 debug_assert(info->src.resource->target != PIPE_BUFFER);
832 debug_assert(info->dst.resource->target != PIPE_BUFFER);
833 fd_log(batch, "START BLIT (TEXTURE)");
834 emit_blit_texture(ctx, batch->draw, info);
835 fd_log(batch, "END BLIT (TEXTURE)");
836 }
837
838 fd6_event_write(batch, batch->draw, PC_CCU_FLUSH_COLOR_TS, true);
839 fd6_event_write(batch, batch->draw, PC_CCU_FLUSH_DEPTH_TS, true);
840 fd6_event_write(batch, batch->draw, CACHE_FLUSH_TS, true);
841 fd6_cache_inv(batch, batch->draw);
842
843 fd_resource(info->dst.resource)->valid = true;
844 batch->needs_flush = true;
845
846 fd_batch_flush(batch);
847 fd_batch_reference(&batch, NULL);
848
849 return true;
850 }
851
852 /**
853 * Re-written z/s blits can still fail for various reasons (for example MSAA).
854 * But we want to do the fallback blit with the re-written pipe_blit_info,
855 * in particular as u_blitter cannot blit stencil. So handle the fallback
856 * ourself and never "fail".
857 */
858 static bool
859 do_rewritten_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
860 {
861 bool success = handle_rgba_blit(ctx, info);
862 if (!success)
863 success = fd_blitter_blit(ctx, info);
864 debug_assert(success); /* fallback should never fail! */
865 return success;
866 }
867
868 /**
869 * Handle depth/stencil blits either via u_blitter and/or re-writing the
870 * blit into an equivilant format that we can handle
871 */
872 static bool
873 handle_zs_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
874 {
875 struct pipe_blit_info blit = *info;
876
877 if (DEBUG_BLIT) {
878 fprintf(stderr, "---- handle_zs_blit: ");
879 dump_blit_info(info);
880 }
881
882 switch (info->dst.format) {
883 case PIPE_FORMAT_S8_UINT:
884 debug_assert(info->mask == PIPE_MASK_S);
885 blit.mask = PIPE_MASK_R;
886 blit.src.format = PIPE_FORMAT_R8_UINT;
887 blit.dst.format = PIPE_FORMAT_R8_UINT;
888 return do_rewritten_blit(ctx, &blit);
889
890 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
891 if (info->mask & PIPE_MASK_Z) {
892 blit.mask = PIPE_MASK_R;
893 blit.src.format = PIPE_FORMAT_R32_FLOAT;
894 blit.dst.format = PIPE_FORMAT_R32_FLOAT;
895 do_rewritten_blit(ctx, &blit);
896 }
897
898 if (info->mask & PIPE_MASK_S) {
899 blit.mask = PIPE_MASK_R;
900 blit.src.format = PIPE_FORMAT_R8_UINT;
901 blit.dst.format = PIPE_FORMAT_R8_UINT;
902 blit.src.resource = &fd_resource(info->src.resource)->stencil->base;
903 blit.dst.resource = &fd_resource(info->dst.resource)->stencil->base;
904 do_rewritten_blit(ctx, &blit);
905 }
906
907 return true;
908
909 case PIPE_FORMAT_Z16_UNORM:
910 blit.mask = PIPE_MASK_R;
911 blit.src.format = PIPE_FORMAT_R16_UNORM;
912 blit.dst.format = PIPE_FORMAT_R16_UNORM;
913 return do_rewritten_blit(ctx, &blit);
914
915 case PIPE_FORMAT_Z32_UNORM:
916 case PIPE_FORMAT_Z32_FLOAT:
917 debug_assert(info->mask == PIPE_MASK_Z);
918 blit.mask = PIPE_MASK_R;
919 blit.src.format = PIPE_FORMAT_R32_UINT;
920 blit.dst.format = PIPE_FORMAT_R32_UINT;
921 return do_rewritten_blit(ctx, &blit);
922
923 case PIPE_FORMAT_Z24X8_UNORM:
924 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
925 blit.mask = 0;
926 if (info->mask & PIPE_MASK_Z)
927 blit.mask |= PIPE_MASK_R | PIPE_MASK_G | PIPE_MASK_B;
928 if (info->mask & PIPE_MASK_S)
929 blit.mask |= PIPE_MASK_A;
930 blit.src.format = PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
931 blit.dst.format = PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
932 return fd_blitter_blit(ctx, &blit);
933
934 default:
935 return false;
936 }
937 }
938
939 static bool
940 handle_compressed_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
941 {
942 struct pipe_blit_info blit = *info;
943
944 if (DEBUG_BLIT) {
945 fprintf(stderr, "---- handle_compressed_blit: ");
946 dump_blit_info(info);
947 }
948
949 if (info->src.format != info->dst.format)
950 return fd_blitter_blit(ctx, info);
951
952 if (util_format_get_blocksize(info->src.format) == 8) {
953 blit.src.format = blit.dst.format = PIPE_FORMAT_R16G16B16A16_UINT;
954 } else {
955 debug_assert(util_format_get_blocksize(info->src.format) == 16);
956 blit.src.format = blit.dst.format = PIPE_FORMAT_R32G32B32A32_UINT;
957 }
958
959 int bw = util_format_get_blockwidth(info->src.format);
960 int bh = util_format_get_blockheight(info->src.format);
961
962 /* NOTE: x/y *must* be aligned to block boundary (ie. in
963 * glCompressedTexSubImage2D()) but width/height may not
964 * be:
965 */
966
967 debug_assert((blit.src.box.x % bw) == 0);
968 debug_assert((blit.src.box.y % bh) == 0);
969
970 blit.src.box.x /= bw;
971 blit.src.box.y /= bh;
972 blit.src.box.width = DIV_ROUND_UP(blit.src.box.width, bw);
973 blit.src.box.height = DIV_ROUND_UP(blit.src.box.height, bh);
974
975 debug_assert((blit.dst.box.x % bw) == 0);
976 debug_assert((blit.dst.box.y % bh) == 0);
977
978 blit.dst.box.x /= bw;
979 blit.dst.box.y /= bh;
980 blit.dst.box.width = DIV_ROUND_UP(blit.dst.box.width, bw);
981 blit.dst.box.height = DIV_ROUND_UP(blit.dst.box.height, bh);
982
983 return do_rewritten_blit(ctx, &blit);
984 }
985
986 static bool
987 fd6_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
988 {
989 if (info->mask & PIPE_MASK_ZS)
990 return handle_zs_blit(ctx, info);
991 if (util_format_is_compressed(info->src.format) ||
992 util_format_is_compressed(info->dst.format))
993 return handle_compressed_blit(ctx, info);
994
995 return handle_rgba_blit(ctx, info);
996 }
997
998 void
999 fd6_blitter_init(struct pipe_context *pctx)
1000 {
1001 fd_context(pctx)->clear_ubwc = fd6_clear_ubwc;
1002
1003 if (fd_mesa_debug & FD_DBG_NOBLIT)
1004 return;
1005
1006 fd_context(pctx)->blit = fd6_blit;
1007 }
1008
1009 unsigned
1010 fd6_tile_mode(const struct pipe_resource *tmpl)
1011 {
1012 /* if the mipmap level 0 is still too small to be tiled, then don't
1013 * bother pretending:
1014 */
1015 if (fd_resource_level_linear(tmpl, 0))
1016 return TILE6_LINEAR;
1017
1018 /* basically just has to be a format we can blit, so uploads/downloads
1019 * via linear staging buffer works:
1020 */
1021 if (ok_format(tmpl->format))
1022 return TILE6_3;
1023
1024 return TILE6_LINEAR;
1025 }