freedreno/a6xx: Turn on texture tiling by default
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_blitter.c
1 /*
2 * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "util/u_dump.h"
29
30 #include "freedreno_blitter.h"
31 #include "freedreno_fence.h"
32 #include "freedreno_resource.h"
33
34 #include "fd6_blitter.h"
35 #include "fd6_format.h"
36 #include "fd6_emit.h"
37
38 /* Make sure none of the requested dimensions extend beyond the size of the
39 * resource. Not entirely sure why this happens, but sometimes it does, and
40 * w/ 2d blt doesn't have wrap modes like a sampler, so force those cases
41 * back to u_blitter
42 */
43 static bool
44 ok_dims(const struct pipe_resource *r, const struct pipe_box *b, int lvl)
45 {
46 int last_layer =
47 r->target == PIPE_TEXTURE_3D ? u_minify(r->depth0, lvl)
48 : r->array_size;
49
50 return (b->x >= 0) && (b->x + b->width <= u_minify(r->width0, lvl)) &&
51 (b->y >= 0) && (b->y + b->height <= u_minify(r->height0, lvl)) &&
52 (b->z >= 0) && (b->z + b->depth <= last_layer);
53 }
54
55 static bool
56 ok_format(enum pipe_format pfmt)
57 {
58 enum a6xx_color_fmt fmt = fd6_pipe2color(pfmt);
59 if (fmt == ~0)
60 return false;
61
62 if (fd6_ifmt(fmt) == 0)
63 return false;
64
65 return true;
66 }
67
68 #define DEBUG_BLIT_FALLBACK 0
69 #define fail_if(cond) \
70 do { \
71 if (cond) { \
72 if (DEBUG_BLIT_FALLBACK) { \
73 fprintf(stderr, "falling back: %s for blit:\n", #cond); \
74 util_dump_blit_info(stderr, info); \
75 fprintf(stderr, "\nsrc: "); \
76 util_dump_resource(stderr, info->src.resource); \
77 fprintf(stderr, "\ndst: "); \
78 util_dump_resource(stderr, info->dst.resource); \
79 fprintf(stderr, "\n"); \
80 } \
81 return false; \
82 } \
83 } while (0)
84
85 static bool
86 can_do_blit(const struct pipe_blit_info *info)
87 {
88 /* I think we can do scaling, but not in z dimension since that would
89 * require blending..
90 */
91 fail_if(info->dst.box.depth != info->src.box.depth);
92
93 /* We can blit if both or neither formats are compressed formats... */
94 fail_if(util_format_is_compressed(info->src.format) !=
95 util_format_is_compressed(info->src.format));
96
97 /* Fail if unsupported format: */
98 fail_if(!ok_format(info->src.format));
99 fail_if(!ok_format(info->dst.format));
100
101 /* ... but only if they're the same compression format. */
102 fail_if(util_format_is_compressed(info->src.format) &&
103 info->src.format != info->dst.format);
104
105 /* src box can be inverted, which we don't support.. dst box cannot: */
106 fail_if((info->src.box.width < 0) || (info->src.box.height < 0));
107
108 fail_if(!ok_dims(info->src.resource, &info->src.box, info->src.level));
109
110 fail_if(!ok_dims(info->dst.resource, &info->dst.box, info->dst.level));
111
112 debug_assert(info->dst.box.width >= 0);
113 debug_assert(info->dst.box.height >= 0);
114 debug_assert(info->dst.box.depth >= 0);
115
116 fail_if(info->dst.resource->nr_samples + info->src.resource->nr_samples > 2);
117
118 fail_if(info->window_rectangle_include);
119
120 fail_if(info->render_condition_enable);
121
122 fail_if(info->alpha_blend);
123
124 fail_if(info->mask != util_format_get_mask(info->src.format));
125
126 fail_if(info->mask != util_format_get_mask(info->dst.format));
127
128 return true;
129 }
130
131 static void
132 emit_setup(struct fd_ringbuffer *ring)
133 {
134 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
135 OUT_RING(ring, PC_CCU_INVALIDATE_COLOR);
136
137 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
138 OUT_RING(ring, LRZ_FLUSH);
139
140 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
141 OUT_RING(ring, 0x0);
142
143 OUT_WFI5(ring);
144
145 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
146 OUT_RING(ring, 0x10000000);
147 }
148
149 static uint32_t
150 blit_control(enum a6xx_color_fmt fmt)
151 {
152 unsigned blit_cntl = 0xf00000;
153 blit_cntl |= A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(fmt);
154 blit_cntl |= A6XX_RB_2D_BLIT_CNTL_IFMT(fd6_ifmt(fmt));
155 return blit_cntl;
156 }
157
158 /* buffers need to be handled specially since x/width can exceed the bounds
159 * supported by hw.. if necessary decompose into (potentially) two 2D blits
160 */
161 static void
162 emit_blit_buffer(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
163 {
164 const struct pipe_box *sbox = &info->src.box;
165 const struct pipe_box *dbox = &info->dst.box;
166 struct fd_resource *src, *dst;
167 unsigned sshift, dshift;
168
169 if (DEBUG_BLIT_FALLBACK) {
170 fprintf(stderr, "buffer blit: ");
171 util_dump_blit_info(stderr, info);
172 fprintf(stderr, "\ndst resource: ");
173 util_dump_resource(stderr, info->dst.resource);
174 fprintf(stderr, "\nsrc resource: ");
175 util_dump_resource(stderr, info->src.resource);
176 fprintf(stderr, "\n");
177 }
178
179 src = fd_resource(info->src.resource);
180 dst = fd_resource(info->dst.resource);
181
182 debug_assert(src->cpp == 1);
183 debug_assert(dst->cpp == 1);
184 debug_assert(info->src.resource->format == info->dst.resource->format);
185 debug_assert((sbox->y == 0) && (sbox->height == 1));
186 debug_assert((dbox->y == 0) && (dbox->height == 1));
187 debug_assert((sbox->z == 0) && (sbox->depth == 1));
188 debug_assert((dbox->z == 0) && (dbox->depth == 1));
189 debug_assert(sbox->width == dbox->width);
190 debug_assert(info->src.level == 0);
191 debug_assert(info->dst.level == 0);
192
193 /*
194 * Buffers can have dimensions bigger than max width, remap into
195 * multiple 1d blits to fit within max dimension
196 *
197 * Note that blob uses .ARRAY_PITCH=128 for blitting buffers, which
198 * seems to prevent overfetch related faults. Not quite sure what
199 * the deal is there.
200 *
201 * Low 6 bits of SRC/DST addresses need to be zero (ie. address
202 * aligned to 64) so we need to shift src/dst x1/x2 to make up the
203 * difference. On top of already splitting up the blit so width
204 * isn't > 16k.
205 *
206 * We perhaps could do a bit better, if src and dst are aligned but
207 * in the worst case this means we have to split the copy up into
208 * 16k (0x4000) minus 64 (0x40).
209 */
210
211 sshift = sbox->x & 0x3f;
212 dshift = dbox->x & 0x3f;
213
214 OUT_PKT7(ring, CP_SET_MARKER, 1);
215 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
216
217 uint32_t blit_cntl = blit_control(RB6_R8_UNORM) | 0x20000000;
218 OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
219 OUT_RING(ring, blit_cntl);
220
221 OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
222 OUT_RING(ring, blit_cntl);
223
224 for (unsigned off = 0; off < sbox->width; off += (0x4000 - 0x40)) {
225 unsigned soff, doff, w, p;
226
227 soff = (sbox->x + off) & ~0x3f;
228 doff = (dbox->x + off) & ~0x3f;
229
230 w = MIN2(sbox->width - off, (0x4000 - 0x40));
231 p = align(w, 64);
232
233 debug_assert((soff + w) <= fd_bo_size(src->bo));
234 debug_assert((doff + w) <= fd_bo_size(dst->bo));
235
236 /*
237 * Emit source:
238 */
239 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 13);
240 OUT_RING(ring, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(RB6_R8_UNORM) |
241 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(TILE6_LINEAR) |
242 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(WZYX) | 0x500000);
243 OUT_RING(ring, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(sshift + w) |
244 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(1)); /* SP_PS_2D_SRC_SIZE */
245 OUT_RELOC(ring, src->bo, soff, 0, 0); /* SP_PS_2D_SRC_LO/HI */
246 OUT_RING(ring, A6XX_SP_PS_2D_SRC_PITCH_PITCH(p));
247
248 OUT_RING(ring, 0x00000000);
249 OUT_RING(ring, 0x00000000);
250 OUT_RING(ring, 0x00000000);
251 OUT_RING(ring, 0x00000000);
252 OUT_RING(ring, 0x00000000);
253
254 OUT_RING(ring, 0x00000000);
255 OUT_RING(ring, 0x00000000);
256 OUT_RING(ring, 0x00000000);
257
258 /*
259 * Emit destination:
260 */
261 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
262 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(RB6_R8_UNORM) |
263 A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
264 A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
265 OUT_RELOC(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
266 OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(p));
267 OUT_RING(ring, 0x00000000);
268 OUT_RING(ring, 0x00000000);
269 OUT_RING(ring, 0x00000000);
270 OUT_RING(ring, 0x00000000);
271 OUT_RING(ring, 0x00000000);
272
273 /*
274 * Blit command:
275 */
276 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
277 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(sshift));
278 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(sshift + w - 1));
279 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(0));
280 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(0));
281
282 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
283 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dshift) | A6XX_GRAS_2D_DST_TL_Y(0));
284 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dshift + w - 1) | A6XX_GRAS_2D_DST_BR_Y(0));
285
286 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
287 OUT_RING(ring, 0x3f);
288 OUT_WFI5(ring);
289
290 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
291 OUT_RING(ring, 0);
292
293 OUT_PKT4(ring, REG_A6XX_SP_2D_SRC_FORMAT, 1);
294 OUT_RING(ring, 0xf180);
295
296 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
297 OUT_RING(ring, 0x01000000);
298
299 OUT_PKT7(ring, CP_BLIT, 1);
300 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
301
302 OUT_WFI5(ring);
303
304 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
305 OUT_RING(ring, 0);
306 }
307 }
308
309 static void
310 emit_blit_texture(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
311 {
312 const struct pipe_box *sbox = &info->src.box;
313 const struct pipe_box *dbox = &info->dst.box;
314 struct fd_resource *src, *dst;
315 struct fd_resource_slice *sslice, *dslice;
316 enum a6xx_color_fmt sfmt, dfmt;
317 enum a6xx_tile_mode stile, dtile;
318 enum a3xx_color_swap sswap, dswap;
319 unsigned spitch, dpitch;
320 unsigned sx1, sy1, sx2, sy2;
321 unsigned dx1, dy1, dx2, dy2;
322
323 if (DEBUG_BLIT_FALLBACK) {
324 fprintf(stderr, "texture blit: ");
325 util_dump_blit_info(stderr, info);
326 fprintf(stderr, "\ndst resource: ");
327 util_dump_resource(stderr, info->dst.resource);
328 fprintf(stderr, "\nsrc resource: ");
329 util_dump_resource(stderr, info->src.resource);
330 fprintf(stderr, "\n");
331 }
332
333 src = fd_resource(info->src.resource);
334 dst = fd_resource(info->dst.resource);
335
336 sslice = fd_resource_slice(src, info->src.level);
337 dslice = fd_resource_slice(dst, info->dst.level);
338
339 sfmt = fd6_pipe2color(info->src.format);
340 dfmt = fd6_pipe2color(info->dst.format);
341
342 int blocksize = util_format_get_blocksize(info->src.format);
343 int blockwidth = util_format_get_blockwidth(info->src.format);
344 int blockheight = util_format_get_blockheight(info->src.format);
345 int nelements;
346
347 stile = fd_resource_level_linear(info->src.resource, info->src.level) ?
348 TILE6_LINEAR : src->tile_mode;
349 dtile = fd_resource_level_linear(info->dst.resource, info->dst.level) ?
350 TILE6_LINEAR : dst->tile_mode;
351
352 sswap = stile ? WZYX : fd6_pipe2swap(info->src.format);
353 dswap = dtile ? WZYX : fd6_pipe2swap(info->dst.format);
354
355 if (util_format_is_compressed(info->src.format)) {
356 debug_assert(info->src.format == info->dst.format);
357 sfmt = dfmt = RB6_R8_UNORM;
358 nelements = blocksize;
359 } else {
360 debug_assert(!util_format_is_compressed(info->dst.format));
361 nelements = 1;
362 }
363
364 spitch = DIV_ROUND_UP(sslice->pitch, blockwidth) * src->cpp;
365 dpitch = DIV_ROUND_UP(dslice->pitch, blockwidth) * dst->cpp;
366
367 sx1 = sbox->x / blockwidth * nelements;
368 sy1 = sbox->y / blockheight;
369 sx2 = DIV_ROUND_UP(sbox->x + sbox->width, blockwidth) * nelements - 1;
370 sy2 = DIV_ROUND_UP(sbox->y + sbox->height, blockheight) - 1;
371
372 dx1 = dbox->x / blockwidth * nelements;
373 dy1 = dbox->y / blockheight;
374 dx2 = DIV_ROUND_UP(dbox->x + dbox->width, blockwidth) * nelements - 1;
375 dy2 = DIV_ROUND_UP(dbox->y + dbox->height, blockheight) - 1;
376
377 uint32_t width = DIV_ROUND_UP(u_minify(src->base.width0, info->src.level), blockwidth) * nelements;
378 uint32_t height = DIV_ROUND_UP(u_minify(src->base.height0, info->src.level), blockheight);
379
380 OUT_PKT7(ring, CP_SET_MARKER, 1);
381 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
382
383 uint32_t blit_cntl = blit_control(dfmt);
384
385 if (dtile != stile)
386 blit_cntl |= 0x20000000;
387
388 if (info->scissor_enable) {
389 OUT_PKT4(ring, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
390 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(info->scissor.minx) |
391 A6XX_GRAS_RESOLVE_CNTL_1_Y(info->scissor.miny));
392 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(info->scissor.maxx - 1) |
393 A6XX_GRAS_RESOLVE_CNTL_1_Y(info->scissor.maxy - 1));
394 blit_cntl |= A6XX_RB_2D_BLIT_CNTL_SCISSOR;
395 }
396
397 OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
398 OUT_RING(ring, blit_cntl);
399
400 OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
401 OUT_RING(ring, blit_cntl);
402
403 for (unsigned i = 0; i < info->dst.box.depth; i++) {
404 unsigned soff = fd_resource_offset(src, info->src.level, sbox->z + i);
405 unsigned doff = fd_resource_offset(dst, info->dst.level, dbox->z + i);
406
407 /*
408 * Emit source:
409 */
410 uint32_t filter = 0;
411 if (info->filter == PIPE_TEX_FILTER_LINEAR)
412 filter = A6XX_SP_PS_2D_SRC_INFO_FILTER;
413
414 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 13);
415 OUT_RING(ring, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(sfmt) |
416 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(stile) |
417 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(sswap) | 0x500000 | filter);
418 OUT_RING(ring, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(width) |
419 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(height)); /* SP_PS_2D_SRC_SIZE */
420 OUT_RELOC(ring, src->bo, soff, 0, 0); /* SP_PS_2D_SRC_LO/HI */
421 OUT_RING(ring, A6XX_SP_PS_2D_SRC_PITCH_PITCH(spitch));
422 OUT_RING(ring, 0x00000000);
423 OUT_RING(ring, 0x00000000);
424 OUT_RING(ring, 0x00000000);
425 OUT_RING(ring, 0x00000000);
426 OUT_RING(ring, 0x00000000);
427
428 OUT_RING(ring, 0x00000000);
429 OUT_RING(ring, 0x00000000);
430 OUT_RING(ring, 0x00000000);
431
432 /*
433 * Emit destination:
434 */
435 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
436 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(dfmt) |
437 A6XX_RB_2D_DST_INFO_TILE_MODE(dtile) |
438 A6XX_RB_2D_DST_INFO_COLOR_SWAP(dswap));
439 OUT_RELOC(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
440 OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(dpitch));
441 OUT_RING(ring, 0x00000000);
442 OUT_RING(ring, 0x00000000);
443 OUT_RING(ring, 0x00000000);
444 OUT_RING(ring, 0x00000000);
445 OUT_RING(ring, 0x00000000);
446
447 /*
448 * Blit command:
449 */
450 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
451 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(sx1));
452 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(sx2));
453 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(sy1));
454 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(sy2));
455
456 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
457 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dx1) | A6XX_GRAS_2D_DST_TL_Y(dy1));
458 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dx2) | A6XX_GRAS_2D_DST_BR_Y(dy2));
459
460 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
461 OUT_RING(ring, 0x3f);
462 OUT_WFI5(ring);
463
464 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
465 OUT_RING(ring, 0);
466
467 OUT_PKT4(ring, REG_A6XX_SP_2D_SRC_FORMAT, 1);
468 OUT_RING(ring, A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT(sfmt) |
469 COND(util_format_is_pure_sint(info->src.format),
470 A6XX_SP_2D_SRC_FORMAT_SINT) |
471 COND(util_format_is_pure_uint(info->src.format),
472 A6XX_SP_2D_SRC_FORMAT_UINT) |
473 COND(util_format_is_snorm(info->src.format),
474 A6XX_SP_2D_SRC_FORMAT_SINT |
475 A6XX_SP_2D_SRC_FORMAT_NORM) |
476 COND(util_format_is_unorm(info->src.format),
477 // TODO sometimes blob uses UINT+NORM but dEQP seems unhappy about that
478 // A6XX_SP_2D_SRC_FORMAT_UINT |
479 A6XX_SP_2D_SRC_FORMAT_NORM) |
480 0xf000);
481
482 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
483 OUT_RING(ring, 0x01000000);
484
485 OUT_PKT7(ring, CP_BLIT, 1);
486 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
487
488 OUT_WFI5(ring);
489
490 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
491 OUT_RING(ring, 0);
492 }
493 }
494
495 static void
496 emit_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
497 {
498 struct fd_batch *batch;
499
500 fd_fence_ref(ctx->base.screen, &ctx->last_fence, NULL);
501
502 batch = fd_bc_alloc_batch(&ctx->screen->batch_cache, ctx, true);
503
504 fd6_emit_restore(batch, batch->draw);
505 fd6_emit_lrz_flush(batch->draw);
506
507 mtx_lock(&ctx->screen->lock);
508
509 fd_batch_resource_used(batch, fd_resource(info->src.resource), false);
510 fd_batch_resource_used(batch, fd_resource(info->dst.resource), true);
511
512 mtx_unlock(&ctx->screen->lock);
513
514 emit_setup(batch->draw);
515
516 if ((info->src.resource->target == PIPE_BUFFER) &&
517 (info->dst.resource->target == PIPE_BUFFER)) {
518 assert(fd_resource(info->src.resource)->tile_mode == TILE6_LINEAR);
519 assert(fd_resource(info->dst.resource)->tile_mode == TILE6_LINEAR);
520 emit_blit_buffer(batch->draw, info);
521 } else {
522 /* I don't *think* we need to handle blits between buffer <-> !buffer */
523 debug_assert(info->src.resource->target != PIPE_BUFFER);
524 debug_assert(info->dst.resource->target != PIPE_BUFFER);
525 emit_blit_texture(batch->draw, info);
526 }
527
528 fd6_event_write(batch, batch->draw, 0x1d, true);
529 fd6_event_write(batch, batch->draw, FACENESS_FLUSH, true);
530 fd6_event_write(batch, batch->draw, CACHE_FLUSH_TS, true);
531
532 fd_resource(info->dst.resource)->valid = true;
533 batch->needs_flush = true;
534
535 fd_batch_flush(batch, false, false);
536 fd_batch_reference(&batch, NULL);
537 }
538
539 static bool
540 fd6_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
541 {
542 if (!can_do_blit(info)) {
543 return false;
544 }
545
546 emit_blit(ctx, info);
547
548 return true;
549 }
550
551 void
552 fd6_blitter_init(struct pipe_context *pctx)
553 {
554 if (fd_mesa_debug & FD_DBG_NOBLIT)
555 return;
556
557 fd_context(pctx)->blit = fd6_blit;
558 }
559
560 unsigned
561 fd6_tile_mode(const struct pipe_resource *tmpl)
562 {
563 /* basically just has to be a format we can blit, so uploads/downloads
564 * via linear staging buffer works:
565 */
566 if (ok_format(tmpl->format))
567 return TILE6_3;
568
569 return TILE6_LINEAR;
570 }