freedreno/a6xx: Combine emit_blit and fd6_blit
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_blitter.c
1 /*
2 * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "util/u_dump.h"
29
30 #include "freedreno_blitter.h"
31 #include "freedreno_fence.h"
32 #include "freedreno_resource.h"
33
34 #include "fd6_blitter.h"
35 #include "fd6_format.h"
36 #include "fd6_emit.h"
37
38 /* Make sure none of the requested dimensions extend beyond the size of the
39 * resource. Not entirely sure why this happens, but sometimes it does, and
40 * w/ 2d blt doesn't have wrap modes like a sampler, so force those cases
41 * back to u_blitter
42 */
43 static bool
44 ok_dims(const struct pipe_resource *r, const struct pipe_box *b, int lvl)
45 {
46 int last_layer =
47 r->target == PIPE_TEXTURE_3D ? u_minify(r->depth0, lvl)
48 : r->array_size;
49
50 return (b->x >= 0) && (b->x + b->width <= u_minify(r->width0, lvl)) &&
51 (b->y >= 0) && (b->y + b->height <= u_minify(r->height0, lvl)) &&
52 (b->z >= 0) && (b->z + b->depth <= last_layer);
53 }
54
55 static bool
56 ok_format(enum pipe_format pfmt)
57 {
58 enum a6xx_color_fmt fmt = fd6_pipe2color(pfmt);
59 if (fmt == ~0)
60 return false;
61
62 if (fd6_ifmt(fmt) == 0)
63 return false;
64
65 return true;
66 }
67
68 #define DEBUG_BLIT_FALLBACK 0
69 #define fail_if(cond) \
70 do { \
71 if (cond) { \
72 if (DEBUG_BLIT_FALLBACK) { \
73 fprintf(stderr, "falling back: %s for blit:\n", #cond); \
74 util_dump_blit_info(stderr, info); \
75 fprintf(stderr, "\nsrc: "); \
76 util_dump_resource(stderr, info->src.resource); \
77 fprintf(stderr, "\ndst: "); \
78 util_dump_resource(stderr, info->dst.resource); \
79 fprintf(stderr, "\n"); \
80 } \
81 return false; \
82 } \
83 } while (0)
84
85 static bool
86 can_do_blit(const struct pipe_blit_info *info)
87 {
88 /* I think we can do scaling, but not in z dimension since that would
89 * require blending..
90 */
91 fail_if(info->dst.box.depth != info->src.box.depth);
92
93 /* We can blit if both or neither formats are compressed formats... */
94 fail_if(util_format_is_compressed(info->src.format) !=
95 util_format_is_compressed(info->src.format));
96
97 /* Fail if unsupported format: */
98 fail_if(!ok_format(info->src.format));
99 fail_if(!ok_format(info->dst.format));
100
101 /* ... but only if they're the same compression format. */
102 fail_if(util_format_is_compressed(info->src.format) &&
103 info->src.format != info->dst.format);
104
105 /* src box can be inverted, which we don't support.. dst box cannot: */
106 fail_if((info->src.box.width < 0) || (info->src.box.height < 0));
107
108 fail_if(!ok_dims(info->src.resource, &info->src.box, info->src.level));
109
110 fail_if(!ok_dims(info->dst.resource, &info->dst.box, info->dst.level));
111
112 debug_assert(info->dst.box.width >= 0);
113 debug_assert(info->dst.box.height >= 0);
114 debug_assert(info->dst.box.depth >= 0);
115
116 /* non-multisampled could either have nr_samples == 0 or == 1 */
117 fail_if(info->dst.resource->nr_samples > 1);
118 fail_if(info->src.resource->nr_samples > 1);
119
120 fail_if(info->window_rectangle_include);
121
122 fail_if(util_format_is_srgb(info->src.format));
123 fail_if(util_format_is_srgb(info->dst.format));
124
125 const struct util_format_description *src_desc =
126 util_format_description(info->src.format);
127 const struct util_format_description *dst_desc =
128 util_format_description(info->dst.format);
129 const int common_channels = MIN2(src_desc->nr_channels, dst_desc->nr_channels);
130
131 if (info->mask & PIPE_MASK_RGBA) {
132 for (int i = 0; i < common_channels; i++) {
133 fail_if(memcmp(&src_desc->channel[i],
134 &dst_desc->channel[i],
135 sizeof(src_desc->channel[0])));
136 }
137 }
138
139 fail_if(info->alpha_blend);
140
141 return true;
142 }
143
144 static void
145 emit_setup(struct fd_ringbuffer *ring)
146 {
147 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
148 OUT_RING(ring, PC_CCU_INVALIDATE_COLOR);
149
150 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
151 OUT_RING(ring, LRZ_FLUSH);
152
153 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
154 OUT_RING(ring, 0x0);
155
156 OUT_WFI5(ring);
157
158 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
159 OUT_RING(ring, 0x10000000);
160 }
161
162 static uint32_t
163 blit_control(enum a6xx_color_fmt fmt)
164 {
165 unsigned blit_cntl = 0xf00000;
166 blit_cntl |= A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(fmt);
167 blit_cntl |= A6XX_RB_2D_BLIT_CNTL_IFMT(fd6_ifmt(fmt));
168 return blit_cntl;
169 }
170
171 /* buffers need to be handled specially since x/width can exceed the bounds
172 * supported by hw.. if necessary decompose into (potentially) two 2D blits
173 */
174 static void
175 emit_blit_buffer(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
176 {
177 const struct pipe_box *sbox = &info->src.box;
178 const struct pipe_box *dbox = &info->dst.box;
179 struct fd_resource *src, *dst;
180 unsigned sshift, dshift;
181
182 if (DEBUG_BLIT_FALLBACK) {
183 fprintf(stderr, "buffer blit: ");
184 util_dump_blit_info(stderr, info);
185 fprintf(stderr, "\ndst resource: ");
186 util_dump_resource(stderr, info->dst.resource);
187 fprintf(stderr, "\nsrc resource: ");
188 util_dump_resource(stderr, info->src.resource);
189 fprintf(stderr, "\n");
190 }
191
192 src = fd_resource(info->src.resource);
193 dst = fd_resource(info->dst.resource);
194
195 debug_assert(src->cpp == 1);
196 debug_assert(dst->cpp == 1);
197 debug_assert(info->src.resource->format == info->dst.resource->format);
198 debug_assert((sbox->y == 0) && (sbox->height == 1));
199 debug_assert((dbox->y == 0) && (dbox->height == 1));
200 debug_assert((sbox->z == 0) && (sbox->depth == 1));
201 debug_assert((dbox->z == 0) && (dbox->depth == 1));
202 debug_assert(sbox->width == dbox->width);
203 debug_assert(info->src.level == 0);
204 debug_assert(info->dst.level == 0);
205
206 /*
207 * Buffers can have dimensions bigger than max width, remap into
208 * multiple 1d blits to fit within max dimension
209 *
210 * Note that blob uses .ARRAY_PITCH=128 for blitting buffers, which
211 * seems to prevent overfetch related faults. Not quite sure what
212 * the deal is there.
213 *
214 * Low 6 bits of SRC/DST addresses need to be zero (ie. address
215 * aligned to 64) so we need to shift src/dst x1/x2 to make up the
216 * difference. On top of already splitting up the blit so width
217 * isn't > 16k.
218 *
219 * We perhaps could do a bit better, if src and dst are aligned but
220 * in the worst case this means we have to split the copy up into
221 * 16k (0x4000) minus 64 (0x40).
222 */
223
224 sshift = sbox->x & 0x3f;
225 dshift = dbox->x & 0x3f;
226
227 OUT_PKT7(ring, CP_SET_MARKER, 1);
228 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
229
230 uint32_t blit_cntl = blit_control(RB6_R8_UNORM) | 0x20000000;
231 OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
232 OUT_RING(ring, blit_cntl);
233
234 OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
235 OUT_RING(ring, blit_cntl);
236
237 for (unsigned off = 0; off < sbox->width; off += (0x4000 - 0x40)) {
238 unsigned soff, doff, w, p;
239
240 soff = (sbox->x + off) & ~0x3f;
241 doff = (dbox->x + off) & ~0x3f;
242
243 w = MIN2(sbox->width - off, (0x4000 - 0x40));
244 p = align(w, 64);
245
246 debug_assert((soff + w) <= fd_bo_size(src->bo));
247 debug_assert((doff + w) <= fd_bo_size(dst->bo));
248
249 /*
250 * Emit source:
251 */
252 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 13);
253 OUT_RING(ring, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(RB6_R8_UNORM) |
254 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(TILE6_LINEAR) |
255 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(WZYX) | 0x500000);
256 OUT_RING(ring, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(sshift + w) |
257 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(1)); /* SP_PS_2D_SRC_SIZE */
258 OUT_RELOC(ring, src->bo, soff, 0, 0); /* SP_PS_2D_SRC_LO/HI */
259 OUT_RING(ring, A6XX_SP_PS_2D_SRC_PITCH_PITCH(p));
260
261 OUT_RING(ring, 0x00000000);
262 OUT_RING(ring, 0x00000000);
263 OUT_RING(ring, 0x00000000);
264 OUT_RING(ring, 0x00000000);
265 OUT_RING(ring, 0x00000000);
266
267 OUT_RING(ring, 0x00000000);
268 OUT_RING(ring, 0x00000000);
269 OUT_RING(ring, 0x00000000);
270
271 /*
272 * Emit destination:
273 */
274 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
275 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(RB6_R8_UNORM) |
276 A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
277 A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
278 OUT_RELOC(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
279 OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(p));
280 OUT_RING(ring, 0x00000000);
281 OUT_RING(ring, 0x00000000);
282 OUT_RING(ring, 0x00000000);
283 OUT_RING(ring, 0x00000000);
284 OUT_RING(ring, 0x00000000);
285
286 /*
287 * Blit command:
288 */
289 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
290 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(sshift));
291 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(sshift + w - 1));
292 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(0));
293 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(0));
294
295 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
296 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dshift) | A6XX_GRAS_2D_DST_TL_Y(0));
297 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dshift + w - 1) | A6XX_GRAS_2D_DST_BR_Y(0));
298
299 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
300 OUT_RING(ring, 0x3f);
301 OUT_WFI5(ring);
302
303 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
304 OUT_RING(ring, 0);
305
306 OUT_PKT4(ring, REG_A6XX_SP_2D_SRC_FORMAT, 1);
307 OUT_RING(ring, 0xf180);
308
309 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
310 OUT_RING(ring, 0x01000000);
311
312 OUT_PKT7(ring, CP_BLIT, 1);
313 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
314
315 OUT_WFI5(ring);
316
317 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
318 OUT_RING(ring, 0);
319 }
320 }
321
322 static void
323 emit_blit_texture(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
324 {
325 const struct pipe_box *sbox = &info->src.box;
326 const struct pipe_box *dbox = &info->dst.box;
327 struct fd_resource *src, *dst;
328 struct fd_resource_slice *sslice, *dslice;
329 enum a6xx_color_fmt sfmt, dfmt;
330 enum a6xx_tile_mode stile, dtile;
331 enum a3xx_color_swap sswap, dswap;
332 unsigned spitch, dpitch;
333 unsigned sx1, sy1, sx2, sy2;
334 unsigned dx1, dy1, dx2, dy2;
335
336 if (DEBUG_BLIT_FALLBACK) {
337 fprintf(stderr, "texture blit: ");
338 util_dump_blit_info(stderr, info);
339 fprintf(stderr, "\ndst resource: ");
340 util_dump_resource(stderr, info->dst.resource);
341 fprintf(stderr, "\nsrc resource: ");
342 util_dump_resource(stderr, info->src.resource);
343 fprintf(stderr, "\n");
344 }
345
346 src = fd_resource(info->src.resource);
347 dst = fd_resource(info->dst.resource);
348
349 sslice = fd_resource_slice(src, info->src.level);
350 dslice = fd_resource_slice(dst, info->dst.level);
351
352 sfmt = fd6_pipe2color(info->src.format);
353 dfmt = fd6_pipe2color(info->dst.format);
354
355 int blocksize = util_format_get_blocksize(info->src.format);
356 int blockwidth = util_format_get_blockwidth(info->src.format);
357 int blockheight = util_format_get_blockheight(info->src.format);
358 int nelements;
359
360 stile = fd_resource_level_linear(info->src.resource, info->src.level) ?
361 TILE6_LINEAR : src->tile_mode;
362 dtile = fd_resource_level_linear(info->dst.resource, info->dst.level) ?
363 TILE6_LINEAR : dst->tile_mode;
364
365 sswap = stile ? WZYX : fd6_pipe2swap(info->src.format);
366 dswap = dtile ? WZYX : fd6_pipe2swap(info->dst.format);
367
368 if (util_format_is_compressed(info->src.format)) {
369 debug_assert(info->src.format == info->dst.format);
370 sfmt = dfmt = RB6_R8_UNORM;
371 nelements = blocksize;
372 } else {
373 debug_assert(!util_format_is_compressed(info->dst.format));
374 nelements = 1;
375 }
376
377 spitch = DIV_ROUND_UP(sslice->pitch, blockwidth) * src->cpp;
378 dpitch = DIV_ROUND_UP(dslice->pitch, blockwidth) * dst->cpp;
379
380 sx1 = sbox->x / blockwidth * nelements;
381 sy1 = sbox->y / blockheight;
382 sx2 = DIV_ROUND_UP(sbox->x + sbox->width, blockwidth) * nelements - 1;
383 sy2 = DIV_ROUND_UP(sbox->y + sbox->height, blockheight) - 1;
384
385 dx1 = dbox->x / blockwidth * nelements;
386 dy1 = dbox->y / blockheight;
387 dx2 = DIV_ROUND_UP(dbox->x + dbox->width, blockwidth) * nelements - 1;
388 dy2 = DIV_ROUND_UP(dbox->y + dbox->height, blockheight) - 1;
389
390 uint32_t width = DIV_ROUND_UP(u_minify(src->base.width0, info->src.level), blockwidth) * nelements;
391 uint32_t height = DIV_ROUND_UP(u_minify(src->base.height0, info->src.level), blockheight);
392
393 OUT_PKT7(ring, CP_SET_MARKER, 1);
394 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
395
396 uint32_t blit_cntl = blit_control(dfmt);
397
398 if (dtile != stile)
399 blit_cntl |= 0x20000000;
400
401 if (info->scissor_enable) {
402 OUT_PKT4(ring, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
403 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(info->scissor.minx) |
404 A6XX_GRAS_RESOLVE_CNTL_1_Y(info->scissor.miny));
405 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(info->scissor.maxx - 1) |
406 A6XX_GRAS_RESOLVE_CNTL_1_Y(info->scissor.maxy - 1));
407 blit_cntl |= A6XX_RB_2D_BLIT_CNTL_SCISSOR;
408 }
409
410 OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
411 OUT_RING(ring, blit_cntl);
412
413 OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
414 OUT_RING(ring, blit_cntl);
415
416 for (unsigned i = 0; i < info->dst.box.depth; i++) {
417 unsigned soff = fd_resource_offset(src, info->src.level, sbox->z + i);
418 unsigned doff = fd_resource_offset(dst, info->dst.level, dbox->z + i);
419
420 /*
421 * Emit source:
422 */
423 uint32_t filter = 0;
424 if (info->filter == PIPE_TEX_FILTER_LINEAR)
425 filter = A6XX_SP_PS_2D_SRC_INFO_FILTER;
426
427 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 13);
428 OUT_RING(ring, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(sfmt) |
429 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(stile) |
430 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(sswap) | 0x500000 | filter);
431 OUT_RING(ring, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(width) |
432 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(height)); /* SP_PS_2D_SRC_SIZE */
433 OUT_RELOC(ring, src->bo, soff, 0, 0); /* SP_PS_2D_SRC_LO/HI */
434 OUT_RING(ring, A6XX_SP_PS_2D_SRC_PITCH_PITCH(spitch));
435 OUT_RING(ring, 0x00000000);
436 OUT_RING(ring, 0x00000000);
437 OUT_RING(ring, 0x00000000);
438 OUT_RING(ring, 0x00000000);
439 OUT_RING(ring, 0x00000000);
440
441 OUT_RING(ring, 0x00000000);
442 OUT_RING(ring, 0x00000000);
443 OUT_RING(ring, 0x00000000);
444
445 /*
446 * Emit destination:
447 */
448 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
449 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(dfmt) |
450 A6XX_RB_2D_DST_INFO_TILE_MODE(dtile) |
451 A6XX_RB_2D_DST_INFO_COLOR_SWAP(dswap));
452 OUT_RELOCW(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
453 OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(dpitch));
454 OUT_RING(ring, 0x00000000);
455 OUT_RING(ring, 0x00000000);
456 OUT_RING(ring, 0x00000000);
457 OUT_RING(ring, 0x00000000);
458 OUT_RING(ring, 0x00000000);
459
460 /*
461 * Blit command:
462 */
463 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
464 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(sx1));
465 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(sx2));
466 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(sy1));
467 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(sy2));
468
469 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
470 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dx1) | A6XX_GRAS_2D_DST_TL_Y(dy1));
471 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dx2) | A6XX_GRAS_2D_DST_BR_Y(dy2));
472
473 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
474 OUT_RING(ring, 0x3f);
475 OUT_WFI5(ring);
476
477 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
478 OUT_RING(ring, 0);
479
480 OUT_PKT4(ring, REG_A6XX_SP_2D_SRC_FORMAT, 1);
481 OUT_RING(ring, A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT(sfmt) |
482 COND(util_format_is_pure_sint(info->src.format),
483 A6XX_SP_2D_SRC_FORMAT_SINT) |
484 COND(util_format_is_pure_uint(info->src.format),
485 A6XX_SP_2D_SRC_FORMAT_UINT) |
486 COND(util_format_is_snorm(info->src.format),
487 A6XX_SP_2D_SRC_FORMAT_SINT |
488 A6XX_SP_2D_SRC_FORMAT_NORM) |
489 COND(util_format_is_unorm(info->src.format),
490 // TODO sometimes blob uses UINT+NORM but dEQP seems unhappy about that
491 // A6XX_SP_2D_SRC_FORMAT_UINT |
492 A6XX_SP_2D_SRC_FORMAT_NORM) |
493 0xf000);
494
495 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
496 OUT_RING(ring, 0x01000000);
497
498 OUT_PKT7(ring, CP_BLIT, 1);
499 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
500
501 OUT_WFI5(ring);
502
503 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
504 OUT_RING(ring, 0);
505 }
506 }
507
508 static bool
509 fd6_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
510 {
511 struct fd_batch *batch;
512
513 if (!can_do_blit(info))
514 return false;
515
516 fd_fence_ref(ctx->base.screen, &ctx->last_fence, NULL);
517
518 batch = fd_bc_alloc_batch(&ctx->screen->batch_cache, ctx, true);
519
520 fd6_emit_restore(batch, batch->draw);
521 fd6_emit_lrz_flush(batch->draw);
522
523 mtx_lock(&ctx->screen->lock);
524
525 fd_batch_resource_used(batch, fd_resource(info->src.resource), false);
526 fd_batch_resource_used(batch, fd_resource(info->dst.resource), true);
527
528 mtx_unlock(&ctx->screen->lock);
529
530 emit_setup(batch->draw);
531
532 if ((info->src.resource->target == PIPE_BUFFER) &&
533 (info->dst.resource->target == PIPE_BUFFER)) {
534 assert(fd_resource(info->src.resource)->tile_mode == TILE6_LINEAR);
535 assert(fd_resource(info->dst.resource)->tile_mode == TILE6_LINEAR);
536 emit_blit_buffer(batch->draw, info);
537 } else {
538 /* I don't *think* we need to handle blits between buffer <-> !buffer */
539 debug_assert(info->src.resource->target != PIPE_BUFFER);
540 debug_assert(info->dst.resource->target != PIPE_BUFFER);
541 emit_blit_texture(batch->draw, info);
542 }
543
544 fd6_event_write(batch, batch->draw, 0x1d, true);
545 fd6_event_write(batch, batch->draw, FACENESS_FLUSH, true);
546 fd6_event_write(batch, batch->draw, CACHE_FLUSH_TS, true);
547
548 fd_resource(info->dst.resource)->valid = true;
549 batch->needs_flush = true;
550
551 fd_batch_flush(batch, false, false);
552 fd_batch_reference(&batch, NULL);
553
554 return true;
555 }
556
557 void
558 fd6_blitter_init(struct pipe_context *pctx)
559 {
560 if (fd_mesa_debug & FD_DBG_NOBLIT)
561 return;
562
563 fd_context(pctx)->blit = fd6_blit;
564 }
565
566 unsigned
567 fd6_tile_mode(const struct pipe_resource *tmpl)
568 {
569 /* basically just has to be a format we can blit, so uploads/downloads
570 * via linear staging buffer works:
571 */
572 if (ok_format(tmpl->format))
573 return TILE6_3;
574
575 return TILE6_LINEAR;
576 }