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freedreno: clear last_fence after resource tracking
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_blitter.c
1 /*
2 * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "util/u_dump.h"
29 #include "util/half_float.h"
30
31 #include "freedreno_blitter.h"
32 #include "freedreno_fence.h"
33 #include "freedreno_log.h"
34 #include "freedreno_resource.h"
35
36 #include "fd6_blitter.h"
37 #include "fd6_format.h"
38 #include "fd6_emit.h"
39 #include "fd6_resource.h"
40 #include "fd6_pack.h"
41
42 /* Make sure none of the requested dimensions extend beyond the size of the
43 * resource. Not entirely sure why this happens, but sometimes it does, and
44 * w/ 2d blt doesn't have wrap modes like a sampler, so force those cases
45 * back to u_blitter
46 */
47 static bool
48 ok_dims(const struct pipe_resource *r, const struct pipe_box *b, int lvl)
49 {
50 int last_layer =
51 r->target == PIPE_TEXTURE_3D ? u_minify(r->depth0, lvl)
52 : r->array_size;
53
54 return (b->x >= 0) && (b->x + b->width <= u_minify(r->width0, lvl)) &&
55 (b->y >= 0) && (b->y + b->height <= u_minify(r->height0, lvl)) &&
56 (b->z >= 0) && (b->z + b->depth <= last_layer);
57 }
58
59 static bool
60 ok_format(enum pipe_format pfmt)
61 {
62 enum a6xx_format fmt = fd6_pipe2color(pfmt);
63
64 if (util_format_is_compressed(pfmt))
65 return true;
66
67 switch (pfmt) {
68 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
69 case PIPE_FORMAT_Z24X8_UNORM:
70 case PIPE_FORMAT_Z16_UNORM:
71 case PIPE_FORMAT_Z32_UNORM:
72 case PIPE_FORMAT_Z32_FLOAT:
73 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
74 case PIPE_FORMAT_S8_UINT:
75 return true;
76 default:
77 break;
78 }
79
80 if (fmt == FMT6_NONE)
81 return false;
82
83 if (fd6_ifmt(fmt) == 0)
84 return false;
85
86 return true;
87 }
88
89 #define DEBUG_BLIT 0
90 #define DEBUG_BLIT_FALLBACK 0
91
92 #define fail_if(cond) \
93 do { \
94 if (cond) { \
95 if (DEBUG_BLIT_FALLBACK) { \
96 fprintf(stderr, "falling back: %s for blit:\n", #cond); \
97 util_dump_blit_info(stderr, info); \
98 fprintf(stderr, "\nsrc: "); \
99 util_dump_resource(stderr, info->src.resource); \
100 fprintf(stderr, "\ndst: "); \
101 util_dump_resource(stderr, info->dst.resource); \
102 fprintf(stderr, "\n"); \
103 } \
104 return false; \
105 } \
106 } while (0)
107
108 static bool
109 can_do_blit(const struct pipe_blit_info *info)
110 {
111 /* I think we can do scaling, but not in z dimension since that would
112 * require blending..
113 */
114 fail_if(info->dst.box.depth != info->src.box.depth);
115
116 /* Fail if unsupported format: */
117 fail_if(!ok_format(info->src.format));
118 fail_if(!ok_format(info->dst.format));
119
120 debug_assert(!util_format_is_compressed(info->src.format));
121 debug_assert(!util_format_is_compressed(info->dst.format));
122
123 fail_if(!ok_dims(info->src.resource, &info->src.box, info->src.level));
124
125 fail_if(!ok_dims(info->dst.resource, &info->dst.box, info->dst.level));
126
127 debug_assert(info->dst.box.width >= 0);
128 debug_assert(info->dst.box.height >= 0);
129 debug_assert(info->dst.box.depth >= 0);
130
131 fail_if(info->dst.resource->nr_samples > 1);
132
133 fail_if(info->window_rectangle_include);
134
135 const struct util_format_description *src_desc =
136 util_format_description(info->src.format);
137 const struct util_format_description *dst_desc =
138 util_format_description(info->dst.format);
139 const int common_channels = MIN2(src_desc->nr_channels, dst_desc->nr_channels);
140
141 if (info->mask & PIPE_MASK_RGBA) {
142 for (int i = 0; i < common_channels; i++) {
143 fail_if(memcmp(&src_desc->channel[i],
144 &dst_desc->channel[i],
145 sizeof(src_desc->channel[0])));
146 }
147 }
148
149 fail_if(info->alpha_blend);
150
151 return true;
152 }
153
154 static void
155 emit_setup(struct fd_batch *batch)
156 {
157 struct fd_ringbuffer *ring = batch->draw;
158
159 fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
160 fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
161 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
162 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_DEPTH, false);
163
164 /* normal BLIT_OP_SCALE operation needs bypass RB_CCU_CNTL */
165 OUT_WFI5(ring);
166 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
167 OUT_RING(ring, fd6_context(batch->ctx)->magic.RB_CCU_CNTL_bypass);
168 }
169
170 static uint32_t
171 blit_control(enum a6xx_format fmt, bool is_srgb)
172 {
173 enum a6xx_2d_ifmt ifmt = fd6_ifmt(fmt);
174
175 if (is_srgb) {
176 assert(ifmt == R2D_UNORM8);
177 ifmt = R2D_UNORM8_SRGB;
178 }
179
180 return A6XX_RB_2D_BLIT_CNTL_MASK(0xf) |
181 A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(fmt) |
182 A6XX_RB_2D_BLIT_CNTL_IFMT(ifmt);
183 }
184
185 /* buffers need to be handled specially since x/width can exceed the bounds
186 * supported by hw.. if necessary decompose into (potentially) two 2D blits
187 */
188 static void
189 emit_blit_buffer(struct fd_context *ctx, struct fd_ringbuffer *ring,
190 const struct pipe_blit_info *info)
191 {
192 const struct pipe_box *sbox = &info->src.box;
193 const struct pipe_box *dbox = &info->dst.box;
194 struct fd_resource *src, *dst;
195 unsigned sshift, dshift;
196
197 if (DEBUG_BLIT) {
198 fprintf(stderr, "buffer blit: ");
199 util_dump_blit_info(stderr, info);
200 fprintf(stderr, "\ndst resource: ");
201 util_dump_resource(stderr, info->dst.resource);
202 fprintf(stderr, "\nsrc resource: ");
203 util_dump_resource(stderr, info->src.resource);
204 fprintf(stderr, "\n");
205 }
206
207 src = fd_resource(info->src.resource);
208 dst = fd_resource(info->dst.resource);
209
210 debug_assert(src->layout.cpp == 1);
211 debug_assert(dst->layout.cpp == 1);
212 debug_assert(info->src.resource->format == info->dst.resource->format);
213 debug_assert((sbox->y == 0) && (sbox->height == 1));
214 debug_assert((dbox->y == 0) && (dbox->height == 1));
215 debug_assert((sbox->z == 0) && (sbox->depth == 1));
216 debug_assert((dbox->z == 0) && (dbox->depth == 1));
217 debug_assert(sbox->width == dbox->width);
218 debug_assert(info->src.level == 0);
219 debug_assert(info->dst.level == 0);
220
221 /*
222 * Buffers can have dimensions bigger than max width, remap into
223 * multiple 1d blits to fit within max dimension
224 *
225 * Note that blob uses .ARRAY_PITCH=128 for blitting buffers, which
226 * seems to prevent overfetch related faults. Not quite sure what
227 * the deal is there.
228 *
229 * Low 6 bits of SRC/DST addresses need to be zero (ie. address
230 * aligned to 64) so we need to shift src/dst x1/x2 to make up the
231 * difference. On top of already splitting up the blit so width
232 * isn't > 16k.
233 *
234 * We perhaps could do a bit better, if src and dst are aligned but
235 * in the worst case this means we have to split the copy up into
236 * 16k (0x4000) minus 64 (0x40).
237 */
238
239 sshift = sbox->x & 0x3f;
240 dshift = dbox->x & 0x3f;
241
242 OUT_PKT7(ring, CP_SET_MARKER, 1);
243 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
244
245 uint32_t blit_cntl = blit_control(FMT6_8_UNORM, false) | 0x20000000;
246 OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
247 OUT_RING(ring, blit_cntl);
248
249 OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
250 OUT_RING(ring, blit_cntl);
251
252 for (unsigned off = 0; off < sbox->width; off += (0x4000 - 0x40)) {
253 unsigned soff, doff, w, p;
254
255 soff = (sbox->x + off) & ~0x3f;
256 doff = (dbox->x + off) & ~0x3f;
257
258 w = MIN2(sbox->width - off, (0x4000 - 0x40));
259 p = align(w, 64);
260
261 debug_assert((soff + w) <= fd_bo_size(src->bo));
262 debug_assert((doff + w) <= fd_bo_size(dst->bo));
263
264 /*
265 * Emit source:
266 */
267 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 10);
268 OUT_RING(ring, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(FMT6_8_UNORM) |
269 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(TILE6_LINEAR) |
270 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(WZYX) |
271 0x500000);
272 OUT_RING(ring, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(sshift + w) |
273 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(1)); /* SP_PS_2D_SRC_SIZE */
274 OUT_RELOC(ring, src->bo, soff, 0, 0); /* SP_PS_2D_SRC_LO/HI */
275 OUT_RING(ring, A6XX_SP_PS_2D_SRC_PITCH_PITCH(p));
276
277 OUT_RING(ring, 0x00000000);
278 OUT_RING(ring, 0x00000000);
279 OUT_RING(ring, 0x00000000);
280 OUT_RING(ring, 0x00000000);
281 OUT_RING(ring, 0x00000000);
282
283 /*
284 * Emit destination:
285 */
286 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
287 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(FMT6_8_UNORM) |
288 A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
289 A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
290 OUT_RELOC(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
291 OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(p));
292 OUT_RING(ring, 0x00000000);
293 OUT_RING(ring, 0x00000000);
294 OUT_RING(ring, 0x00000000);
295 OUT_RING(ring, 0x00000000);
296 OUT_RING(ring, 0x00000000);
297
298 /*
299 * Blit command:
300 */
301 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
302 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(sshift));
303 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(sshift + w - 1));
304 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(0));
305 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(0));
306
307 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
308 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dshift) | A6XX_GRAS_2D_DST_TL_Y(0));
309 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dshift + w - 1) | A6XX_GRAS_2D_DST_BR_Y(0));
310
311 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
312 OUT_RING(ring, 0x3f);
313 OUT_WFI5(ring);
314
315 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
316 OUT_RING(ring, 0);
317
318 OUT_PKT4(ring, REG_A6XX_SP_2D_SRC_FORMAT, 1);
319 OUT_RING(ring, 0xf180);
320
321 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
322 OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
323
324 OUT_PKT7(ring, CP_BLIT, 1);
325 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
326
327 OUT_WFI5(ring);
328
329 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
330 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
331 }
332 }
333
334 static void
335 emit_blit_or_clear_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
336 const struct pipe_blit_info *info, union pipe_color_union *color)
337 {
338 const struct pipe_box *sbox = &info->src.box;
339 const struct pipe_box *dbox = &info->dst.box;
340 struct fd_resource *src, *dst;
341 struct fdl_slice *sslice, *dslice;
342 enum a6xx_format sfmt, dfmt;
343 enum a6xx_tile_mode stile, dtile;
344 enum a3xx_color_swap sswap, dswap;
345 int sx1, sy1, sx2, sy2;
346 int dx1, dy1, dx2, dy2;
347
348 if (DEBUG_BLIT) {
349 fprintf(stderr, "texture blit: ");
350 util_dump_blit_info(stderr, info);
351 fprintf(stderr, "\ndst resource: ");
352 util_dump_resource(stderr, info->dst.resource);
353 fprintf(stderr, "\nsrc resource: ");
354 util_dump_resource(stderr, info->src.resource);
355 fprintf(stderr, "\n");
356 }
357
358 src = fd_resource(info->src.resource);
359 dst = fd_resource(info->dst.resource);
360
361 sslice = fd_resource_slice(src, info->src.level);
362 dslice = fd_resource_slice(dst, info->dst.level);
363
364 sfmt = fd6_pipe2color(info->src.format);
365 dfmt = fd6_pipe2color(info->dst.format);
366
367 stile = fd_resource_tile_mode(info->src.resource, info->src.level);
368 dtile = fd_resource_tile_mode(info->dst.resource, info->dst.level);
369
370 /* Linear levels of a tiled resource are always WZYX, so look at
371 * rsc->tile_mode to determine the swap.
372 */
373 sswap = fd6_resource_swap(src, info->src.format);
374 dswap = fd6_resource_swap(dst, info->dst.format);
375
376 uint32_t nr_samples = fd_resource_nr_samples(&dst->base);
377 sx1 = sbox->x * nr_samples;
378 sy1 = sbox->y;
379 sx2 = (sbox->x + sbox->width) * nr_samples - 1;
380 sy2 = sbox->y + sbox->height - 1;
381
382 dx1 = dbox->x * nr_samples;
383 dy1 = dbox->y;
384 dx2 = (dbox->x + dbox->width) * nr_samples - 1;
385 dy2 = dbox->y + dbox->height - 1;
386
387 uint32_t width = u_minify(src->base.width0, info->src.level) * nr_samples;
388 uint32_t height = u_minify(src->base.height0, info->src.level);
389
390 OUT_PKT7(ring, CP_SET_MARKER, 1);
391 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
392
393 uint32_t blit_cntl = blit_control(dfmt, util_format_is_srgb(info->dst.format));
394
395 if (color) {
396 blit_cntl |= A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR;
397
398 switch (info->dst.format) {
399 case PIPE_FORMAT_Z24X8_UNORM:
400 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
401 case PIPE_FORMAT_X24S8_UINT: {
402 uint32_t depth_unorm24 = color->f[0] * ((1u << 24) - 1);
403 uint8_t stencil = color->ui[1];
404 color->ui[0] = depth_unorm24 & 0xff;
405 color->ui[1] = (depth_unorm24 >> 8) & 0xff;
406 color->ui[2] = (depth_unorm24 >> 16) & 0xff;
407 color->ui[3] = stencil;
408
409 dfmt = FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
410 break;
411 }
412 case PIPE_FORMAT_B5G6R5_UNORM:
413 case PIPE_FORMAT_B5G5R5A1_UNORM:
414 case PIPE_FORMAT_B5G5R5X1_UNORM:
415 case PIPE_FORMAT_B4G4R4A4_UNORM:
416 color->ui[0] = float_to_ubyte(color->f[0]);
417 color->ui[1] = float_to_ubyte(color->f[1]);
418 color->ui[2] = float_to_ubyte(color->f[2]);
419 color->ui[3] = float_to_ubyte(color->f[3]);
420 break;
421 default:
422 break;
423 }
424
425 OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
426
427 switch (fd6_ifmt(dfmt)) {
428 case R2D_UNORM8:
429 case R2D_UNORM8_SRGB:
430 OUT_RING(ring, float_to_ubyte(color->f[0]));
431 OUT_RING(ring, float_to_ubyte(color->f[1]));
432 OUT_RING(ring, float_to_ubyte(color->f[2]));
433 OUT_RING(ring, float_to_ubyte(color->f[3]));
434 break;
435 case R2D_FLOAT16:
436 OUT_RING(ring, _mesa_float_to_half(color->f[0]));
437 OUT_RING(ring, _mesa_float_to_half(color->f[1]));
438 OUT_RING(ring, _mesa_float_to_half(color->f[2]));
439 OUT_RING(ring, _mesa_float_to_half(color->f[3]));
440 sfmt = FMT6_16_16_16_16_FLOAT;
441 break;
442
443 case R2D_FLOAT32:
444 case R2D_INT32:
445 case R2D_INT16:
446 case R2D_INT8:
447 case R2D_RAW:
448 default:
449 OUT_RING(ring, color->ui[0]);
450 OUT_RING(ring, color->ui[1]);
451 OUT_RING(ring, color->ui[2]);
452 OUT_RING(ring, color->ui[3]);
453 break;
454 }
455 }
456
457 if (dtile != stile)
458 blit_cntl |= 0x20000000;
459
460 if (info->scissor_enable) {
461 OUT_PKT4(ring, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
462 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(info->scissor.minx) |
463 A6XX_GRAS_RESOLVE_CNTL_1_Y(info->scissor.miny));
464 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(info->scissor.maxx - 1) |
465 A6XX_GRAS_RESOLVE_CNTL_1_Y(info->scissor.maxy - 1));
466 blit_cntl |= A6XX_RB_2D_BLIT_CNTL_SCISSOR;
467 }
468
469 OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
470 OUT_RING(ring, blit_cntl);
471
472 OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
473 OUT_RING(ring, blit_cntl);
474
475 for (unsigned i = 0; i < info->dst.box.depth; i++) {
476 unsigned soff = fd_resource_offset(src, info->src.level, sbox->z + i);
477 unsigned doff = fd_resource_offset(dst, info->dst.level, dbox->z + i);
478 bool subwc_enabled = fd_resource_ubwc_enabled(src, info->src.level);
479 bool dubwc_enabled = fd_resource_ubwc_enabled(dst, info->dst.level);
480
481 /*
482 * Emit source:
483 */
484 uint32_t filter = 0;
485 if (info->filter == PIPE_TEX_FILTER_LINEAR)
486 filter = A6XX_SP_PS_2D_SRC_INFO_FILTER;
487
488 enum a3xx_msaa_samples samples = fd_msaa_samples(src->base.nr_samples);
489
490 if (sfmt == FMT6_10_10_10_2_UNORM_DEST)
491 sfmt = FMT6_10_10_10_2_UNORM;
492
493 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 10);
494 OUT_RING(ring, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(sfmt) |
495 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(stile) |
496 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(sswap) |
497 A6XX_SP_PS_2D_SRC_INFO_SAMPLES(samples) |
498 COND(samples > MSAA_ONE && (info->mask & PIPE_MASK_RGBA),
499 A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE) |
500 COND(subwc_enabled, A6XX_SP_PS_2D_SRC_INFO_FLAGS) |
501 COND(util_format_is_srgb(info->src.format), A6XX_SP_PS_2D_SRC_INFO_SRGB) |
502 0x500000 | filter);
503 OUT_RING(ring, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(width) |
504 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(height)); /* SP_PS_2D_SRC_SIZE */
505 OUT_RELOC(ring, src->bo, soff, 0, 0); /* SP_PS_2D_SRC_LO/HI */
506 OUT_RING(ring, A6XX_SP_PS_2D_SRC_PITCH_PITCH(sslice->pitch));
507
508 OUT_RING(ring, 0x00000000);
509 OUT_RING(ring, 0x00000000);
510 OUT_RING(ring, 0x00000000);
511 OUT_RING(ring, 0x00000000);
512 OUT_RING(ring, 0x00000000);
513
514 if (subwc_enabled) {
515 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_FLAGS_LO, 6);
516 fd6_emit_flag_reference(ring, src, info->src.level, sbox->z + i);
517 OUT_RING(ring, 0x00000000);
518 OUT_RING(ring, 0x00000000);
519 OUT_RING(ring, 0x00000000);
520 }
521
522 /*
523 * Emit destination:
524 */
525 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
526 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(dfmt) |
527 A6XX_RB_2D_DST_INFO_TILE_MODE(dtile) |
528 A6XX_RB_2D_DST_INFO_COLOR_SWAP(dswap) |
529 COND(util_format_is_srgb(info->dst.format), A6XX_RB_2D_DST_INFO_SRGB) |
530 COND(dubwc_enabled, A6XX_RB_2D_DST_INFO_FLAGS));
531 OUT_RELOC(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
532 OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(dslice->pitch));
533 OUT_RING(ring, 0x00000000);
534 OUT_RING(ring, 0x00000000);
535 OUT_RING(ring, 0x00000000);
536 OUT_RING(ring, 0x00000000);
537 OUT_RING(ring, 0x00000000);
538
539 if (dubwc_enabled) {
540 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_FLAGS_LO, 6);
541 fd6_emit_flag_reference(ring, dst, info->dst.level, dbox->z + i);
542 OUT_RING(ring, 0x00000000);
543 OUT_RING(ring, 0x00000000);
544 OUT_RING(ring, 0x00000000);
545 }
546
547 /*
548 * Blit command:
549 */
550 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
551 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(sx1));
552 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(sx2));
553 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(sy1));
554 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(sy2));
555
556 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
557 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dx1) | A6XX_GRAS_2D_DST_TL_Y(dy1));
558 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dx2) | A6XX_GRAS_2D_DST_BR_Y(dy2));
559
560 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
561 OUT_RING(ring, 0x3f);
562 OUT_WFI5(ring);
563
564 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
565 OUT_RING(ring, 0);
566
567 if (dfmt == FMT6_10_10_10_2_UNORM_DEST)
568 sfmt = FMT6_16_16_16_16_FLOAT;
569
570 /* This register is probably badly named... it seems that it's
571 * controlling the internal/accumulator format or something like
572 * that. It's certainly not tied to only the src format.
573 */
574 OUT_PKT4(ring, REG_A6XX_SP_2D_SRC_FORMAT, 1);
575 OUT_RING(ring, A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT(sfmt) |
576 COND(util_format_is_pure_sint(info->src.format),
577 A6XX_SP_2D_SRC_FORMAT_SINT) |
578 COND(util_format_is_pure_uint(info->src.format),
579 A6XX_SP_2D_SRC_FORMAT_UINT) |
580 COND(util_format_is_snorm(info->src.format),
581 A6XX_SP_2D_SRC_FORMAT_SINT |
582 A6XX_SP_2D_SRC_FORMAT_NORM) |
583 COND(util_format_is_unorm(info->src.format),
584 // TODO sometimes blob uses UINT+NORM but dEQP seems unhappy about that
585 // A6XX_SP_2D_SRC_FORMAT_UINT |
586 A6XX_SP_2D_SRC_FORMAT_NORM) |
587 COND(util_format_is_srgb(info->dst.format), A6XX_SP_2D_SRC_FORMAT_SRGB) |
588 A6XX_SP_2D_SRC_FORMAT_MASK(0xf));
589
590 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
591 OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
592
593 OUT_PKT7(ring, CP_BLIT, 1);
594 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
595
596 OUT_WFI5(ring);
597
598 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
599 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
600 }
601 }
602
603 void
604 fd6_clear_surface(struct fd_context *ctx,
605 struct fd_ringbuffer *ring, struct pipe_surface *psurf,
606 uint32_t width, uint32_t height, union pipe_color_union *color)
607 {
608 struct pipe_blit_info info = {};
609
610 info.dst.resource = psurf->texture;
611 info.dst.level = psurf->u.tex.level;
612 info.dst.box.x = 0;
613 info.dst.box.y = 0;
614 info.dst.box.z = psurf->u.tex.first_layer;
615 info.dst.box.width = width;
616 info.dst.box.height = height;
617 info.dst.box.depth = psurf->u.tex.last_layer + 1 - psurf->u.tex.first_layer;
618 info.dst.format = psurf->format;
619 info.src = info.dst;
620 info.mask = util_format_get_mask(psurf->format);
621 info.filter = PIPE_TEX_FILTER_NEAREST;
622 info.scissor_enable = 0;
623
624 emit_blit_or_clear_texture(ctx, ring, &info, color);
625 }
626
627 static bool
628 handle_rgba_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
629 {
630 struct fd_batch *batch;
631
632 debug_assert(!(info->mask & PIPE_MASK_ZS));
633
634 if (!can_do_blit(info))
635 return false;
636
637 batch = fd_bc_alloc_batch(&ctx->screen->batch_cache, ctx, true);
638
639 fd6_emit_restore(batch, batch->draw);
640 fd6_emit_lrz_flush(batch->draw);
641
642 fd_screen_lock(ctx->screen);
643
644 fd_batch_resource_read(batch, fd_resource(info->src.resource));
645 fd_batch_resource_write(batch, fd_resource(info->dst.resource));
646
647 fd_screen_unlock(ctx->screen);
648
649 /* Clearing last_fence must come after the batch dependency tracking
650 * (resource_read()/resource_write()), as that can trigger a flush,
651 * re-populating last_fence
652 */
653 fd_fence_ref(&ctx->last_fence, NULL);
654
655 fd_batch_set_stage(batch, FD_STAGE_BLIT);
656
657 fd_log_stream(batch, stream, util_dump_blit_info(stream, info));
658
659 emit_setup(batch);
660
661 if ((info->src.resource->target == PIPE_BUFFER) &&
662 (info->dst.resource->target == PIPE_BUFFER)) {
663 assert(fd_resource(info->src.resource)->layout.tile_mode == TILE6_LINEAR);
664 assert(fd_resource(info->dst.resource)->layout.tile_mode == TILE6_LINEAR);
665 fd_log(batch, "START BLIT (BUFFER)");
666 emit_blit_buffer(ctx, batch->draw, info);
667 fd_log(batch, "END BLIT (BUFFER)");
668 } else {
669 /* I don't *think* we need to handle blits between buffer <-> !buffer */
670 debug_assert(info->src.resource->target != PIPE_BUFFER);
671 debug_assert(info->dst.resource->target != PIPE_BUFFER);
672 fd_log(batch, "START BLIT (TEXTURE)");
673 emit_blit_or_clear_texture(ctx, batch->draw, info, NULL);
674 fd_log(batch, "END BLIT (TEXTURE)");
675 }
676
677 fd6_event_write(batch, batch->draw, PC_CCU_FLUSH_COLOR_TS, true);
678 fd6_event_write(batch, batch->draw, PC_CCU_FLUSH_DEPTH_TS, true);
679 fd6_event_write(batch, batch->draw, CACHE_FLUSH_TS, true);
680 fd6_cache_inv(batch, batch->draw);
681
682 fd_resource(info->dst.resource)->valid = true;
683 batch->needs_flush = true;
684
685 fd_batch_flush(batch);
686 fd_batch_reference(&batch, NULL);
687
688 return true;
689 }
690
691 /**
692 * Re-written z/s blits can still fail for various reasons (for example MSAA).
693 * But we want to do the fallback blit with the re-written pipe_blit_info,
694 * in particular as u_blitter cannot blit stencil. So handle the fallback
695 * ourself and never "fail".
696 */
697 static bool
698 do_rewritten_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
699 {
700 bool success = handle_rgba_blit(ctx, info);
701 if (!success)
702 success = fd_blitter_blit(ctx, info);
703 debug_assert(success); /* fallback should never fail! */
704 return success;
705 }
706
707 /**
708 * Handle depth/stencil blits either via u_blitter and/or re-writing the
709 * blit into an equivilant format that we can handle
710 */
711 static bool
712 handle_zs_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
713 {
714 struct pipe_blit_info blit = *info;
715
716 if (DEBUG_BLIT) {
717 fprintf(stderr, "---- handle_zs_blit: ");
718 util_dump_blit_info(stderr, info);
719 fprintf(stderr, "\ndst resource: ");
720 util_dump_resource(stderr, info->dst.resource);
721 fprintf(stderr, "\nsrc resource: ");
722 util_dump_resource(stderr, info->src.resource);
723 fprintf(stderr, "\n");
724 }
725
726 switch (info->dst.format) {
727 case PIPE_FORMAT_S8_UINT:
728 debug_assert(info->mask == PIPE_MASK_S);
729 blit.mask = PIPE_MASK_R;
730 blit.src.format = PIPE_FORMAT_R8_UINT;
731 blit.dst.format = PIPE_FORMAT_R8_UINT;
732 return do_rewritten_blit(ctx, &blit);
733
734 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
735 if (info->mask & PIPE_MASK_Z) {
736 blit.mask = PIPE_MASK_R;
737 blit.src.format = PIPE_FORMAT_R32_FLOAT;
738 blit.dst.format = PIPE_FORMAT_R32_FLOAT;
739 do_rewritten_blit(ctx, &blit);
740 }
741
742 if (info->mask & PIPE_MASK_S) {
743 blit.mask = PIPE_MASK_R;
744 blit.src.format = PIPE_FORMAT_R8_UINT;
745 blit.dst.format = PIPE_FORMAT_R8_UINT;
746 blit.src.resource = &fd_resource(info->src.resource)->stencil->base;
747 blit.dst.resource = &fd_resource(info->dst.resource)->stencil->base;
748 do_rewritten_blit(ctx, &blit);
749 }
750
751 return true;
752
753 case PIPE_FORMAT_Z16_UNORM:
754 blit.mask = PIPE_MASK_R;
755 blit.src.format = PIPE_FORMAT_R16_UNORM;
756 blit.dst.format = PIPE_FORMAT_R16_UNORM;
757 return do_rewritten_blit(ctx, &blit);
758
759 case PIPE_FORMAT_Z32_UNORM:
760 case PIPE_FORMAT_Z32_FLOAT:
761 debug_assert(info->mask == PIPE_MASK_Z);
762 blit.mask = PIPE_MASK_R;
763 blit.src.format = PIPE_FORMAT_R32_UINT;
764 blit.dst.format = PIPE_FORMAT_R32_UINT;
765 return do_rewritten_blit(ctx, &blit);
766
767 case PIPE_FORMAT_Z24X8_UNORM:
768 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
769 blit.mask = 0;
770 if (info->mask & PIPE_MASK_Z)
771 blit.mask |= PIPE_MASK_R | PIPE_MASK_G | PIPE_MASK_B;
772 if (info->mask & PIPE_MASK_S)
773 blit.mask |= PIPE_MASK_A;
774 blit.src.format = PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
775 blit.dst.format = PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
776 return fd_blitter_blit(ctx, &blit);
777
778 default:
779 return false;
780 }
781 }
782
783 static bool
784 handle_compressed_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
785 {
786 struct pipe_blit_info blit = *info;
787
788 if (DEBUG_BLIT) {
789 fprintf(stderr, "---- handle_compressed_blit: ");
790 util_dump_blit_info(stderr, info);
791 fprintf(stderr, "\ndst resource: ");
792 util_dump_resource(stderr, info->dst.resource);
793 fprintf(stderr, "\nsrc resource: ");
794 util_dump_resource(stderr, info->src.resource);
795 fprintf(stderr, "\n");
796 }
797
798 if (info->src.format != info->dst.format)
799 return fd_blitter_blit(ctx, info);
800
801 if (util_format_get_blocksize(info->src.format) == 8) {
802 blit.src.format = blit.dst.format = PIPE_FORMAT_R16G16B16A16_UINT;
803 } else {
804 debug_assert(util_format_get_blocksize(info->src.format) == 16);
805 blit.src.format = blit.dst.format = PIPE_FORMAT_R32G32B32A32_UINT;
806 }
807
808 int bw = util_format_get_blockwidth(info->src.format);
809 int bh = util_format_get_blockheight(info->src.format);
810
811 /* NOTE: x/y *must* be aligned to block boundary (ie. in
812 * glCompressedTexSubImage2D()) but width/height may not
813 * be:
814 */
815
816 debug_assert((blit.src.box.x % bw) == 0);
817 debug_assert((blit.src.box.y % bh) == 0);
818
819 blit.src.box.x /= bw;
820 blit.src.box.y /= bh;
821 blit.src.box.width = DIV_ROUND_UP(blit.src.box.width, bw);
822 blit.src.box.height = DIV_ROUND_UP(blit.src.box.height, bh);
823
824 debug_assert((blit.dst.box.x % bw) == 0);
825 debug_assert((blit.dst.box.y % bh) == 0);
826
827 blit.dst.box.x /= bw;
828 blit.dst.box.y /= bh;
829 blit.dst.box.width = DIV_ROUND_UP(blit.dst.box.width, bw);
830 blit.dst.box.height = DIV_ROUND_UP(blit.dst.box.height, bh);
831
832 return do_rewritten_blit(ctx, &blit);
833 }
834
835 static bool
836 fd6_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
837 {
838 if (info->mask & PIPE_MASK_ZS)
839 return handle_zs_blit(ctx, info);
840 if (util_format_is_compressed(info->src.format) ||
841 util_format_is_compressed(info->dst.format))
842 return handle_compressed_blit(ctx, info);
843
844 return handle_rgba_blit(ctx, info);
845 }
846
847 void
848 fd6_blitter_init(struct pipe_context *pctx)
849 {
850 if (fd_mesa_debug & FD_DBG_NOBLIT)
851 return;
852
853 fd_context(pctx)->blit = fd6_blit;
854 }
855
856 unsigned
857 fd6_tile_mode(const struct pipe_resource *tmpl)
858 {
859 /* if the mipmap level 0 is still too small to be tiled, then don't
860 * bother pretending:
861 */
862 if (fd_resource_level_linear(tmpl, 0))
863 return TILE6_LINEAR;
864
865 /* basically just has to be a format we can blit, so uploads/downloads
866 * via linear staging buffer works:
867 */
868 if (ok_format(tmpl->format))
869 return TILE6_3;
870
871 return TILE6_LINEAR;
872 }