2 * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
28 #include "util/u_dump.h"
29 #include "util/half_float.h"
31 #include "freedreno_blitter.h"
32 #include "freedreno_fence.h"
33 #include "freedreno_log.h"
34 #include "freedreno_resource.h"
36 #include "fd6_blitter.h"
37 #include "fd6_format.h"
39 #include "fd6_resource.h"
42 static inline enum a6xx_2d_ifmt
43 fd6_ifmt(enum a6xx_format fmt
)
51 case FMT6_8_8_8_8_UNORM
:
52 case FMT6_8_8_8_X8_UNORM
:
53 case FMT6_8_8_8_8_SNORM
:
54 case FMT6_4_4_4_4_UNORM
:
55 case FMT6_5_5_5_1_UNORM
:
56 case FMT6_5_6_5_UNORM
:
63 case FMT6_32_32_32_32_UINT
:
64 case FMT6_32_32_32_32_SINT
:
71 case FMT6_16_16_16_16_UINT
:
72 case FMT6_16_16_16_16_SINT
:
73 case FMT6_10_10_10_2_UINT
:
80 case FMT6_8_8_8_8_UINT
:
81 case FMT6_8_8_8_8_SINT
:
82 case FMT6_Z24_UNORM_S8_UINT
:
83 case FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8
:
88 case FMT6_16_16_UNORM
:
89 case FMT6_16_16_SNORM
:
90 case FMT6_16_16_16_16_UNORM
:
91 case FMT6_16_16_16_16_SNORM
:
93 case FMT6_32_32_FLOAT
:
94 case FMT6_32_32_32_32_FLOAT
:
98 case FMT6_16_16_FLOAT
:
99 case FMT6_16_16_16_16_FLOAT
:
100 case FMT6_11_11_10_FLOAT
:
101 case FMT6_10_10_10_2_UNORM_DEST
:
105 unreachable("bad format");
110 /* Make sure none of the requested dimensions extend beyond the size of the
111 * resource. Not entirely sure why this happens, but sometimes it does, and
112 * w/ 2d blt doesn't have wrap modes like a sampler, so force those cases
116 ok_dims(const struct pipe_resource
*r
, const struct pipe_box
*b
, int lvl
)
119 r
->target
== PIPE_TEXTURE_3D
? u_minify(r
->depth0
, lvl
)
122 return (b
->x
>= 0) && (b
->x
+ b
->width
<= u_minify(r
->width0
, lvl
)) &&
123 (b
->y
>= 0) && (b
->y
+ b
->height
<= u_minify(r
->height0
, lvl
)) &&
124 (b
->z
>= 0) && (b
->z
+ b
->depth
<= last_layer
);
128 ok_format(enum pipe_format pfmt
)
130 enum a6xx_format fmt
= fd6_pipe2color(pfmt
);
132 if (util_format_is_compressed(pfmt
))
136 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
137 case PIPE_FORMAT_Z24X8_UNORM
:
138 case PIPE_FORMAT_Z16_UNORM
:
139 case PIPE_FORMAT_Z32_UNORM
:
140 case PIPE_FORMAT_Z32_FLOAT
:
141 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
142 case PIPE_FORMAT_S8_UINT
:
148 if (fmt
== FMT6_NONE
)
151 if (fmt
== FMT6_10_10_10_2_UNORM_DEST
)
158 #define DEBUG_BLIT_FALLBACK 0
160 #define fail_if(cond) \
163 if (DEBUG_BLIT_FALLBACK) { \
164 fprintf(stderr, "falling back: %s for blit:\n", #cond); \
165 util_dump_blit_info(stderr, info); \
166 fprintf(stderr, "\nsrc: "); \
167 util_dump_resource(stderr, info->src.resource); \
168 fprintf(stderr, "\ndst: "); \
169 util_dump_resource(stderr, info->dst.resource); \
170 fprintf(stderr, "\n"); \
177 can_do_blit(const struct pipe_blit_info
*info
)
179 /* I think we can do scaling, but not in z dimension since that would
182 fail_if(info
->dst
.box
.depth
!= info
->src
.box
.depth
);
184 /* Fail if unsupported format: */
185 fail_if(!ok_format(info
->src
.format
));
186 fail_if(!ok_format(info
->dst
.format
));
188 debug_assert(!util_format_is_compressed(info
->src
.format
));
189 debug_assert(!util_format_is_compressed(info
->dst
.format
));
191 fail_if(!ok_dims(info
->src
.resource
, &info
->src
.box
, info
->src
.level
));
193 fail_if(!ok_dims(info
->dst
.resource
, &info
->dst
.box
, info
->dst
.level
));
195 debug_assert(info
->dst
.box
.width
>= 0);
196 debug_assert(info
->dst
.box
.height
>= 0);
197 debug_assert(info
->dst
.box
.depth
>= 0);
199 fail_if(info
->dst
.resource
->nr_samples
> 1);
201 fail_if(info
->window_rectangle_include
);
203 const struct util_format_description
*src_desc
=
204 util_format_description(info
->src
.format
);
205 const struct util_format_description
*dst_desc
=
206 util_format_description(info
->dst
.format
);
207 const int common_channels
= MIN2(src_desc
->nr_channels
, dst_desc
->nr_channels
);
209 if (info
->mask
& PIPE_MASK_RGBA
) {
210 for (int i
= 0; i
< common_channels
; i
++) {
211 fail_if(memcmp(&src_desc
->channel
[i
],
212 &dst_desc
->channel
[i
],
213 sizeof(src_desc
->channel
[0])));
217 fail_if(info
->alpha_blend
);
223 emit_setup(struct fd_batch
*batch
)
225 struct fd_ringbuffer
*ring
= batch
->draw
;
227 fd6_event_write(batch
, ring
, PC_CCU_FLUSH_COLOR_TS
, true);
228 fd6_event_write(batch
, ring
, PC_CCU_FLUSH_DEPTH_TS
, true);
229 fd6_event_write(batch
, ring
, PC_CCU_INVALIDATE_COLOR
, false);
230 fd6_event_write(batch
, ring
, PC_CCU_INVALIDATE_DEPTH
, false);
232 /* normal BLIT_OP_SCALE operation needs bypass RB_CCU_CNTL */
234 OUT_PKT4(ring
, REG_A6XX_RB_CCU_CNTL
, 1);
235 OUT_RING(ring
, fd6_context(batch
->ctx
)->magic
.RB_CCU_CNTL_bypass
);
239 blit_control(enum a6xx_format fmt
, bool is_srgb
)
241 enum a6xx_2d_ifmt ifmt
= fd6_ifmt(fmt
);
244 assert(ifmt
== R2D_UNORM8
);
245 ifmt
= R2D_UNORM8_SRGB
;
248 return A6XX_RB_2D_BLIT_CNTL_MASK(0xf) |
249 A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(fmt
) |
250 A6XX_RB_2D_BLIT_CNTL_IFMT(ifmt
);
253 /* buffers need to be handled specially since x/width can exceed the bounds
254 * supported by hw.. if necessary decompose into (potentially) two 2D blits
257 emit_blit_buffer(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
258 const struct pipe_blit_info
*info
)
260 const struct pipe_box
*sbox
= &info
->src
.box
;
261 const struct pipe_box
*dbox
= &info
->dst
.box
;
262 struct fd_resource
*src
, *dst
;
263 unsigned sshift
, dshift
;
266 fprintf(stderr
, "buffer blit: ");
267 util_dump_blit_info(stderr
, info
);
268 fprintf(stderr
, "\ndst resource: ");
269 util_dump_resource(stderr
, info
->dst
.resource
);
270 fprintf(stderr
, "\nsrc resource: ");
271 util_dump_resource(stderr
, info
->src
.resource
);
272 fprintf(stderr
, "\n");
275 src
= fd_resource(info
->src
.resource
);
276 dst
= fd_resource(info
->dst
.resource
);
278 debug_assert(src
->layout
.cpp
== 1);
279 debug_assert(dst
->layout
.cpp
== 1);
280 debug_assert(info
->src
.resource
->format
== info
->dst
.resource
->format
);
281 debug_assert((sbox
->y
== 0) && (sbox
->height
== 1));
282 debug_assert((dbox
->y
== 0) && (dbox
->height
== 1));
283 debug_assert((sbox
->z
== 0) && (sbox
->depth
== 1));
284 debug_assert((dbox
->z
== 0) && (dbox
->depth
== 1));
285 debug_assert(sbox
->width
== dbox
->width
);
286 debug_assert(info
->src
.level
== 0);
287 debug_assert(info
->dst
.level
== 0);
290 * Buffers can have dimensions bigger than max width, remap into
291 * multiple 1d blits to fit within max dimension
293 * Note that blob uses .ARRAY_PITCH=128 for blitting buffers, which
294 * seems to prevent overfetch related faults. Not quite sure what
297 * Low 6 bits of SRC/DST addresses need to be zero (ie. address
298 * aligned to 64) so we need to shift src/dst x1/x2 to make up the
299 * difference. On top of already splitting up the blit so width
302 * We perhaps could do a bit better, if src and dst are aligned but
303 * in the worst case this means we have to split the copy up into
304 * 16k (0x4000) minus 64 (0x40).
307 sshift
= sbox
->x
& 0x3f;
308 dshift
= dbox
->x
& 0x3f;
310 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
311 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE
));
313 uint32_t blit_cntl
= blit_control(FMT6_8_UNORM
, false) | 0x20000000;
314 OUT_PKT4(ring
, REG_A6XX_RB_2D_BLIT_CNTL
, 1);
315 OUT_RING(ring
, blit_cntl
);
317 OUT_PKT4(ring
, REG_A6XX_GRAS_2D_BLIT_CNTL
, 1);
318 OUT_RING(ring
, blit_cntl
);
320 for (unsigned off
= 0; off
< sbox
->width
; off
+= (0x4000 - 0x40)) {
321 unsigned soff
, doff
, w
, p
;
323 soff
= (sbox
->x
+ off
) & ~0x3f;
324 doff
= (dbox
->x
+ off
) & ~0x3f;
326 w
= MIN2(sbox
->width
- off
, (0x4000 - 0x40));
329 debug_assert((soff
+ w
) <= fd_bo_size(src
->bo
));
330 debug_assert((doff
+ w
) <= fd_bo_size(dst
->bo
));
335 OUT_PKT4(ring
, REG_A6XX_SP_PS_2D_SRC_INFO
, 10);
336 OUT_RING(ring
, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(FMT6_8_UNORM
) |
337 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(TILE6_LINEAR
) |
338 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(WZYX
) |
340 OUT_RING(ring
, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(sshift
+ w
) |
341 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(1)); /* SP_PS_2D_SRC_SIZE */
342 OUT_RELOC(ring
, src
->bo
, soff
, 0, 0); /* SP_PS_2D_SRC_LO/HI */
343 OUT_RING(ring
, A6XX_SP_PS_2D_SRC_PITCH_PITCH(p
));
345 OUT_RING(ring
, 0x00000000);
346 OUT_RING(ring
, 0x00000000);
347 OUT_RING(ring
, 0x00000000);
348 OUT_RING(ring
, 0x00000000);
349 OUT_RING(ring
, 0x00000000);
354 OUT_PKT4(ring
, REG_A6XX_RB_2D_DST_INFO
, 9);
355 OUT_RING(ring
, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(FMT6_8_UNORM
) |
356 A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
357 A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX
));
358 OUT_RELOC(ring
, dst
->bo
, doff
, 0, 0); /* RB_2D_DST_LO/HI */
359 OUT_RING(ring
, A6XX_RB_2D_DST_SIZE_PITCH(p
));
360 OUT_RING(ring
, 0x00000000);
361 OUT_RING(ring
, 0x00000000);
362 OUT_RING(ring
, 0x00000000);
363 OUT_RING(ring
, 0x00000000);
364 OUT_RING(ring
, 0x00000000);
369 OUT_PKT4(ring
, REG_A6XX_GRAS_2D_SRC_TL_X
, 4);
370 OUT_RING(ring
, A6XX_GRAS_2D_SRC_TL_X_X(sshift
));
371 OUT_RING(ring
, A6XX_GRAS_2D_SRC_BR_X_X(sshift
+ w
- 1));
372 OUT_RING(ring
, A6XX_GRAS_2D_SRC_TL_Y_Y(0));
373 OUT_RING(ring
, A6XX_GRAS_2D_SRC_BR_Y_Y(0));
375 OUT_PKT4(ring
, REG_A6XX_GRAS_2D_DST_TL
, 2);
376 OUT_RING(ring
, A6XX_GRAS_2D_DST_TL_X(dshift
) | A6XX_GRAS_2D_DST_TL_Y(0));
377 OUT_RING(ring
, A6XX_GRAS_2D_DST_BR_X(dshift
+ w
- 1) | A6XX_GRAS_2D_DST_BR_Y(0));
379 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
380 OUT_RING(ring
, 0x3f);
383 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_8C01
, 1);
386 OUT_PKT4(ring
, REG_A6XX_SP_2D_SRC_FORMAT
, 1);
387 OUT_RING(ring
, 0xf180);
389 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_8E04
, 1);
390 OUT_RING(ring
, fd6_context(ctx
)->magic
.RB_UNKNOWN_8E04_blit
);
392 OUT_PKT7(ring
, CP_BLIT
, 1);
393 OUT_RING(ring
, CP_BLIT_0_OP(BLIT_OP_SCALE
));
397 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_8E04
, 1);
398 OUT_RING(ring
, 0); /* RB_UNKNOWN_8E04 */
403 emit_blit_dst(struct fd_ringbuffer
*ring
, const struct pipe_blit_info
*info
, unsigned layer
)
405 struct fd_resource
*dst
= fd_resource(info
->dst
.resource
);
406 enum a6xx_format fmt
= fd6_pipe2color(info
->dst
.format
);
407 enum a6xx_tile_mode tile
= fd_resource_tile_mode(info
->dst
.resource
, info
->dst
.level
);
408 enum a3xx_color_swap swap
= fd6_resource_swap(dst
, info
->dst
.format
);
409 uint32_t pitch
= fd_resource_pitch(dst
, info
->dst
.level
);
410 bool ubwc_enabled
= fd_resource_ubwc_enabled(dst
, info
->dst
.level
);
411 unsigned off
= fd_resource_offset(dst
, info
->dst
.level
, layer
);
413 if (fmt
== FMT6_Z24_UNORM_S8_UINT
)
414 fmt
= FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8
;
416 OUT_PKT4(ring
, REG_A6XX_RB_2D_DST_INFO
, 9);
417 OUT_RING(ring
, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(fmt
) |
418 A6XX_RB_2D_DST_INFO_TILE_MODE(tile
) |
419 A6XX_RB_2D_DST_INFO_COLOR_SWAP(swap
) |
420 COND(util_format_is_srgb(info
->dst
.format
), A6XX_RB_2D_DST_INFO_SRGB
) |
421 COND(ubwc_enabled
, A6XX_RB_2D_DST_INFO_FLAGS
));
422 OUT_RELOC(ring
, dst
->bo
, off
, 0, 0); /* RB_2D_DST_LO/HI */
423 OUT_RING(ring
, A6XX_RB_2D_DST_SIZE_PITCH(pitch
));
424 OUT_RING(ring
, 0x00000000);
425 OUT_RING(ring
, 0x00000000);
426 OUT_RING(ring
, 0x00000000);
427 OUT_RING(ring
, 0x00000000);
428 OUT_RING(ring
, 0x00000000);
431 OUT_PKT4(ring
, REG_A6XX_RB_2D_DST_FLAGS_LO
, 6);
432 fd6_emit_flag_reference(ring
, dst
, info
->dst
.level
, layer
);
433 OUT_RING(ring
, 0x00000000);
434 OUT_RING(ring
, 0x00000000);
435 OUT_RING(ring
, 0x00000000);
440 emit_blit_src(struct fd_ringbuffer
*ring
, const struct pipe_blit_info
*info
, unsigned layer
, unsigned nr_samples
)
442 struct fd_resource
*src
= fd_resource(info
->src
.resource
);
443 enum a6xx_format sfmt
= fd6_pipe2color(info
->src
.format
);
444 enum a6xx_tile_mode stile
= fd_resource_tile_mode(info
->src
.resource
, info
->src
.level
);
445 enum a3xx_color_swap sswap
= fd6_resource_swap(src
, info
->src
.format
);
446 uint32_t pitch
= fd_resource_pitch(src
, info
->src
.level
);
447 bool subwc_enabled
= fd_resource_ubwc_enabled(src
, info
->src
.level
);
448 unsigned soff
= fd_resource_offset(src
, info
->src
.level
, layer
);
449 uint32_t width
= u_minify(src
->base
.width0
, info
->src
.level
) * nr_samples
;
450 uint32_t height
= u_minify(src
->base
.height0
, info
->src
.level
);
453 if (info
->filter
== PIPE_TEX_FILTER_LINEAR
)
454 filter
= A6XX_SP_PS_2D_SRC_INFO_FILTER
;
456 enum a3xx_msaa_samples samples
= fd_msaa_samples(src
->base
.nr_samples
);
458 if (sfmt
== FMT6_10_10_10_2_UNORM_DEST
)
459 sfmt
= FMT6_10_10_10_2_UNORM
;
461 OUT_PKT4(ring
, REG_A6XX_SP_PS_2D_SRC_INFO
, 10);
462 OUT_RING(ring
, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(sfmt
) |
463 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(stile
) |
464 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(sswap
) |
465 A6XX_SP_PS_2D_SRC_INFO_SAMPLES(samples
) |
466 COND(samples
> MSAA_ONE
&& (info
->mask
& PIPE_MASK_RGBA
),
467 A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE
) |
468 COND(subwc_enabled
, A6XX_SP_PS_2D_SRC_INFO_FLAGS
) |
469 COND(util_format_is_srgb(info
->src
.format
), A6XX_SP_PS_2D_SRC_INFO_SRGB
) |
471 OUT_RING(ring
, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(width
) |
472 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(height
)); /* SP_PS_2D_SRC_SIZE */
473 OUT_RELOC(ring
, src
->bo
, soff
, 0, 0); /* SP_PS_2D_SRC_LO/HI */
474 OUT_RING(ring
, A6XX_SP_PS_2D_SRC_PITCH_PITCH(pitch
));
476 OUT_RING(ring
, 0x00000000);
477 OUT_RING(ring
, 0x00000000);
478 OUT_RING(ring
, 0x00000000);
479 OUT_RING(ring
, 0x00000000);
480 OUT_RING(ring
, 0x00000000);
483 OUT_PKT4(ring
, REG_A6XX_SP_PS_2D_SRC_FLAGS_LO
, 6);
484 fd6_emit_flag_reference(ring
, src
, info
->src
.level
, layer
);
485 OUT_RING(ring
, 0x00000000);
486 OUT_RING(ring
, 0x00000000);
487 OUT_RING(ring
, 0x00000000);
492 emit_blit_or_clear_texture(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
493 const struct pipe_blit_info
*info
, union pipe_color_union
*color
)
495 const struct pipe_box
*sbox
= &info
->src
.box
;
496 const struct pipe_box
*dbox
= &info
->dst
.box
;
497 struct fd_resource
*dst
;
498 enum a6xx_format sfmt
, dfmt
;
499 enum a6xx_tile_mode stile
, dtile
;
500 int sx1
, sy1
, sx2
, sy2
;
501 int dx1
, dy1
, dx2
, dy2
;
504 fprintf(stderr
, "texture blit: ");
505 util_dump_blit_info(stderr
, info
);
506 fprintf(stderr
, "\ndst resource: ");
507 util_dump_resource(stderr
, info
->dst
.resource
);
508 fprintf(stderr
, "\nsrc resource: ");
509 util_dump_resource(stderr
, info
->src
.resource
);
510 fprintf(stderr
, "\n");
513 dst
= fd_resource(info
->dst
.resource
);
515 sfmt
= fd6_pipe2color(info
->src
.format
);
516 dfmt
= fd6_pipe2color(info
->dst
.format
);
518 stile
= fd_resource_tile_mode(info
->src
.resource
, info
->src
.level
);
519 dtile
= fd_resource_tile_mode(info
->dst
.resource
, info
->dst
.level
);
521 uint32_t nr_samples
= fd_resource_nr_samples(&dst
->base
);
522 sx1
= sbox
->x
* nr_samples
;
524 sx2
= (sbox
->x
+ sbox
->width
) * nr_samples
- 1;
525 sy2
= sbox
->y
+ sbox
->height
- 1;
527 dx1
= dbox
->x
* nr_samples
;
529 dx2
= (dbox
->x
+ dbox
->width
) * nr_samples
- 1;
530 dy2
= dbox
->y
+ dbox
->height
- 1;
532 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
533 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE
));
535 uint32_t blit_cntl
= blit_control(dfmt
, util_format_is_srgb(info
->dst
.format
));
538 blit_cntl
|= A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR
;
540 switch (info
->dst
.format
) {
541 case PIPE_FORMAT_Z24X8_UNORM
:
542 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
543 case PIPE_FORMAT_X24S8_UINT
: {
544 uint32_t depth_unorm24
= color
->f
[0] * ((1u << 24) - 1);
545 uint8_t stencil
= color
->ui
[1];
546 color
->ui
[0] = depth_unorm24
& 0xff;
547 color
->ui
[1] = (depth_unorm24
>> 8) & 0xff;
548 color
->ui
[2] = (depth_unorm24
>> 16) & 0xff;
549 color
->ui
[3] = stencil
;
556 OUT_PKT4(ring
, REG_A6XX_RB_2D_SRC_SOLID_C0
, 4);
558 switch (fd6_ifmt(dfmt
)) {
560 case R2D_UNORM8_SRGB
:
561 OUT_RING(ring
, float_to_ubyte(color
->f
[0]));
562 OUT_RING(ring
, float_to_ubyte(color
->f
[1]));
563 OUT_RING(ring
, float_to_ubyte(color
->f
[2]));
564 OUT_RING(ring
, float_to_ubyte(color
->f
[3]));
567 OUT_RING(ring
, _mesa_float_to_half(color
->f
[0]));
568 OUT_RING(ring
, _mesa_float_to_half(color
->f
[1]));
569 OUT_RING(ring
, _mesa_float_to_half(color
->f
[2]));
570 OUT_RING(ring
, _mesa_float_to_half(color
->f
[3]));
571 sfmt
= FMT6_16_16_16_16_FLOAT
;
578 OUT_RING(ring
, color
->ui
[0]);
579 OUT_RING(ring
, color
->ui
[1]);
580 OUT_RING(ring
, color
->ui
[2]);
581 OUT_RING(ring
, color
->ui
[3]);
587 blit_cntl
|= 0x20000000;
589 if (info
->scissor_enable
) {
590 OUT_PKT4(ring
, REG_A6XX_GRAS_RESOLVE_CNTL_1
, 2);
591 OUT_RING(ring
, A6XX_GRAS_RESOLVE_CNTL_1_X(info
->scissor
.minx
) |
592 A6XX_GRAS_RESOLVE_CNTL_1_Y(info
->scissor
.miny
));
593 OUT_RING(ring
, A6XX_GRAS_RESOLVE_CNTL_1_X(info
->scissor
.maxx
- 1) |
594 A6XX_GRAS_RESOLVE_CNTL_1_Y(info
->scissor
.maxy
- 1));
595 blit_cntl
|= A6XX_RB_2D_BLIT_CNTL_SCISSOR
;
598 OUT_PKT4(ring
, REG_A6XX_RB_2D_BLIT_CNTL
, 1);
599 OUT_RING(ring
, blit_cntl
);
601 OUT_PKT4(ring
, REG_A6XX_GRAS_2D_BLIT_CNTL
, 1);
602 OUT_RING(ring
, blit_cntl
);
604 for (unsigned i
= 0; i
< info
->dst
.box
.depth
; i
++) {
606 emit_blit_src(ring
, info
, sbox
->z
+ i
, nr_samples
);
608 emit_blit_dst(ring
, info
, dbox
->z
+ i
);
613 OUT_PKT4(ring
, REG_A6XX_GRAS_2D_SRC_TL_X
, 4);
614 OUT_RING(ring
, A6XX_GRAS_2D_SRC_TL_X_X(sx1
));
615 OUT_RING(ring
, A6XX_GRAS_2D_SRC_BR_X_X(sx2
));
616 OUT_RING(ring
, A6XX_GRAS_2D_SRC_TL_Y_Y(sy1
));
617 OUT_RING(ring
, A6XX_GRAS_2D_SRC_BR_Y_Y(sy2
));
619 OUT_PKT4(ring
, REG_A6XX_GRAS_2D_DST_TL
, 2);
620 OUT_RING(ring
, A6XX_GRAS_2D_DST_TL_X(dx1
) | A6XX_GRAS_2D_DST_TL_Y(dy1
));
621 OUT_RING(ring
, A6XX_GRAS_2D_DST_BR_X(dx2
) | A6XX_GRAS_2D_DST_BR_Y(dy2
));
623 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
624 OUT_RING(ring
, 0x3f);
627 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_8C01
, 1);
630 if (dfmt
== FMT6_10_10_10_2_UNORM_DEST
)
631 sfmt
= FMT6_16_16_16_16_FLOAT
;
633 /* This register is probably badly named... it seems that it's
634 * controlling the internal/accumulator format or something like
635 * that. It's certainly not tied to only the src format.
637 OUT_PKT4(ring
, REG_A6XX_SP_2D_SRC_FORMAT
, 1);
638 OUT_RING(ring
, A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT(sfmt
) |
639 COND(util_format_is_pure_sint(info
->src
.format
),
640 A6XX_SP_2D_SRC_FORMAT_SINT
) |
641 COND(util_format_is_pure_uint(info
->src
.format
),
642 A6XX_SP_2D_SRC_FORMAT_UINT
) |
643 COND(util_format_is_snorm(info
->src
.format
),
644 A6XX_SP_2D_SRC_FORMAT_SINT
|
645 A6XX_SP_2D_SRC_FORMAT_NORM
) |
646 COND(util_format_is_unorm(info
->src
.format
),
647 // TODO sometimes blob uses UINT+NORM but dEQP seems unhappy about that
648 // A6XX_SP_2D_SRC_FORMAT_UINT |
649 A6XX_SP_2D_SRC_FORMAT_NORM
) |
650 COND(util_format_is_srgb(info
->dst
.format
), A6XX_SP_2D_SRC_FORMAT_SRGB
) |
651 A6XX_SP_2D_SRC_FORMAT_MASK(0xf));
653 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_8E04
, 1);
654 OUT_RING(ring
, fd6_context(ctx
)->magic
.RB_UNKNOWN_8E04_blit
);
656 OUT_PKT7(ring
, CP_BLIT
, 1);
657 OUT_RING(ring
, CP_BLIT_0_OP(BLIT_OP_SCALE
));
661 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_8E04
, 1);
662 OUT_RING(ring
, 0); /* RB_UNKNOWN_8E04 */
667 fd6_clear_surface(struct fd_context
*ctx
,
668 struct fd_ringbuffer
*ring
, struct pipe_surface
*psurf
,
669 uint32_t width
, uint32_t height
, union pipe_color_union
*color
)
671 struct pipe_blit_info info
= {};
673 info
.dst
.resource
= psurf
->texture
;
674 info
.dst
.level
= psurf
->u
.tex
.level
;
677 info
.dst
.box
.z
= psurf
->u
.tex
.first_layer
;
678 info
.dst
.box
.width
= width
;
679 info
.dst
.box
.height
= height
;
680 info
.dst
.box
.depth
= psurf
->u
.tex
.last_layer
+ 1 - psurf
->u
.tex
.first_layer
;
681 info
.dst
.format
= psurf
->format
;
683 info
.mask
= util_format_get_mask(psurf
->format
);
684 info
.filter
= PIPE_TEX_FILTER_NEAREST
;
685 info
.scissor_enable
= 0;
687 emit_blit_or_clear_texture(ctx
, ring
, &info
, color
);
691 handle_rgba_blit(struct fd_context
*ctx
, const struct pipe_blit_info
*info
)
693 struct fd_batch
*batch
;
695 debug_assert(!(info
->mask
& PIPE_MASK_ZS
));
697 if (!can_do_blit(info
))
700 batch
= fd_bc_alloc_batch(&ctx
->screen
->batch_cache
, ctx
, true);
702 fd6_emit_restore(batch
, batch
->draw
);
703 fd6_emit_lrz_flush(batch
->draw
);
705 fd_screen_lock(ctx
->screen
);
707 fd_batch_resource_read(batch
, fd_resource(info
->src
.resource
));
708 fd_batch_resource_write(batch
, fd_resource(info
->dst
.resource
));
710 fd_screen_unlock(ctx
->screen
);
712 /* Clearing last_fence must come after the batch dependency tracking
713 * (resource_read()/resource_write()), as that can trigger a flush,
714 * re-populating last_fence
716 fd_fence_ref(&ctx
->last_fence
, NULL
);
718 fd_batch_set_stage(batch
, FD_STAGE_BLIT
);
720 fd_log_stream(batch
, stream
, util_dump_blit_info(stream
, info
));
724 if ((info
->src
.resource
->target
== PIPE_BUFFER
) &&
725 (info
->dst
.resource
->target
== PIPE_BUFFER
)) {
726 assert(fd_resource(info
->src
.resource
)->layout
.tile_mode
== TILE6_LINEAR
);
727 assert(fd_resource(info
->dst
.resource
)->layout
.tile_mode
== TILE6_LINEAR
);
728 fd_log(batch
, "START BLIT (BUFFER)");
729 emit_blit_buffer(ctx
, batch
->draw
, info
);
730 fd_log(batch
, "END BLIT (BUFFER)");
732 /* I don't *think* we need to handle blits between buffer <-> !buffer */
733 debug_assert(info
->src
.resource
->target
!= PIPE_BUFFER
);
734 debug_assert(info
->dst
.resource
->target
!= PIPE_BUFFER
);
735 fd_log(batch
, "START BLIT (TEXTURE)");
736 emit_blit_or_clear_texture(ctx
, batch
->draw
, info
, NULL
);
737 fd_log(batch
, "END BLIT (TEXTURE)");
740 fd6_event_write(batch
, batch
->draw
, PC_CCU_FLUSH_COLOR_TS
, true);
741 fd6_event_write(batch
, batch
->draw
, PC_CCU_FLUSH_DEPTH_TS
, true);
742 fd6_event_write(batch
, batch
->draw
, CACHE_FLUSH_TS
, true);
743 fd6_cache_inv(batch
, batch
->draw
);
745 fd_resource(info
->dst
.resource
)->valid
= true;
746 batch
->needs_flush
= true;
748 fd_batch_flush(batch
);
749 fd_batch_reference(&batch
, NULL
);
755 * Re-written z/s blits can still fail for various reasons (for example MSAA).
756 * But we want to do the fallback blit with the re-written pipe_blit_info,
757 * in particular as u_blitter cannot blit stencil. So handle the fallback
758 * ourself and never "fail".
761 do_rewritten_blit(struct fd_context
*ctx
, const struct pipe_blit_info
*info
)
763 bool success
= handle_rgba_blit(ctx
, info
);
765 success
= fd_blitter_blit(ctx
, info
);
766 debug_assert(success
); /* fallback should never fail! */
771 * Handle depth/stencil blits either via u_blitter and/or re-writing the
772 * blit into an equivilant format that we can handle
775 handle_zs_blit(struct fd_context
*ctx
, const struct pipe_blit_info
*info
)
777 struct pipe_blit_info blit
= *info
;
780 fprintf(stderr
, "---- handle_zs_blit: ");
781 util_dump_blit_info(stderr
, info
);
782 fprintf(stderr
, "\ndst resource: ");
783 util_dump_resource(stderr
, info
->dst
.resource
);
784 fprintf(stderr
, "\nsrc resource: ");
785 util_dump_resource(stderr
, info
->src
.resource
);
786 fprintf(stderr
, "\n");
789 switch (info
->dst
.format
) {
790 case PIPE_FORMAT_S8_UINT
:
791 debug_assert(info
->mask
== PIPE_MASK_S
);
792 blit
.mask
= PIPE_MASK_R
;
793 blit
.src
.format
= PIPE_FORMAT_R8_UINT
;
794 blit
.dst
.format
= PIPE_FORMAT_R8_UINT
;
795 return do_rewritten_blit(ctx
, &blit
);
797 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
798 if (info
->mask
& PIPE_MASK_Z
) {
799 blit
.mask
= PIPE_MASK_R
;
800 blit
.src
.format
= PIPE_FORMAT_R32_FLOAT
;
801 blit
.dst
.format
= PIPE_FORMAT_R32_FLOAT
;
802 do_rewritten_blit(ctx
, &blit
);
805 if (info
->mask
& PIPE_MASK_S
) {
806 blit
.mask
= PIPE_MASK_R
;
807 blit
.src
.format
= PIPE_FORMAT_R8_UINT
;
808 blit
.dst
.format
= PIPE_FORMAT_R8_UINT
;
809 blit
.src
.resource
= &fd_resource(info
->src
.resource
)->stencil
->base
;
810 blit
.dst
.resource
= &fd_resource(info
->dst
.resource
)->stencil
->base
;
811 do_rewritten_blit(ctx
, &blit
);
816 case PIPE_FORMAT_Z16_UNORM
:
817 blit
.mask
= PIPE_MASK_R
;
818 blit
.src
.format
= PIPE_FORMAT_R16_UNORM
;
819 blit
.dst
.format
= PIPE_FORMAT_R16_UNORM
;
820 return do_rewritten_blit(ctx
, &blit
);
822 case PIPE_FORMAT_Z32_UNORM
:
823 case PIPE_FORMAT_Z32_FLOAT
:
824 debug_assert(info
->mask
== PIPE_MASK_Z
);
825 blit
.mask
= PIPE_MASK_R
;
826 blit
.src
.format
= PIPE_FORMAT_R32_UINT
;
827 blit
.dst
.format
= PIPE_FORMAT_R32_UINT
;
828 return do_rewritten_blit(ctx
, &blit
);
830 case PIPE_FORMAT_Z24X8_UNORM
:
831 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
833 if (info
->mask
& PIPE_MASK_Z
)
834 blit
.mask
|= PIPE_MASK_R
| PIPE_MASK_G
| PIPE_MASK_B
;
835 if (info
->mask
& PIPE_MASK_S
)
836 blit
.mask
|= PIPE_MASK_A
;
837 blit
.src
.format
= PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8
;
838 blit
.dst
.format
= PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8
;
839 return fd_blitter_blit(ctx
, &blit
);
847 handle_compressed_blit(struct fd_context
*ctx
, const struct pipe_blit_info
*info
)
849 struct pipe_blit_info blit
= *info
;
852 fprintf(stderr
, "---- handle_compressed_blit: ");
853 util_dump_blit_info(stderr
, info
);
854 fprintf(stderr
, "\ndst resource: ");
855 util_dump_resource(stderr
, info
->dst
.resource
);
856 fprintf(stderr
, "\nsrc resource: ");
857 util_dump_resource(stderr
, info
->src
.resource
);
858 fprintf(stderr
, "\n");
861 if (info
->src
.format
!= info
->dst
.format
)
862 return fd_blitter_blit(ctx
, info
);
864 if (util_format_get_blocksize(info
->src
.format
) == 8) {
865 blit
.src
.format
= blit
.dst
.format
= PIPE_FORMAT_R16G16B16A16_UINT
;
867 debug_assert(util_format_get_blocksize(info
->src
.format
) == 16);
868 blit
.src
.format
= blit
.dst
.format
= PIPE_FORMAT_R32G32B32A32_UINT
;
871 int bw
= util_format_get_blockwidth(info
->src
.format
);
872 int bh
= util_format_get_blockheight(info
->src
.format
);
874 /* NOTE: x/y *must* be aligned to block boundary (ie. in
875 * glCompressedTexSubImage2D()) but width/height may not
879 debug_assert((blit
.src
.box
.x
% bw
) == 0);
880 debug_assert((blit
.src
.box
.y
% bh
) == 0);
882 blit
.src
.box
.x
/= bw
;
883 blit
.src
.box
.y
/= bh
;
884 blit
.src
.box
.width
= DIV_ROUND_UP(blit
.src
.box
.width
, bw
);
885 blit
.src
.box
.height
= DIV_ROUND_UP(blit
.src
.box
.height
, bh
);
887 debug_assert((blit
.dst
.box
.x
% bw
) == 0);
888 debug_assert((blit
.dst
.box
.y
% bh
) == 0);
890 blit
.dst
.box
.x
/= bw
;
891 blit
.dst
.box
.y
/= bh
;
892 blit
.dst
.box
.width
= DIV_ROUND_UP(blit
.dst
.box
.width
, bw
);
893 blit
.dst
.box
.height
= DIV_ROUND_UP(blit
.dst
.box
.height
, bh
);
895 return do_rewritten_blit(ctx
, &blit
);
899 fd6_blit(struct fd_context
*ctx
, const struct pipe_blit_info
*info
)
901 if (info
->mask
& PIPE_MASK_ZS
)
902 return handle_zs_blit(ctx
, info
);
903 if (util_format_is_compressed(info
->src
.format
) ||
904 util_format_is_compressed(info
->dst
.format
))
905 return handle_compressed_blit(ctx
, info
);
907 return handle_rgba_blit(ctx
, info
);
911 fd6_blitter_init(struct pipe_context
*pctx
)
913 if (fd_mesa_debug
& FD_DBG_NOBLIT
)
916 fd_context(pctx
)->blit
= fd6_blit
;
920 fd6_tile_mode(const struct pipe_resource
*tmpl
)
922 /* if the mipmap level 0 is still too small to be tiled, then don't
925 if (fd_resource_level_linear(tmpl
, 0))
928 /* basically just has to be a format we can blit, so uploads/downloads
929 * via linear staging buffer works:
931 if (ok_format(tmpl
->format
))