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freedreno/regs: update a6xx RB regs
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_blitter.c
1 /*
2 * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "util/u_dump.h"
29 #include "util/half_float.h"
30
31 #include "freedreno_blitter.h"
32 #include "freedreno_fence.h"
33 #include "freedreno_log.h"
34 #include "freedreno_resource.h"
35
36 #include "fd6_blitter.h"
37 #include "fd6_format.h"
38 #include "fd6_emit.h"
39 #include "fd6_resource.h"
40
41 static inline enum a6xx_2d_ifmt
42 fd6_ifmt(enum a6xx_format fmt)
43 {
44 switch (fmt) {
45 case FMT6_A8_UNORM:
46 case FMT6_8_UNORM:
47 case FMT6_8_SNORM:
48 case FMT6_8_8_UNORM:
49 case FMT6_8_8_SNORM:
50 case FMT6_8_8_8_8_UNORM:
51 case FMT6_8_8_8_X8_UNORM:
52 case FMT6_8_8_8_8_SNORM:
53 case FMT6_4_4_4_4_UNORM:
54 case FMT6_5_5_5_1_UNORM:
55 case FMT6_5_6_5_UNORM:
56 return R2D_UNORM8;
57
58 case FMT6_32_UINT:
59 case FMT6_32_SINT:
60 case FMT6_32_32_UINT:
61 case FMT6_32_32_SINT:
62 case FMT6_32_32_32_32_UINT:
63 case FMT6_32_32_32_32_SINT:
64 return R2D_INT32;
65
66 case FMT6_16_UINT:
67 case FMT6_16_SINT:
68 case FMT6_16_16_UINT:
69 case FMT6_16_16_SINT:
70 case FMT6_16_16_16_16_UINT:
71 case FMT6_16_16_16_16_SINT:
72 case FMT6_10_10_10_2_UINT:
73 return R2D_INT16;
74
75 case FMT6_8_UINT:
76 case FMT6_8_SINT:
77 case FMT6_8_8_UINT:
78 case FMT6_8_8_SINT:
79 case FMT6_8_8_8_8_UINT:
80 case FMT6_8_8_8_8_SINT:
81 case FMT6_Z24_UNORM_S8_UINT:
82 case FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8:
83 return R2D_INT8;
84
85 case FMT6_16_UNORM:
86 case FMT6_16_SNORM:
87 case FMT6_16_16_UNORM:
88 case FMT6_16_16_SNORM:
89 case FMT6_16_16_16_16_UNORM:
90 case FMT6_16_16_16_16_SNORM:
91 case FMT6_32_FLOAT:
92 case FMT6_32_32_FLOAT:
93 case FMT6_32_32_32_32_FLOAT:
94 return R2D_FLOAT32;
95
96 case FMT6_16_FLOAT:
97 case FMT6_16_16_FLOAT:
98 case FMT6_16_16_16_16_FLOAT:
99 case FMT6_11_11_10_FLOAT:
100 case FMT6_10_10_10_2_UNORM_DEST:
101 return R2D_FLOAT16;
102
103 default:
104 unreachable("bad format");
105 return 0;
106 }
107 }
108
109 /* Make sure none of the requested dimensions extend beyond the size of the
110 * resource. Not entirely sure why this happens, but sometimes it does, and
111 * w/ 2d blt doesn't have wrap modes like a sampler, so force those cases
112 * back to u_blitter
113 */
114 static bool
115 ok_dims(const struct pipe_resource *r, const struct pipe_box *b, int lvl)
116 {
117 int last_layer =
118 r->target == PIPE_TEXTURE_3D ? u_minify(r->depth0, lvl)
119 : r->array_size;
120
121 return (b->x >= 0) && (b->x + b->width <= u_minify(r->width0, lvl)) &&
122 (b->y >= 0) && (b->y + b->height <= u_minify(r->height0, lvl)) &&
123 (b->z >= 0) && (b->z + b->depth <= last_layer);
124 }
125
126 static bool
127 ok_format(enum pipe_format pfmt)
128 {
129 enum a6xx_format fmt = fd6_pipe2color(pfmt);
130
131 if (util_format_is_compressed(pfmt))
132 return true;
133
134 switch (pfmt) {
135 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
136 case PIPE_FORMAT_Z24X8_UNORM:
137 case PIPE_FORMAT_Z16_UNORM:
138 case PIPE_FORMAT_Z32_UNORM:
139 case PIPE_FORMAT_Z32_FLOAT:
140 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
141 case PIPE_FORMAT_S8_UINT:
142 return true;
143 default:
144 break;
145 }
146
147 if (fmt == FMT6_NONE)
148 return false;
149
150 return true;
151 }
152
153 #define DEBUG_BLIT 0
154 #define DEBUG_BLIT_FALLBACK 0
155
156 #define fail_if(cond) \
157 do { \
158 if (cond) { \
159 if (DEBUG_BLIT_FALLBACK) { \
160 fprintf(stderr, "falling back: %s for blit:\n", #cond); \
161 util_dump_blit_info(stderr, info); \
162 fprintf(stderr, "\nsrc: "); \
163 util_dump_resource(stderr, info->src.resource); \
164 fprintf(stderr, "\ndst: "); \
165 util_dump_resource(stderr, info->dst.resource); \
166 fprintf(stderr, "\n"); \
167 } \
168 return false; \
169 } \
170 } while (0)
171
172 static bool
173 can_do_blit(const struct pipe_blit_info *info)
174 {
175 /* I think we can do scaling, but not in z dimension since that would
176 * require blending..
177 */
178 fail_if(info->dst.box.depth != info->src.box.depth);
179
180 /* Fail if unsupported format: */
181 fail_if(!ok_format(info->src.format));
182 fail_if(!ok_format(info->dst.format));
183
184 debug_assert(!util_format_is_compressed(info->src.format));
185 debug_assert(!util_format_is_compressed(info->dst.format));
186
187 fail_if(!ok_dims(info->src.resource, &info->src.box, info->src.level));
188
189 fail_if(!ok_dims(info->dst.resource, &info->dst.box, info->dst.level));
190
191 debug_assert(info->dst.box.width >= 0);
192 debug_assert(info->dst.box.height >= 0);
193 debug_assert(info->dst.box.depth >= 0);
194
195 fail_if(info->dst.resource->nr_samples > 1);
196
197 fail_if(info->window_rectangle_include);
198
199 const struct util_format_description *src_desc =
200 util_format_description(info->src.format);
201 const struct util_format_description *dst_desc =
202 util_format_description(info->dst.format);
203 const int common_channels = MIN2(src_desc->nr_channels, dst_desc->nr_channels);
204
205 if (info->mask & PIPE_MASK_RGBA) {
206 for (int i = 0; i < common_channels; i++) {
207 fail_if(memcmp(&src_desc->channel[i],
208 &dst_desc->channel[i],
209 sizeof(src_desc->channel[0])));
210 }
211 }
212
213 fail_if(info->alpha_blend);
214
215 return true;
216 }
217
218 static void
219 emit_setup(struct fd_batch *batch)
220 {
221 struct fd_ringbuffer *ring = batch->draw;
222
223 fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
224 fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
225 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
226 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_DEPTH, false);
227
228 /* normal BLIT_OP_SCALE operation needs bypass RB_CCU_CNTL */
229 OUT_WFI5(ring);
230 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
231 OUT_RING(ring, fd6_context(batch->ctx)->magic.RB_CCU_CNTL_bypass);
232 }
233
234 static void
235 emit_blit_setup(struct fd_ringbuffer *ring,
236 enum pipe_format pfmt, bool scissor_enable, union pipe_color_union *color)
237 {
238 enum a6xx_format fmt = fd6_pipe2color(pfmt);
239 bool is_srgb = util_format_is_srgb(pfmt);
240 enum a6xx_2d_ifmt ifmt = fd6_ifmt(fmt);
241
242 OUT_PKT7(ring, CP_SET_MARKER, 1);
243 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
244
245 if (is_srgb) {
246 assert(ifmt == R2D_UNORM8);
247 ifmt = R2D_UNORM8_SRGB;
248 }
249
250 uint32_t blit_cntl = A6XX_RB_2D_BLIT_CNTL_MASK(0xf) |
251 A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(fmt) |
252 A6XX_RB_2D_BLIT_CNTL_IFMT(ifmt) |
253 COND(color, A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR) |
254 COND(scissor_enable, A6XX_RB_2D_BLIT_CNTL_SCISSOR);
255
256 OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
257 OUT_RING(ring, blit_cntl);
258
259 OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
260 OUT_RING(ring, blit_cntl);
261
262 if (fmt == FMT6_10_10_10_2_UNORM_DEST)
263 fmt = FMT6_16_16_16_16_FLOAT;
264
265 /* This register is probably badly named... it seems that it's
266 * controlling the internal/accumulator format or something like
267 * that. It's certainly not tied to only the src format.
268 */
269 OUT_PKT4(ring, REG_A6XX_SP_2D_DST_FORMAT, 1);
270 OUT_RING(ring, A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(fmt) |
271 COND(util_format_is_pure_sint(pfmt),
272 A6XX_SP_2D_DST_FORMAT_SINT) |
273 COND(util_format_is_pure_uint(pfmt),
274 A6XX_SP_2D_DST_FORMAT_UINT) |
275 COND(util_format_is_snorm(pfmt),
276 A6XX_SP_2D_DST_FORMAT_SINT |
277 A6XX_SP_2D_DST_FORMAT_NORM) |
278 COND(util_format_is_unorm(pfmt),
279 // TODO sometimes blob uses UINT+NORM but dEQP seems unhappy about that
280 // A6XX_SP_2D_DST_FORMAT_UINT |
281 A6XX_SP_2D_DST_FORMAT_NORM) |
282 COND(is_srgb, A6XX_SP_2D_DST_FORMAT_SRGB) |
283 A6XX_SP_2D_DST_FORMAT_MASK(0xf));
284
285 OUT_PKT4(ring, REG_A6XX_RB_2D_UNKNOWN_8C01, 1);
286 OUT_RING(ring, 0);
287 }
288
289 /* buffers need to be handled specially since x/width can exceed the bounds
290 * supported by hw.. if necessary decompose into (potentially) two 2D blits
291 */
292 static void
293 emit_blit_buffer(struct fd_context *ctx, struct fd_ringbuffer *ring,
294 const struct pipe_blit_info *info)
295 {
296 const struct pipe_box *sbox = &info->src.box;
297 const struct pipe_box *dbox = &info->dst.box;
298 struct fd_resource *src, *dst;
299 unsigned sshift, dshift;
300
301 if (DEBUG_BLIT) {
302 fprintf(stderr, "buffer blit: ");
303 util_dump_blit_info(stderr, info);
304 fprintf(stderr, "\ndst resource: ");
305 util_dump_resource(stderr, info->dst.resource);
306 fprintf(stderr, "\nsrc resource: ");
307 util_dump_resource(stderr, info->src.resource);
308 fprintf(stderr, "\n");
309 }
310
311 src = fd_resource(info->src.resource);
312 dst = fd_resource(info->dst.resource);
313
314 debug_assert(src->layout.cpp == 1);
315 debug_assert(dst->layout.cpp == 1);
316 debug_assert(info->src.resource->format == info->dst.resource->format);
317 debug_assert((sbox->y == 0) && (sbox->height == 1));
318 debug_assert((dbox->y == 0) && (dbox->height == 1));
319 debug_assert((sbox->z == 0) && (sbox->depth == 1));
320 debug_assert((dbox->z == 0) && (dbox->depth == 1));
321 debug_assert(sbox->width == dbox->width);
322 debug_assert(info->src.level == 0);
323 debug_assert(info->dst.level == 0);
324
325 /*
326 * Buffers can have dimensions bigger than max width, remap into
327 * multiple 1d blits to fit within max dimension
328 *
329 * Note that blob uses .ARRAY_PITCH=128 for blitting buffers, which
330 * seems to prevent overfetch related faults. Not quite sure what
331 * the deal is there.
332 *
333 * Low 6 bits of SRC/DST addresses need to be zero (ie. address
334 * aligned to 64) so we need to shift src/dst x1/x2 to make up the
335 * difference. On top of already splitting up the blit so width
336 * isn't > 16k.
337 *
338 * We perhaps could do a bit better, if src and dst are aligned but
339 * in the worst case this means we have to split the copy up into
340 * 16k (0x4000) minus 64 (0x40).
341 */
342
343 sshift = sbox->x & 0x3f;
344 dshift = dbox->x & 0x3f;
345
346 emit_blit_setup(ring, PIPE_FORMAT_R8_UNORM, false, NULL);
347
348 for (unsigned off = 0; off < sbox->width; off += (0x4000 - 0x40)) {
349 unsigned soff, doff, w, p;
350
351 soff = (sbox->x + off) & ~0x3f;
352 doff = (dbox->x + off) & ~0x3f;
353
354 w = MIN2(sbox->width - off, (0x4000 - 0x40));
355 p = align(w, 64);
356
357 debug_assert((soff + w) <= fd_bo_size(src->bo));
358 debug_assert((doff + w) <= fd_bo_size(dst->bo));
359
360 /*
361 * Emit source:
362 */
363 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 10);
364 OUT_RING(ring, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(FMT6_8_UNORM) |
365 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(TILE6_LINEAR) |
366 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(WZYX) |
367 0x500000);
368 OUT_RING(ring, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(sshift + w) |
369 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(1)); /* SP_PS_2D_SRC_SIZE */
370 OUT_RELOC(ring, src->bo, soff, 0, 0); /* SP_PS_2D_SRC_LO/HI */
371 OUT_RING(ring, A6XX_SP_PS_2D_SRC_PITCH_PITCH(p));
372
373 OUT_RING(ring, 0x00000000);
374 OUT_RING(ring, 0x00000000);
375 OUT_RING(ring, 0x00000000);
376 OUT_RING(ring, 0x00000000);
377 OUT_RING(ring, 0x00000000);
378
379 /*
380 * Emit destination:
381 */
382 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
383 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(FMT6_8_UNORM) |
384 A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
385 A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
386 OUT_RELOC(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
387 OUT_RING(ring, A6XX_RB_2D_DST_PITCH(p));
388 OUT_RING(ring, 0x00000000);
389 OUT_RING(ring, 0x00000000);
390 OUT_RING(ring, 0x00000000);
391 OUT_RING(ring, 0x00000000);
392 OUT_RING(ring, 0x00000000);
393
394 /*
395 * Blit command:
396 */
397 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
398 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X(sshift));
399 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X(sshift + w - 1));
400 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y(0));
401 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y(0));
402
403 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
404 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dshift) | A6XX_GRAS_2D_DST_TL_Y(0));
405 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dshift + w - 1) | A6XX_GRAS_2D_DST_BR_Y(0));
406
407 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
408 OUT_RING(ring, 0x3f);
409 OUT_WFI5(ring);
410
411 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
412 OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
413
414 OUT_PKT7(ring, CP_BLIT, 1);
415 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
416
417 OUT_WFI5(ring);
418
419 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
420 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
421 }
422 }
423
424 static void
425 emit_blit_dst(struct fd_ringbuffer *ring, struct pipe_resource *prsc, enum pipe_format pfmt, unsigned level, unsigned layer)
426 {
427 struct fd_resource *dst = fd_resource(prsc);
428 enum a6xx_format fmt = fd6_pipe2color(pfmt);
429 enum a6xx_tile_mode tile = fd_resource_tile_mode(prsc, level);
430 enum a3xx_color_swap swap = fd6_resource_swap(dst, pfmt);
431 uint32_t pitch = fd_resource_pitch(dst, level);
432 bool ubwc_enabled = fd_resource_ubwc_enabled(dst, level);
433 unsigned off = fd_resource_offset(dst, level, layer);
434
435 if (fmt == FMT6_Z24_UNORM_S8_UINT)
436 fmt = FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
437
438 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
439 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(fmt) |
440 A6XX_RB_2D_DST_INFO_TILE_MODE(tile) |
441 A6XX_RB_2D_DST_INFO_COLOR_SWAP(swap) |
442 COND(util_format_is_srgb(pfmt), A6XX_RB_2D_DST_INFO_SRGB) |
443 COND(ubwc_enabled, A6XX_RB_2D_DST_INFO_FLAGS));
444 OUT_RELOC(ring, dst->bo, off, 0, 0); /* RB_2D_DST_LO/HI */
445 OUT_RING(ring, A6XX_RB_2D_DST_PITCH(pitch));
446 OUT_RING(ring, 0x00000000);
447 OUT_RING(ring, 0x00000000);
448 OUT_RING(ring, 0x00000000);
449 OUT_RING(ring, 0x00000000);
450 OUT_RING(ring, 0x00000000);
451
452 if (ubwc_enabled) {
453 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_FLAGS_LO, 6);
454 fd6_emit_flag_reference(ring, dst, level, layer);
455 OUT_RING(ring, 0x00000000);
456 OUT_RING(ring, 0x00000000);
457 OUT_RING(ring, 0x00000000);
458 }
459 }
460
461 static void
462 emit_blit_src(struct fd_ringbuffer *ring, const struct pipe_blit_info *info, unsigned layer, unsigned nr_samples)
463 {
464 struct fd_resource *src = fd_resource(info->src.resource);
465 enum a6xx_format sfmt = fd6_pipe2color(info->src.format);
466 enum a6xx_tile_mode stile = fd_resource_tile_mode(info->src.resource, info->src.level);
467 enum a3xx_color_swap sswap = fd6_resource_swap(src, info->src.format);
468 uint32_t pitch = fd_resource_pitch(src, info->src.level);
469 bool subwc_enabled = fd_resource_ubwc_enabled(src, info->src.level);
470 unsigned soff = fd_resource_offset(src, info->src.level, layer);
471 uint32_t width = u_minify(src->base.width0, info->src.level) * nr_samples;
472 uint32_t height = u_minify(src->base.height0, info->src.level);
473 uint32_t filter = 0;
474
475 if (info->filter == PIPE_TEX_FILTER_LINEAR)
476 filter = A6XX_SP_PS_2D_SRC_INFO_FILTER;
477
478 enum a3xx_msaa_samples samples = fd_msaa_samples(src->base.nr_samples);
479
480 if (sfmt == FMT6_10_10_10_2_UNORM_DEST)
481 sfmt = FMT6_10_10_10_2_UNORM;
482
483 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 10);
484 OUT_RING(ring, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(sfmt) |
485 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(stile) |
486 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(sswap) |
487 A6XX_SP_PS_2D_SRC_INFO_SAMPLES(samples) |
488 COND(samples > MSAA_ONE && (info->mask & PIPE_MASK_RGBA),
489 A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE) |
490 COND(subwc_enabled, A6XX_SP_PS_2D_SRC_INFO_FLAGS) |
491 COND(util_format_is_srgb(info->src.format), A6XX_SP_PS_2D_SRC_INFO_SRGB) |
492 0x500000 | filter);
493 OUT_RING(ring, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(width) |
494 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(height)); /* SP_PS_2D_SRC_SIZE */
495 OUT_RELOC(ring, src->bo, soff, 0, 0); /* SP_PS_2D_SRC_LO/HI */
496 OUT_RING(ring, A6XX_SP_PS_2D_SRC_PITCH_PITCH(pitch));
497
498 OUT_RING(ring, 0x00000000);
499 OUT_RING(ring, 0x00000000);
500 OUT_RING(ring, 0x00000000);
501 OUT_RING(ring, 0x00000000);
502 OUT_RING(ring, 0x00000000);
503
504 if (subwc_enabled) {
505 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_FLAGS_LO, 6);
506 fd6_emit_flag_reference(ring, src, info->src.level, layer);
507 OUT_RING(ring, 0x00000000);
508 OUT_RING(ring, 0x00000000);
509 OUT_RING(ring, 0x00000000);
510 }
511 }
512
513 static void
514 emit_blit_texture(struct fd_context *ctx,
515 struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
516 {
517 const struct pipe_box *sbox = &info->src.box;
518 const struct pipe_box *dbox = &info->dst.box;
519 struct fd_resource *dst;
520 int sx1, sy1, sx2, sy2;
521 int dx1, dy1, dx2, dy2;
522
523 if (DEBUG_BLIT) {
524 fprintf(stderr, "texture blit: ");
525 util_dump_blit_info(stderr, info);
526 fprintf(stderr, "\ndst resource: ");
527 util_dump_resource(stderr, info->dst.resource);
528 fprintf(stderr, "\nsrc resource: ");
529 util_dump_resource(stderr, info->src.resource);
530 fprintf(stderr, "\n");
531 }
532
533 dst = fd_resource(info->dst.resource);
534
535 uint32_t nr_samples = fd_resource_nr_samples(&dst->base);
536
537 sx1 = sbox->x * nr_samples;
538 sy1 = sbox->y;
539 sx2 = (sbox->x + sbox->width) * nr_samples - 1;
540 sy2 = sbox->y + sbox->height - 1;
541
542 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
543 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X(sx1));
544 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X(sx2));
545 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y(sy1));
546 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y(sy2));
547
548 dx1 = dbox->x * nr_samples;
549 dy1 = dbox->y;
550 dx2 = (dbox->x + dbox->width) * nr_samples - 1;
551 dy2 = dbox->y + dbox->height - 1;
552
553 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
554 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dx1) | A6XX_GRAS_2D_DST_TL_Y(dy1));
555 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dx2) | A6XX_GRAS_2D_DST_BR_Y(dy2));
556
557 if (info->scissor_enable) {
558 OUT_PKT4(ring, REG_A6XX_GRAS_2D_RESOLVE_CNTL_1, 2);
559 OUT_RING(ring, A6XX_GRAS_2D_RESOLVE_CNTL_1_X(info->scissor.minx) |
560 A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(info->scissor.miny));
561 OUT_RING(ring, A6XX_GRAS_2D_RESOLVE_CNTL_1_X(info->scissor.maxx - 1) |
562 A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(info->scissor.maxy - 1));
563 }
564
565 emit_blit_setup(ring, info->dst.format, info->scissor_enable, NULL);
566
567 for (unsigned i = 0; i < info->dst.box.depth; i++) {
568
569 emit_blit_src(ring, info, sbox->z + i, nr_samples);
570 emit_blit_dst(ring, info->dst.resource, info->dst.format, info->dst.level, dbox->z + i);
571
572 /*
573 * Blit command:
574 */
575 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
576 OUT_RING(ring, 0x3f);
577 OUT_WFI5(ring);
578
579 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
580 OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
581
582 OUT_PKT7(ring, CP_BLIT, 1);
583 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
584
585 OUT_WFI5(ring);
586
587 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
588 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
589 }
590 }
591
592 static void
593 emit_clear_color(struct fd_ringbuffer *ring,
594 enum pipe_format pfmt, union pipe_color_union *color)
595 {
596 switch (pfmt) {
597 case PIPE_FORMAT_Z24X8_UNORM:
598 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
599 case PIPE_FORMAT_X24S8_UINT: {
600 uint32_t depth_unorm24 = color->f[0] * ((1u << 24) - 1);
601 uint8_t stencil = color->ui[1];
602 color->ui[0] = depth_unorm24 & 0xff;
603 color->ui[1] = (depth_unorm24 >> 8) & 0xff;
604 color->ui[2] = (depth_unorm24 >> 16) & 0xff;
605 color->ui[3] = stencil;
606 break;
607 }
608 default:
609 break;
610 }
611
612 OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
613 switch (fd6_ifmt(fd6_pipe2color(pfmt))) {
614 case R2D_UNORM8:
615 case R2D_UNORM8_SRGB:
616 OUT_RING(ring, float_to_ubyte(color->f[0]));
617 OUT_RING(ring, float_to_ubyte(color->f[1]));
618 OUT_RING(ring, float_to_ubyte(color->f[2]));
619 OUT_RING(ring, float_to_ubyte(color->f[3]));
620 break;
621 case R2D_FLOAT16:
622 OUT_RING(ring, _mesa_float_to_half(color->f[0]));
623 OUT_RING(ring, _mesa_float_to_half(color->f[1]));
624 OUT_RING(ring, _mesa_float_to_half(color->f[2]));
625 OUT_RING(ring, _mesa_float_to_half(color->f[3]));
626 break;
627 case R2D_FLOAT32:
628 case R2D_INT32:
629 case R2D_INT16:
630 case R2D_INT8:
631 default:
632 OUT_RING(ring, color->ui[0]);
633 OUT_RING(ring, color->ui[1]);
634 OUT_RING(ring, color->ui[2]);
635 OUT_RING(ring, color->ui[3]);
636 break;
637 }
638 }
639
640 void
641 fd6_clear_surface(struct fd_context *ctx,
642 struct fd_ringbuffer *ring, struct pipe_surface *psurf,
643 uint32_t width, uint32_t height, union pipe_color_union *color)
644 {
645 if (DEBUG_BLIT) {
646 fprintf(stderr, "surface clear:\ndst resource: ");
647 util_dump_resource(stderr, psurf->texture);
648 fprintf(stderr, "\n");
649 }
650
651 uint32_t nr_samples = fd_resource_nr_samples(psurf->texture);
652 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
653 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) | A6XX_GRAS_2D_DST_TL_Y(0));
654 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(width * nr_samples - 1) |
655 A6XX_GRAS_2D_DST_BR_Y(height - 1));
656
657 emit_clear_color(ring, psurf->format, color);
658 emit_blit_setup(ring, psurf->format, false, color);
659
660 for (unsigned i = psurf->u.tex.first_layer; i <= psurf->u.tex.last_layer; i++) {
661 emit_blit_dst(ring, psurf->texture, psurf->format, psurf->u.tex.level, i);
662
663 /*
664 * Blit command:
665 */
666 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
667 OUT_RING(ring, 0x3f);
668 OUT_WFI5(ring);
669
670 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
671 OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
672
673 OUT_PKT7(ring, CP_BLIT, 1);
674 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
675
676 OUT_WFI5(ring);
677
678 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
679 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
680 }
681 }
682
683 static bool
684 handle_rgba_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
685 {
686 struct fd_batch *batch;
687
688 debug_assert(!(info->mask & PIPE_MASK_ZS));
689
690 if (!can_do_blit(info))
691 return false;
692
693 batch = fd_bc_alloc_batch(&ctx->screen->batch_cache, ctx, true);
694
695 fd6_emit_restore(batch, batch->draw);
696 fd6_emit_lrz_flush(batch->draw);
697
698 fd_screen_lock(ctx->screen);
699
700 fd_batch_resource_read(batch, fd_resource(info->src.resource));
701 fd_batch_resource_write(batch, fd_resource(info->dst.resource));
702
703 fd_screen_unlock(ctx->screen);
704
705 /* Clearing last_fence must come after the batch dependency tracking
706 * (resource_read()/resource_write()), as that can trigger a flush,
707 * re-populating last_fence
708 */
709 fd_fence_ref(&ctx->last_fence, NULL);
710
711 fd_batch_set_stage(batch, FD_STAGE_BLIT);
712
713 fd_log_stream(batch, stream, util_dump_blit_info(stream, info));
714
715 emit_setup(batch);
716
717 if ((info->src.resource->target == PIPE_BUFFER) &&
718 (info->dst.resource->target == PIPE_BUFFER)) {
719 assert(fd_resource(info->src.resource)->layout.tile_mode == TILE6_LINEAR);
720 assert(fd_resource(info->dst.resource)->layout.tile_mode == TILE6_LINEAR);
721 fd_log(batch, "START BLIT (BUFFER)");
722 emit_blit_buffer(ctx, batch->draw, info);
723 fd_log(batch, "END BLIT (BUFFER)");
724 } else {
725 /* I don't *think* we need to handle blits between buffer <-> !buffer */
726 debug_assert(info->src.resource->target != PIPE_BUFFER);
727 debug_assert(info->dst.resource->target != PIPE_BUFFER);
728 fd_log(batch, "START BLIT (TEXTURE)");
729 emit_blit_texture(ctx, batch->draw, info);
730 fd_log(batch, "END BLIT (TEXTURE)");
731 }
732
733 fd6_event_write(batch, batch->draw, PC_CCU_FLUSH_COLOR_TS, true);
734 fd6_event_write(batch, batch->draw, PC_CCU_FLUSH_DEPTH_TS, true);
735 fd6_event_write(batch, batch->draw, CACHE_FLUSH_TS, true);
736 fd6_cache_inv(batch, batch->draw);
737
738 fd_resource(info->dst.resource)->valid = true;
739 batch->needs_flush = true;
740
741 fd_batch_flush(batch);
742 fd_batch_reference(&batch, NULL);
743
744 return true;
745 }
746
747 /**
748 * Re-written z/s blits can still fail for various reasons (for example MSAA).
749 * But we want to do the fallback blit with the re-written pipe_blit_info,
750 * in particular as u_blitter cannot blit stencil. So handle the fallback
751 * ourself and never "fail".
752 */
753 static bool
754 do_rewritten_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
755 {
756 bool success = handle_rgba_blit(ctx, info);
757 if (!success)
758 success = fd_blitter_blit(ctx, info);
759 debug_assert(success); /* fallback should never fail! */
760 return success;
761 }
762
763 /**
764 * Handle depth/stencil blits either via u_blitter and/or re-writing the
765 * blit into an equivilant format that we can handle
766 */
767 static bool
768 handle_zs_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
769 {
770 struct pipe_blit_info blit = *info;
771
772 if (DEBUG_BLIT) {
773 fprintf(stderr, "---- handle_zs_blit: ");
774 util_dump_blit_info(stderr, info);
775 fprintf(stderr, "\ndst resource: ");
776 util_dump_resource(stderr, info->dst.resource);
777 fprintf(stderr, "\nsrc resource: ");
778 util_dump_resource(stderr, info->src.resource);
779 fprintf(stderr, "\n");
780 }
781
782 switch (info->dst.format) {
783 case PIPE_FORMAT_S8_UINT:
784 debug_assert(info->mask == PIPE_MASK_S);
785 blit.mask = PIPE_MASK_R;
786 blit.src.format = PIPE_FORMAT_R8_UINT;
787 blit.dst.format = PIPE_FORMAT_R8_UINT;
788 return do_rewritten_blit(ctx, &blit);
789
790 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
791 if (info->mask & PIPE_MASK_Z) {
792 blit.mask = PIPE_MASK_R;
793 blit.src.format = PIPE_FORMAT_R32_FLOAT;
794 blit.dst.format = PIPE_FORMAT_R32_FLOAT;
795 do_rewritten_blit(ctx, &blit);
796 }
797
798 if (info->mask & PIPE_MASK_S) {
799 blit.mask = PIPE_MASK_R;
800 blit.src.format = PIPE_FORMAT_R8_UINT;
801 blit.dst.format = PIPE_FORMAT_R8_UINT;
802 blit.src.resource = &fd_resource(info->src.resource)->stencil->base;
803 blit.dst.resource = &fd_resource(info->dst.resource)->stencil->base;
804 do_rewritten_blit(ctx, &blit);
805 }
806
807 return true;
808
809 case PIPE_FORMAT_Z16_UNORM:
810 blit.mask = PIPE_MASK_R;
811 blit.src.format = PIPE_FORMAT_R16_UNORM;
812 blit.dst.format = PIPE_FORMAT_R16_UNORM;
813 return do_rewritten_blit(ctx, &blit);
814
815 case PIPE_FORMAT_Z32_UNORM:
816 case PIPE_FORMAT_Z32_FLOAT:
817 debug_assert(info->mask == PIPE_MASK_Z);
818 blit.mask = PIPE_MASK_R;
819 blit.src.format = PIPE_FORMAT_R32_UINT;
820 blit.dst.format = PIPE_FORMAT_R32_UINT;
821 return do_rewritten_blit(ctx, &blit);
822
823 case PIPE_FORMAT_Z24X8_UNORM:
824 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
825 blit.mask = 0;
826 if (info->mask & PIPE_MASK_Z)
827 blit.mask |= PIPE_MASK_R | PIPE_MASK_G | PIPE_MASK_B;
828 if (info->mask & PIPE_MASK_S)
829 blit.mask |= PIPE_MASK_A;
830 blit.src.format = PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
831 blit.dst.format = PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
832 return fd_blitter_blit(ctx, &blit);
833
834 default:
835 return false;
836 }
837 }
838
839 static bool
840 handle_compressed_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
841 {
842 struct pipe_blit_info blit = *info;
843
844 if (DEBUG_BLIT) {
845 fprintf(stderr, "---- handle_compressed_blit: ");
846 util_dump_blit_info(stderr, info);
847 fprintf(stderr, "\ndst resource: ");
848 util_dump_resource(stderr, info->dst.resource);
849 fprintf(stderr, "\nsrc resource: ");
850 util_dump_resource(stderr, info->src.resource);
851 fprintf(stderr, "\n");
852 }
853
854 if (info->src.format != info->dst.format)
855 return fd_blitter_blit(ctx, info);
856
857 if (util_format_get_blocksize(info->src.format) == 8) {
858 blit.src.format = blit.dst.format = PIPE_FORMAT_R16G16B16A16_UINT;
859 } else {
860 debug_assert(util_format_get_blocksize(info->src.format) == 16);
861 blit.src.format = blit.dst.format = PIPE_FORMAT_R32G32B32A32_UINT;
862 }
863
864 int bw = util_format_get_blockwidth(info->src.format);
865 int bh = util_format_get_blockheight(info->src.format);
866
867 /* NOTE: x/y *must* be aligned to block boundary (ie. in
868 * glCompressedTexSubImage2D()) but width/height may not
869 * be:
870 */
871
872 debug_assert((blit.src.box.x % bw) == 0);
873 debug_assert((blit.src.box.y % bh) == 0);
874
875 blit.src.box.x /= bw;
876 blit.src.box.y /= bh;
877 blit.src.box.width = DIV_ROUND_UP(blit.src.box.width, bw);
878 blit.src.box.height = DIV_ROUND_UP(blit.src.box.height, bh);
879
880 debug_assert((blit.dst.box.x % bw) == 0);
881 debug_assert((blit.dst.box.y % bh) == 0);
882
883 blit.dst.box.x /= bw;
884 blit.dst.box.y /= bh;
885 blit.dst.box.width = DIV_ROUND_UP(blit.dst.box.width, bw);
886 blit.dst.box.height = DIV_ROUND_UP(blit.dst.box.height, bh);
887
888 return do_rewritten_blit(ctx, &blit);
889 }
890
891 static bool
892 fd6_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
893 {
894 if (info->mask & PIPE_MASK_ZS)
895 return handle_zs_blit(ctx, info);
896 if (util_format_is_compressed(info->src.format) ||
897 util_format_is_compressed(info->dst.format))
898 return handle_compressed_blit(ctx, info);
899
900 return handle_rgba_blit(ctx, info);
901 }
902
903 void
904 fd6_blitter_init(struct pipe_context *pctx)
905 {
906 if (fd_mesa_debug & FD_DBG_NOBLIT)
907 return;
908
909 fd_context(pctx)->blit = fd6_blit;
910 }
911
912 unsigned
913 fd6_tile_mode(const struct pipe_resource *tmpl)
914 {
915 /* if the mipmap level 0 is still too small to be tiled, then don't
916 * bother pretending:
917 */
918 if (fd_resource_level_linear(tmpl, 0))
919 return TILE6_LINEAR;
920
921 /* basically just has to be a format we can blit, so uploads/downloads
922 * via linear staging buffer works:
923 */
924 if (ok_format(tmpl->format))
925 return TILE6_3;
926
927 return TILE6_LINEAR;
928 }