src/gallium/drivers/freedreno/a6xx/fd6_compute.c

   1 /*
   2  * Copyright (C) 2019 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "pipe/p_state.h"
  28 #include "util/u_dump.h"
  29
  30 #include "freedreno_log.h"
  31 #include "freedreno_resource.h"
  32
  33 #include "fd6_compute.h"
  34 #include "fd6_const.h"
  35 #include "fd6_context.h"
  36 #include "fd6_emit.h"
  37
  38 struct fd6_compute_stateobj {
  39         struct ir3_shader *shader;
  40 };
  41
  42
  43 static void *
  44 fd6_create_compute_state(struct pipe_context *pctx,
  45                 const struct pipe_compute_state *cso)
  46 {
  47         struct fd_context *ctx = fd_context(pctx);
  48
  49         /* req_input_mem will only be non-zero for cl kernels (ie. clover).
  50          * This isn't a perfect test because I guess it is possible (but
  51          * uncommon) for none for the kernel parameters to be a global,
  52          * but ctx->set_global_bindings() can't fail, so this is the next
  53          * best place to fail if we need a newer version of kernel driver:
  54          */
  55         if ((cso->req_input_mem > 0) &&
  56                         fd_device_version(ctx->dev) < FD_VERSION_BO_IOVA) {
  57                 return NULL;
  58         }
  59
  60         struct ir3_compiler *compiler = ctx->screen->compiler;
  61         struct fd6_compute_stateobj *so = CALLOC_STRUCT(fd6_compute_stateobj);
  62         so->shader = ir3_shader_create_compute(compiler, cso, &ctx->debug, pctx->screen);
  63         return so;
  64 }
  65
  66 static void
  67 fd6_delete_compute_state(struct pipe_context *pctx, void *hwcso)
  68 {
  69         struct fd6_compute_stateobj *so = hwcso;
  70         ir3_shader_state_delete(pctx, so->shader);
  71         free(so);
  72 }
  73
  74 /* maybe move to fd6_program? */
  75 static void
  76 cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v)
  77 {
  78         const struct ir3_info *i = &v->info;
  79         enum a3xx_threadsize thrsz = FOUR_QUADS;
  80
  81         OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
  82         OUT_RING(ring, 0xff);
  83
  84         unsigned constlen = align(v->constlen, 4);
  85         OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL, 1);
  86         OUT_RING(ring, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) |
  87                         A6XX_HLSQ_CS_CNTL_ENABLED);
  88
  89         OUT_PKT4(ring, REG_A6XX_SP_CS_CONFIG, 2);
  90         OUT_RING(ring, A6XX_SP_CS_CONFIG_ENABLED |
  91                         A6XX_SP_CS_CONFIG_NIBO(v->shader->nir->info.num_ssbos +
  92                                         v->shader->nir->info.num_images) |
  93                         A6XX_SP_CS_CONFIG_NTEX(v->num_samp) |
  94                         A6XX_SP_CS_CONFIG_NSAMP(v->num_samp));    /* SP_VS_CONFIG */
  95         OUT_RING(ring, v->instrlen);                      /* SP_VS_INSTRLEN */
  96
  97         OUT_PKT4(ring, REG_A6XX_SP_CS_CTRL_REG0, 1);
  98         OUT_RING(ring, A6XX_SP_CS_CTRL_REG0_THREADSIZE(thrsz) |
  99                         A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1) |
 100                         A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(i->max_half_reg + 1) |
 101                         COND(v->mergedregs, A6XX_SP_CS_CTRL_REG0_MERGEDREGS) |
 102                         A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v->branchstack) |
 103                         COND(v->need_pixlod, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE));
 104
 105         OUT_PKT4(ring, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
 106         OUT_RING(ring, 0x41);
 107
 108         uint32_t local_invocation_id, work_group_id;
 109         local_invocation_id = ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
 110         work_group_id = ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
 111
 112         OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL_0, 2);
 113         OUT_RING(ring, A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
 114                 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
 115                 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
 116                 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
 117         OUT_RING(ring, 0x2fc);             /* HLSQ_CS_UNKNOWN_B998 */
 118
 119         OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START_LO, 2);
 120         OUT_RELOC(ring, v->bo, 0, 0, 0);   /* SP_CS_OBJ_START_LO/HI */
 121
 122         if (v->instrlen > 0)
 123                 fd6_emit_shader(ring, v);
 124 }
 125
 126 static void
 127 fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info)
 128 {
 129         struct fd6_compute_stateobj *so = ctx->compute;
 130         struct ir3_shader_key key = {};
 131         struct ir3_shader_variant *v;
 132         struct fd_ringbuffer *ring = ctx->batch->draw;
 133         unsigned i, nglobal = 0;
 134
 135         fd6_emit_restore(ctx->batch, ring);
 136
 137         v = ir3_shader_variant(so->shader, key, false, &ctx->debug);
 138         if (!v)
 139                 return;
 140
 141         if (ctx->dirty_shader[PIPE_SHADER_COMPUTE] & FD_DIRTY_SHADER_PROG)
 142                 cs_program_emit(ring, v);
 143
 144         fd6_emit_cs_state(ctx, ring, v);
 145         fd6_emit_cs_consts(v, ring, ctx, info);
 146
 147         foreach_bit(i, ctx->global_bindings.enabled_mask)
 148                 nglobal++;
 149
 150         if (nglobal > 0) {
 151                 /* global resources don't otherwise get an OUT_RELOC(), since
 152                  * the raw ptr address is emitted in ir3_emit_cs_consts().
 153                  * So to make the kernel aware that these buffers are referenced
 154                  * by the batch, emit dummy reloc's as part of a no-op packet
 155                  * payload:
 156                  */
 157                 OUT_PKT7(ring, CP_NOP, 2 * nglobal);
 158                 foreach_bit(i, ctx->global_bindings.enabled_mask) {
 159                         struct pipe_resource *prsc = ctx->global_bindings.buf[i];
 160                         OUT_RELOC(ring, fd_resource(prsc)->bo, 0, 0, 0);
 161                 }
 162         }
 163
 164         OUT_PKT7(ring, CP_SET_MARKER, 1);
 165         OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
 166
 167         const unsigned *local_size = info->block; // v->shader->nir->info->cs.local_size;
 168         const unsigned *num_groups = info->grid;
 169         /* for some reason, mesa/st doesn't set info->work_dim, so just assume 3: */
 170         const unsigned work_dim = info->work_dim ? info->work_dim : 3;
 171         OUT_PKT4(ring, REG_A6XX_HLSQ_CS_NDRANGE_0, 7);
 172         OUT_RING(ring, A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(work_dim) |
 173                 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size[0] - 1) |
 174                 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size[1] - 1) |
 175                 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size[2] - 1));
 176         OUT_RING(ring, A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(local_size[0] * num_groups[0]));
 177         OUT_RING(ring, 0);            /* HLSQ_CS_NDRANGE_2_GLOBALOFF_X */
 178         OUT_RING(ring, A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(local_size[1] * num_groups[1]));
 179         OUT_RING(ring, 0);            /* HLSQ_CS_NDRANGE_4_GLOBALOFF_Y */
 180         OUT_RING(ring, A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(local_size[2] * num_groups[2]));
 181         OUT_RING(ring, 0);            /* HLSQ_CS_NDRANGE_6_GLOBALOFF_Z */
 182
 183         OUT_PKT4(ring, REG_A6XX_HLSQ_CS_KERNEL_GROUP_X, 3);
 184         OUT_RING(ring, 1);            /* HLSQ_CS_KERNEL_GROUP_X */
 185         OUT_RING(ring, 1);            /* HLSQ_CS_KERNEL_GROUP_Y */
 186         OUT_RING(ring, 1);            /* HLSQ_CS_KERNEL_GROUP_Z */
 187
 188         fd_log(ctx->batch, "COMPUTE: START");
 189         fd_log_stream(ctx->batch, stream, util_dump_grid_info(stream, info));
 190
 191         if (info->indirect) {
 192                 struct fd_resource *rsc = fd_resource(info->indirect);
 193
 194                 OUT_PKT7(ring, CP_EXEC_CS_INDIRECT, 4);
 195                 OUT_RING(ring, 0x00000000);
 196                 OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0);  /* ADDR_LO/HI */
 197                 OUT_RING(ring, A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
 198                                 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
 199                                 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
 200         } else {
 201                 OUT_PKT7(ring, CP_EXEC_CS, 4);
 202                 OUT_RING(ring, 0x00000000);
 203                 OUT_RING(ring, CP_EXEC_CS_1_NGROUPS_X(info->grid[0]));
 204                 OUT_RING(ring, CP_EXEC_CS_2_NGROUPS_Y(info->grid[1]));
 205                 OUT_RING(ring, CP_EXEC_CS_3_NGROUPS_Z(info->grid[2]));
 206         }
 207
 208         fd_log(ctx->batch, "COMPUTE: END");
 209         OUT_WFI5(ring);
 210         fd_log(ctx->batch, "..");
 211
 212         fd6_cache_flush(ctx->batch, ring);
 213         fd_log(ctx->batch, "..");
 214 }
 215
 216 void
 217 fd6_compute_init(struct pipe_context *pctx)
 218 {
 219         struct fd_context *ctx = fd_context(pctx);
 220         ctx->launch_grid = fd6_launch_grid;
 221         pctx->create_compute_state = fd6_create_compute_state;
 222         pctx->delete_compute_state = fd6_delete_compute_state;
 223 }