2 * Copyright (C) 2019 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_dump.h"
30 #include "freedreno_log.h"
31 #include "freedreno_resource.h"
33 #include "fd6_compute.h"
34 #include "fd6_context.h"
37 struct fd6_compute_stateobj
{
38 struct ir3_shader
*shader
;
43 fd6_create_compute_state(struct pipe_context
*pctx
,
44 const struct pipe_compute_state
*cso
)
46 struct fd_context
*ctx
= fd_context(pctx
);
48 /* req_input_mem will only be non-zero for cl kernels (ie. clover).
49 * This isn't a perfect test because I guess it is possible (but
50 * uncommon) for none for the kernel parameters to be a global,
51 * but ctx->set_global_bindings() can't fail, so this is the next
52 * best place to fail if we need a newer version of kernel driver:
54 if ((cso
->req_input_mem
> 0) &&
55 fd_device_version(ctx
->dev
) < FD_VERSION_BO_IOVA
) {
59 struct ir3_compiler
*compiler
= ctx
->screen
->compiler
;
60 struct fd6_compute_stateobj
*so
= CALLOC_STRUCT(fd6_compute_stateobj
);
61 so
->shader
= ir3_shader_create_compute(compiler
, cso
, &ctx
->debug
, pctx
->screen
);
66 fd6_delete_compute_state(struct pipe_context
*pctx
, void *hwcso
)
68 struct fd6_compute_stateobj
*so
= hwcso
;
69 ir3_shader_destroy(so
->shader
);
73 /* maybe move to fd6_program? */
75 cs_program_emit(struct fd_ringbuffer
*ring
, struct ir3_shader_variant
*v
)
77 const struct ir3_info
*i
= &v
->info
;
78 enum a3xx_threadsize thrsz
= FOUR_QUADS
;
80 OUT_PKT4(ring
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
83 unsigned constlen
= align(v
->constlen
, 4);
84 OUT_PKT4(ring
, REG_A6XX_HLSQ_CS_CNTL
, 1);
85 OUT_RING(ring
, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen
) |
86 A6XX_HLSQ_CS_CNTL_ENABLED
);
88 OUT_PKT4(ring
, REG_A6XX_SP_CS_CONFIG
, 2);
89 OUT_RING(ring
, A6XX_SP_CS_CONFIG_ENABLED
|
90 A6XX_SP_CS_CONFIG_NIBO(v
->shader
->nir
->info
.num_ssbos
+
91 v
->shader
->nir
->info
.num_images
) |
92 A6XX_SP_CS_CONFIG_NTEX(v
->num_samp
) |
93 A6XX_SP_CS_CONFIG_NSAMP(v
->num_samp
)); /* SP_VS_CONFIG */
94 OUT_RING(ring
, v
->instrlen
); /* SP_VS_INSTRLEN */
96 OUT_PKT4(ring
, REG_A6XX_SP_CS_CTRL_REG0
, 1);
97 OUT_RING(ring
, A6XX_SP_CS_CTRL_REG0_THREADSIZE(thrsz
) |
98 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i
->max_reg
+ 1) |
99 A6XX_SP_CS_CTRL_REG0_MERGEDREGS
|
100 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v
->branchstack
) |
101 COND(v
->need_pixlod
, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE
));
103 OUT_PKT4(ring
, REG_A6XX_SP_CS_UNKNOWN_A9B1
, 1);
104 OUT_RING(ring
, 0x41);
106 uint32_t local_invocation_id
, work_group_id
;
107 local_invocation_id
= ir3_find_sysval_regid(v
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
);
108 work_group_id
= ir3_find_sysval_regid(v
, SYSTEM_VALUE_WORK_GROUP_ID
);
110 OUT_PKT4(ring
, REG_A6XX_HLSQ_CS_CNTL_0
, 2);
111 OUT_RING(ring
, A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id
) |
112 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
113 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
114 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id
));
115 OUT_RING(ring
, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
117 OUT_PKT4(ring
, REG_A6XX_SP_CS_OBJ_START_LO
, 2);
118 OUT_RELOC(ring
, v
->bo
, 0, 0, 0); /* SP_CS_OBJ_START_LO/HI */
121 fd6_emit_shader(ring
, v
);
125 fd6_launch_grid(struct fd_context
*ctx
, const struct pipe_grid_info
*info
)
127 struct fd6_compute_stateobj
*so
= ctx
->compute
;
128 struct ir3_shader_key key
= {};
129 struct ir3_shader_variant
*v
;
130 struct fd_ringbuffer
*ring
= ctx
->batch
->draw
;
131 unsigned i
, nglobal
= 0;
133 fd6_emit_restore(ctx
->batch
, ring
);
135 v
= ir3_shader_variant(so
->shader
, key
, false, &ctx
->debug
);
139 if (ctx
->dirty_shader
[PIPE_SHADER_COMPUTE
] & FD_DIRTY_SHADER_PROG
)
140 cs_program_emit(ring
, v
);
142 fd6_emit_cs_state(ctx
, ring
, v
);
143 ir3_emit_cs_consts(v
, ring
, ctx
, info
);
145 foreach_bit(i
, ctx
->global_bindings
.enabled_mask
)
149 /* global resources don't otherwise get an OUT_RELOC(), since
150 * the raw ptr address is emitted in ir3_emit_cs_consts().
151 * So to make the kernel aware that these buffers are referenced
152 * by the batch, emit dummy reloc's as part of a no-op packet
155 OUT_PKT7(ring
, CP_NOP
, 2 * nglobal
);
156 foreach_bit(i
, ctx
->global_bindings
.enabled_mask
) {
157 struct pipe_resource
*prsc
= ctx
->global_bindings
.buf
[i
];
158 OUT_RELOCW(ring
, fd_resource(prsc
)->bo
, 0, 0, 0);
162 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
163 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE
));
165 const unsigned *local_size
= info
->block
; // v->shader->nir->info->cs.local_size;
166 const unsigned *num_groups
= info
->grid
;
167 /* for some reason, mesa/st doesn't set info->work_dim, so just assume 3: */
168 const unsigned work_dim
= info
->work_dim
? info
->work_dim
: 3;
169 OUT_PKT4(ring
, REG_A6XX_HLSQ_CS_NDRANGE_0
, 7);
170 OUT_RING(ring
, A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(work_dim
) |
171 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size
[0] - 1) |
172 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size
[1] - 1) |
173 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size
[2] - 1));
174 OUT_RING(ring
, A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(local_size
[0] * num_groups
[0]));
175 OUT_RING(ring
, 0); /* HLSQ_CS_NDRANGE_2_GLOBALOFF_X */
176 OUT_RING(ring
, A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(local_size
[1] * num_groups
[1]));
177 OUT_RING(ring
, 0); /* HLSQ_CS_NDRANGE_4_GLOBALOFF_Y */
178 OUT_RING(ring
, A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(local_size
[2] * num_groups
[2]));
179 OUT_RING(ring
, 0); /* HLSQ_CS_NDRANGE_6_GLOBALOFF_Z */
181 OUT_PKT4(ring
, REG_A6XX_HLSQ_CS_KERNEL_GROUP_X
, 3);
182 OUT_RING(ring
, 1); /* HLSQ_CS_KERNEL_GROUP_X */
183 OUT_RING(ring
, 1); /* HLSQ_CS_KERNEL_GROUP_Y */
184 OUT_RING(ring
, 1); /* HLSQ_CS_KERNEL_GROUP_Z */
186 fd_log(ctx
->batch
, "COMPUTE: START");
187 fd_log_stream(ctx
->batch
, stream
, util_dump_grid_info(stream
, info
));
189 if (info
->indirect
) {
190 struct fd_resource
*rsc
= fd_resource(info
->indirect
);
192 OUT_PKT7(ring
, CP_EXEC_CS_INDIRECT
, 4);
193 OUT_RING(ring
, 0x00000000);
194 OUT_RELOC(ring
, rsc
->bo
, info
->indirect_offset
, 0, 0); /* ADDR_LO/HI */
195 OUT_RING(ring
, A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size
[0] - 1) |
196 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size
[1] - 1) |
197 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size
[2] - 1));
199 OUT_PKT7(ring
, CP_EXEC_CS
, 4);
200 OUT_RING(ring
, 0x00000000);
201 OUT_RING(ring
, CP_EXEC_CS_1_NGROUPS_X(info
->grid
[0]));
202 OUT_RING(ring
, CP_EXEC_CS_2_NGROUPS_Y(info
->grid
[1]));
203 OUT_RING(ring
, CP_EXEC_CS_3_NGROUPS_Z(info
->grid
[2]));
206 fd_log(ctx
->batch
, "COMPUTE: END");
208 fd_log(ctx
->batch
, "..");
210 fd6_cache_flush(ctx
->batch
, ring
);
211 fd_log(ctx
->batch
, "..");
215 fd6_compute_init(struct pipe_context
*pctx
)
217 struct fd_context
*ctx
= fd_context(pctx
);
218 ctx
->launch_grid
= fd6_launch_grid
;
219 pctx
->create_compute_state
= fd6_create_compute_state
;
220 pctx
->delete_compute_state
= fd6_delete_compute_state
;