src/gallium/drivers/freedreno/a6xx/fd6_context.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #include "freedreno_query_acc.h"
  29
  30 #include "fd6_context.h"
  31 #include "fd6_compute.h"
  32 #include "fd6_blend.h"
  33 #include "fd6_blitter.h"
  34 #include "fd6_draw.h"
  35 #include "fd6_emit.h"
  36 #include "fd6_gmem.h"
  37 #include "fd6_image.h"
  38 #include "fd6_program.h"
  39 #include "fd6_query.h"
  40 #include "fd6_rasterizer.h"
  41 #include "fd6_texture.h"
  42 #include "fd6_zsa.h"
  43
  44 static void
  45 fd6_context_destroy(struct pipe_context *pctx)
  46 {
  47         struct fd6_context *fd6_ctx = fd6_context(fd_context(pctx));
  48
  49         u_upload_destroy(fd6_ctx->border_color_uploader);
  50
  51         fd_context_destroy(pctx);
  52
  53         if (fd6_ctx->vsc_data)
  54                 fd_bo_del(fd6_ctx->vsc_data);
  55         if (fd6_ctx->vsc_data2)
  56                 fd_bo_del(fd6_ctx->vsc_data2);
  57         fd_bo_del(fd6_ctx->control_mem);
  58
  59         fd_context_cleanup_common_vbos(&fd6_ctx->base);
  60
  61         ir3_cache_destroy(fd6_ctx->shader_cache);
  62
  63         fd6_texture_fini(pctx);
  64
  65         free(fd6_ctx);
  66 }
  67
  68 static const uint8_t primtypes[] = {
  69                 [PIPE_PRIM_POINTS]                      = DI_PT_POINTLIST,
  70                 [PIPE_PRIM_LINES]                       = DI_PT_LINELIST,
  71                 [PIPE_PRIM_LINE_STRIP]                  = DI_PT_LINESTRIP,
  72                 [PIPE_PRIM_LINE_LOOP]                   = DI_PT_LINELOOP,
  73                 [PIPE_PRIM_TRIANGLES]                   = DI_PT_TRILIST,
  74                 [PIPE_PRIM_TRIANGLE_STRIP]              = DI_PT_TRISTRIP,
  75                 [PIPE_PRIM_TRIANGLE_FAN]                = DI_PT_TRIFAN,
  76                 [PIPE_PRIM_LINES_ADJACENCY]             = DI_PT_LINE_ADJ,
  77                 [PIPE_PRIM_LINE_STRIP_ADJACENCY]        = DI_PT_LINESTRIP_ADJ,
  78                 [PIPE_PRIM_TRIANGLES_ADJACENCY]         = DI_PT_TRI_ADJ,
  79                 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY]    = DI_PT_TRISTRIP_ADJ,
  80                 [PIPE_PRIM_PATCHES]                     = DI_PT_PATCHES0,
  81                 [PIPE_PRIM_MAX]                         = DI_PT_RECTLIST,  /* internal clear blits */
  82 };
  83
  84 struct pipe_context *
  85 fd6_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
  86 {
  87         struct fd_screen *screen = fd_screen(pscreen);
  88         struct fd6_context *fd6_ctx = CALLOC_STRUCT(fd6_context);
  89         struct pipe_context *pctx;
  90
  91         if (!fd6_ctx)
  92                 return NULL;
  93
  94
  95         switch (screen->gpu_id) {
  96         case 618:
  97 /*
  98 GRAS_BIN_CONTROL:
  99 RB_BIN_CONTROL:
 100   - a618 doesn't appear to set .USE_VIZ; also bin size diffs
 101
 102 RB_CCU_CNTL:
 103   - 0x3c400004 -> 0x3e400004
 104   - 0x10000000 -> 0x08000000
 105
 106 RB_UNKNOWN_8E04:               <-- see stencil-0000.rd.gz
 107   - 0x01000000 -> 0x00100000
 108
 109 SP_UNKNOWN_A0F8:
 110 PC_UNKNOWN_9805:
 111   - 0x1 -> 0
 112  */
 113                 fd6_ctx->magic.RB_UNKNOWN_8E04_blit = 0x00100000;
 114                 fd6_ctx->magic.RB_CCU_CNTL_gmem     = 0x3e400004;
 115                 fd6_ctx->magic.RB_CCU_CNTL_bypass   = 0x08000000;
 116                 fd6_ctx->magic.PC_UNKNOWN_9805 = 0x0;
 117                 fd6_ctx->magic.SP_UNKNOWN_A0F8 = 0x0;
 118                 break;
 119         case 630:
 120                 fd6_ctx->magic.RB_UNKNOWN_8E04_blit = 0x01000000;
 121                 // NOTE: newer blob using 0x3c400004, need to revisit:
 122                 fd6_ctx->magic.RB_CCU_CNTL_gmem     = 0x7c400004;
 123                 fd6_ctx->magic.RB_CCU_CNTL_bypass   = 0x10000000;
 124                 fd6_ctx->magic.PC_UNKNOWN_9805 = 0x1;
 125                 fd6_ctx->magic.SP_UNKNOWN_A0F8 = 0x1;
 126                 break;
 127         case 640:
 128                 fd6_ctx->magic.RB_UNKNOWN_8E04_blit = 0x00100000;
 129                 fd6_ctx->magic.RB_CCU_CNTL_gmem     = 0x7c400000;
 130                 fd6_ctx->magic.RB_CCU_CNTL_bypass   = 0x10000000;
 131                 fd6_ctx->magic.PC_UNKNOWN_9805 = 0x1;
 132                 fd6_ctx->magic.SP_UNKNOWN_A0F8 = 0x1;
 133                 break;
 134         default:
 135                 unreachable("missing magic config");
 136         }
 137
 138         pctx = &fd6_ctx->base.base;
 139         pctx->screen = pscreen;
 140
 141         fd6_ctx->base.dev = fd_device_ref(screen->dev);
 142         fd6_ctx->base.screen = fd_screen(pscreen);
 143
 144         pctx->destroy = fd6_context_destroy;
 145         pctx->create_blend_state = fd6_blend_state_create;
 146         pctx->create_rasterizer_state = fd6_rasterizer_state_create;
 147         pctx->create_depth_stencil_alpha_state = fd6_zsa_state_create;
 148
 149         fd6_draw_init(pctx);
 150         fd6_compute_init(pctx);
 151         fd6_gmem_init(pctx);
 152         fd6_texture_init(pctx);
 153         fd6_prog_init(pctx);
 154         fd6_emit_init(pctx);
 155
 156         pctx = fd_context_init(&fd6_ctx->base, pscreen, primtypes, priv, flags);
 157         if (!pctx)
 158                 return NULL;
 159
 160         /* after fd_context_init() to override set_shader_images() */
 161         fd6_image_init(pctx);
 162
 163         util_blitter_set_texture_multisample(fd6_ctx->base.blitter, true);
 164
 165         /* fd_context_init overwrites delete_rasterizer_state, so set this
 166          * here. */
 167         pctx->delete_rasterizer_state = fd6_rasterizer_state_delete;
 168         pctx->delete_blend_state = fd6_blend_state_delete;
 169         pctx->delete_depth_stencil_alpha_state = fd6_depth_stencil_alpha_state_delete;
 170
 171         /* initial sizes for VSC buffers (or rather the per-pipe sizes
 172          * which is used to derive entire buffer size:
 173          */
 174         fd6_ctx->vsc_data_pitch = 0x440;
 175         fd6_ctx->vsc_data2_pitch = 0x1040;
 176
 177         fd6_ctx->control_mem = fd_bo_new(screen->dev, 0x1000,
 178                         DRM_FREEDRENO_GEM_TYPE_KMEM, "control");
 179
 180         fd_context_setup_common_vbos(&fd6_ctx->base);
 181
 182         fd6_query_context_init(pctx);
 183         fd6_blitter_init(pctx);
 184
 185         fd6_ctx->border_color_uploader = u_upload_create(pctx, 4096, 0,
 186                                                          PIPE_USAGE_STREAM, 0);
 187
 188         return pctx;
 189 }