src/gallium/drivers/freedreno/a6xx/fd6_context.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #include "freedreno_query_acc.h"
  29
  30 #include "fd6_context.h"
  31 #include "fd6_compute.h"
  32 #include "fd6_blend.h"
  33 #include "fd6_blitter.h"
  34 #include "fd6_draw.h"
  35 #include "fd6_emit.h"
  36 #include "fd6_gmem.h"
  37 #include "fd6_image.h"
  38 #include "fd6_program.h"
  39 #include "fd6_query.h"
  40 #include "fd6_rasterizer.h"
  41 #include "fd6_texture.h"
  42 #include "fd6_zsa.h"
  43
  44 static void
  45 fd6_context_destroy(struct pipe_context *pctx)
  46 {
  47         struct fd6_context *fd6_ctx = fd6_context(fd_context(pctx));
  48
  49         u_upload_destroy(fd6_ctx->border_color_uploader);
  50
  51         fd_context_destroy(pctx);
  52
  53         if (fd6_ctx->vsc_draw_strm)
  54                 fd_bo_del(fd6_ctx->vsc_draw_strm);
  55         if (fd6_ctx->vsc_prim_strm)
  56                 fd_bo_del(fd6_ctx->vsc_prim_strm);
  57         fd_bo_del(fd6_ctx->control_mem);
  58
  59         fd_context_cleanup_common_vbos(&fd6_ctx->base);
  60
  61         ir3_cache_destroy(fd6_ctx->shader_cache);
  62
  63         fd6_texture_fini(pctx);
  64
  65         free(fd6_ctx);
  66 }
  67
  68 static const uint8_t primtypes[] = {
  69                 [PIPE_PRIM_POINTS]                      = DI_PT_POINTLIST,
  70                 [PIPE_PRIM_LINES]                       = DI_PT_LINELIST,
  71                 [PIPE_PRIM_LINE_STRIP]                  = DI_PT_LINESTRIP,
  72                 [PIPE_PRIM_LINE_LOOP]                   = DI_PT_LINELOOP,
  73                 [PIPE_PRIM_TRIANGLES]                   = DI_PT_TRILIST,
  74                 [PIPE_PRIM_TRIANGLE_STRIP]              = DI_PT_TRISTRIP,
  75                 [PIPE_PRIM_TRIANGLE_FAN]                = DI_PT_TRIFAN,
  76                 [PIPE_PRIM_LINES_ADJACENCY]             = DI_PT_LINE_ADJ,
  77                 [PIPE_PRIM_LINE_STRIP_ADJACENCY]        = DI_PT_LINESTRIP_ADJ,
  78                 [PIPE_PRIM_TRIANGLES_ADJACENCY]         = DI_PT_TRI_ADJ,
  79                 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY]    = DI_PT_TRISTRIP_ADJ,
  80                 [PIPE_PRIM_PATCHES]                     = DI_PT_PATCHES0,
  81                 [PIPE_PRIM_MAX]                         = DI_PT_RECTLIST,  /* internal clear blits */
  82 };
  83
  84 static void *
  85 fd6_vertex_state_create(struct pipe_context *pctx, unsigned num_elements,
  86                 const struct pipe_vertex_element *elements)
  87 {
  88         struct fd_context *ctx = fd_context(pctx);
  89
  90         struct fd6_vertex_stateobj *state = CALLOC_STRUCT(fd6_vertex_stateobj);
  91         memcpy(state->base.pipe, elements, sizeof(*elements) * num_elements);
  92         state->base.num_elements = num_elements;
  93         state->stateobj =
  94                 fd_ringbuffer_new_object(ctx->pipe, 4 * (num_elements * 2 + 1));
  95         struct fd_ringbuffer *ring = state->stateobj;
  96
  97         OUT_PKT4(ring, REG_A6XX_VFD_DECODE(0), 2 * num_elements);
  98         for (int32_t i = 0; i < num_elements; i++) {
  99                 const struct pipe_vertex_element *elem = &elements[i];
 100                 enum pipe_format pfmt = elem->src_format;
 101                 enum a6xx_format fmt = fd6_pipe2vtx(pfmt);
 102                 bool isint = util_format_is_pure_integer(pfmt);
 103                 debug_assert(fmt != FMT6_NONE);
 104
 105                 OUT_RING(ring, A6XX_VFD_DECODE_INSTR_IDX(elem->vertex_buffer_index) |
 106                                 A6XX_VFD_DECODE_INSTR_OFFSET(elem->src_offset) |
 107                                 A6XX_VFD_DECODE_INSTR_FORMAT(fmt) |
 108                                 COND(elem->instance_divisor, A6XX_VFD_DECODE_INSTR_INSTANCED) |
 109                                 A6XX_VFD_DECODE_INSTR_SWAP(fd6_pipe2swap(pfmt)) |
 110                                 A6XX_VFD_DECODE_INSTR_UNK30 |
 111                                 COND(!isint, A6XX_VFD_DECODE_INSTR_FLOAT));
 112                 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
 113         }
 114
 115         return state;
 116 }
 117
 118 static void
 119 fd6_vertex_state_delete(struct pipe_context *pctx, void *hwcso)
 120 {
 121         struct fd6_vertex_stateobj *so = hwcso;
 122
 123         fd_ringbuffer_del(so->stateobj);
 124         FREE(hwcso);
 125 }
 126
 127 struct pipe_context *
 128 fd6_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
 129 {
 130         struct fd_screen *screen = fd_screen(pscreen);
 131         struct fd6_context *fd6_ctx = CALLOC_STRUCT(fd6_context);
 132         struct pipe_context *pctx;
 133
 134         if (!fd6_ctx)
 135                 return NULL;
 136
 137
 138         switch (screen->gpu_id) {
 139         case 618:
 140 /*
 141 GRAS_BIN_CONTROL:
 142 RB_BIN_CONTROL:
 143   - a618 doesn't appear to set .USE_VIZ; also bin size diffs
 144
 145 RB_CCU_CNTL:
 146   - 0x3c400004 -> 0x3e400004
 147   - 0x10000000 -> 0x08000000
 148
 149 RB_UNKNOWN_8E04:               <-- see stencil-0000.rd.gz
 150   - 0x01000000 -> 0x00100000
 151
 152 SP_UNKNOWN_A0F8:
 153 PC_UNKNOWN_9805:
 154   - 0x1 -> 0
 155  */
 156                 fd6_ctx->magic.RB_UNKNOWN_8E04_blit = 0x00100000;
 157                 fd6_ctx->magic.RB_CCU_CNTL_gmem = A6XX_RB_CCU_CNTL_OFFSET(0x7c000) |
 158                                                                                   A6XX_RB_CCU_CNTL_GMEM |
 159                                                                                   A6XX_RB_CCU_CNTL_UNK2;
 160                 fd6_ctx->magic.RB_CCU_CNTL_bypass = A6XX_RB_CCU_CNTL_OFFSET(0x10000);
 161                 fd6_ctx->magic.PC_UNKNOWN_9805 = 0x0;
 162                 fd6_ctx->magic.SP_UNKNOWN_A0F8 = 0x0;
 163                 break;
 164         case 630:
 165                 fd6_ctx->magic.RB_UNKNOWN_8E04_blit = 0x01000000;
 166                 fd6_ctx->magic.RB_CCU_CNTL_gmem = A6XX_RB_CCU_CNTL_OFFSET(0xf8000) |
 167                                                                                   A6XX_RB_CCU_CNTL_GMEM |
 168                                                                                   A6XX_RB_CCU_CNTL_UNK2;
 169                 fd6_ctx->magic.RB_CCU_CNTL_bypass = A6XX_RB_CCU_CNTL_OFFSET(0x20000);
 170                 fd6_ctx->magic.PC_UNKNOWN_9805 = 0x1;
 171                 fd6_ctx->magic.SP_UNKNOWN_A0F8 = 0x1;
 172                 break;
 173         case 640:
 174                 fd6_ctx->magic.RB_UNKNOWN_8E04_blit = 0x00100000;
 175                 fd6_ctx->magic.RB_CCU_CNTL_gmem = A6XX_RB_CCU_CNTL_OFFSET(0xf8000) |
 176                                                                                   A6XX_RB_CCU_CNTL_GMEM;
 177                 fd6_ctx->magic.RB_CCU_CNTL_bypass = A6XX_RB_CCU_CNTL_OFFSET(0x20000);
 178                 fd6_ctx->magic.PC_UNKNOWN_9805 = 0x1;
 179                 fd6_ctx->magic.SP_UNKNOWN_A0F8 = 0x1;
 180                 break;
 181         case 650:
 182                 fd6_ctx->magic.RB_UNKNOWN_8E04_blit = 0x04100000;
 183                 fd6_ctx->magic.RB_CCU_CNTL_gmem = A6XX_RB_CCU_CNTL_OFFSET(0x114000) |
 184                                                                                   A6XX_RB_CCU_CNTL_GMEM;
 185                 fd6_ctx->magic.RB_CCU_CNTL_bypass = A6XX_RB_CCU_CNTL_OFFSET(0x30000);
 186                 fd6_ctx->magic.PC_UNKNOWN_9805 = 0x2;
 187                 fd6_ctx->magic.SP_UNKNOWN_A0F8 = 0x2;
 188                 break;
 189         default:
 190                 unreachable("missing magic config");
 191         }
 192
 193         pctx = &fd6_ctx->base.base;
 194         pctx->screen = pscreen;
 195
 196         fd6_ctx->base.dev = fd_device_ref(screen->dev);
 197         fd6_ctx->base.screen = fd_screen(pscreen);
 198
 199         pctx->destroy = fd6_context_destroy;
 200         pctx->create_blend_state = fd6_blend_state_create;
 201         pctx->create_rasterizer_state = fd6_rasterizer_state_create;
 202         pctx->create_depth_stencil_alpha_state = fd6_zsa_state_create;
 203         pctx->create_vertex_elements_state = fd6_vertex_state_create;
 204
 205         fd6_draw_init(pctx);
 206         fd6_compute_init(pctx);
 207         fd6_gmem_init(pctx);
 208         fd6_texture_init(pctx);
 209         fd6_prog_init(pctx);
 210         fd6_emit_init(pctx);
 211         fd6_query_context_init(pctx);
 212
 213         pctx = fd_context_init(&fd6_ctx->base, pscreen, primtypes, priv, flags);
 214         if (!pctx)
 215                 return NULL;
 216
 217         /* after fd_context_init() to override set_shader_images() */
 218         fd6_image_init(pctx);
 219
 220         util_blitter_set_texture_multisample(fd6_ctx->base.blitter, true);
 221
 222         pctx->delete_vertex_elements_state = fd6_vertex_state_delete;
 223
 224         /* fd_context_init overwrites delete_rasterizer_state, so set this
 225          * here. */
 226         pctx->delete_rasterizer_state = fd6_rasterizer_state_delete;
 227         pctx->delete_blend_state = fd6_blend_state_delete;
 228         pctx->delete_depth_stencil_alpha_state = fd6_depth_stencil_alpha_state_delete;
 229
 230         /* initial sizes for VSC buffers (or rather the per-pipe sizes
 231          * which is used to derive entire buffer size:
 232          */
 233         fd6_ctx->vsc_draw_strm_pitch = 0x440;
 234         fd6_ctx->vsc_prim_strm_pitch = 0x1040;
 235
 236         fd6_ctx->control_mem = fd_bo_new(screen->dev, 0x1000,
 237                         DRM_FREEDRENO_GEM_TYPE_KMEM, "control");
 238
 239         fd_context_setup_common_vbos(&fd6_ctx->base);
 240
 241         fd6_blitter_init(pctx);
 242
 243         fd6_ctx->border_color_uploader = u_upload_create(pctx, 4096, 0,
 244                                                          PIPE_USAGE_STREAM, 0);
 245
 246         return pctx;
 247 }