2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
28 #include "freedreno_query_acc.h"
30 #include "fd6_context.h"
31 #include "fd6_compute.h"
32 #include "fd6_blend.h"
33 #include "fd6_blitter.h"
37 #include "fd6_image.h"
38 #include "fd6_program.h"
39 #include "fd6_query.h"
40 #include "fd6_rasterizer.h"
41 #include "fd6_texture.h"
45 fd6_context_destroy(struct pipe_context
*pctx
)
47 struct fd6_context
*fd6_ctx
= fd6_context(fd_context(pctx
));
49 u_upload_destroy(fd6_ctx
->border_color_uploader
);
51 fd_context_destroy(pctx
);
53 if (fd6_ctx
->vsc_draw_strm
)
54 fd_bo_del(fd6_ctx
->vsc_draw_strm
);
55 if (fd6_ctx
->vsc_prim_strm
)
56 fd_bo_del(fd6_ctx
->vsc_prim_strm
);
57 fd_bo_del(fd6_ctx
->control_mem
);
59 fd_context_cleanup_common_vbos(&fd6_ctx
->base
);
61 ir3_cache_destroy(fd6_ctx
->shader_cache
);
63 fd6_texture_fini(pctx
);
68 static const uint8_t primtypes
[] = {
69 [PIPE_PRIM_POINTS
] = DI_PT_POINTLIST
,
70 [PIPE_PRIM_LINES
] = DI_PT_LINELIST
,
71 [PIPE_PRIM_LINE_STRIP
] = DI_PT_LINESTRIP
,
72 [PIPE_PRIM_LINE_LOOP
] = DI_PT_LINELOOP
,
73 [PIPE_PRIM_TRIANGLES
] = DI_PT_TRILIST
,
74 [PIPE_PRIM_TRIANGLE_STRIP
] = DI_PT_TRISTRIP
,
75 [PIPE_PRIM_TRIANGLE_FAN
] = DI_PT_TRIFAN
,
76 [PIPE_PRIM_LINES_ADJACENCY
] = DI_PT_LINE_ADJ
,
77 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = DI_PT_LINESTRIP_ADJ
,
78 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = DI_PT_TRI_ADJ
,
79 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = DI_PT_TRISTRIP_ADJ
,
80 [PIPE_PRIM_PATCHES
] = DI_PT_PATCHES0
,
81 [PIPE_PRIM_MAX
] = DI_PT_RECTLIST
, /* internal clear blits */
85 fd6_context_create(struct pipe_screen
*pscreen
, void *priv
, unsigned flags
)
87 struct fd_screen
*screen
= fd_screen(pscreen
);
88 struct fd6_context
*fd6_ctx
= CALLOC_STRUCT(fd6_context
);
89 struct pipe_context
*pctx
;
95 switch (screen
->gpu_id
) {
100 - a618 doesn't appear to set .USE_VIZ; also bin size diffs
103 - 0x3c400004 -> 0x3e400004
104 - 0x10000000 -> 0x08000000
106 RB_UNKNOWN_8E04: <-- see stencil-0000.rd.gz
107 - 0x01000000 -> 0x00100000
113 fd6_ctx
->magic
.RB_UNKNOWN_8E04_blit
= 0x00100000;
114 fd6_ctx
->magic
.RB_CCU_CNTL_gmem
= A6XX_RB_CCU_CNTL_OFFSET(0x7c000) |
115 A6XX_RB_CCU_CNTL_GMEM
|
116 A6XX_RB_CCU_CNTL_UNK2
;
117 fd6_ctx
->magic
.RB_CCU_CNTL_bypass
= A6XX_RB_CCU_CNTL_OFFSET(0x10000);
118 fd6_ctx
->magic
.PC_UNKNOWN_9805
= 0x0;
119 fd6_ctx
->magic
.SP_UNKNOWN_A0F8
= 0x0;
122 fd6_ctx
->magic
.RB_UNKNOWN_8E04_blit
= 0x01000000;
123 fd6_ctx
->magic
.RB_CCU_CNTL_gmem
= A6XX_RB_CCU_CNTL_OFFSET(0xf8000) |
124 A6XX_RB_CCU_CNTL_GMEM
|
125 A6XX_RB_CCU_CNTL_UNK2
;
126 fd6_ctx
->magic
.RB_CCU_CNTL_bypass
= A6XX_RB_CCU_CNTL_OFFSET(0x20000);
127 fd6_ctx
->magic
.PC_UNKNOWN_9805
= 0x1;
128 fd6_ctx
->magic
.SP_UNKNOWN_A0F8
= 0x1;
131 fd6_ctx
->magic
.RB_UNKNOWN_8E04_blit
= 0x00100000;
132 fd6_ctx
->magic
.RB_CCU_CNTL_gmem
= A6XX_RB_CCU_CNTL_OFFSET(0xf8000) |
133 A6XX_RB_CCU_CNTL_GMEM
;
134 fd6_ctx
->magic
.RB_CCU_CNTL_bypass
= A6XX_RB_CCU_CNTL_OFFSET(0x20000);
135 fd6_ctx
->magic
.PC_UNKNOWN_9805
= 0x1;
136 fd6_ctx
->magic
.SP_UNKNOWN_A0F8
= 0x1;
139 fd6_ctx
->magic
.RB_UNKNOWN_8E04_blit
= 0x04100000;
140 fd6_ctx
->magic
.RB_CCU_CNTL_gmem
= A6XX_RB_CCU_CNTL_OFFSET(0x114000) |
141 A6XX_RB_CCU_CNTL_GMEM
;
142 fd6_ctx
->magic
.RB_CCU_CNTL_bypass
= A6XX_RB_CCU_CNTL_OFFSET(0x30000);
143 fd6_ctx
->magic
.PC_UNKNOWN_9805
= 0x2;
144 fd6_ctx
->magic
.SP_UNKNOWN_A0F8
= 0x2;
147 unreachable("missing magic config");
150 pctx
= &fd6_ctx
->base
.base
;
151 pctx
->screen
= pscreen
;
153 fd6_ctx
->base
.dev
= fd_device_ref(screen
->dev
);
154 fd6_ctx
->base
.screen
= fd_screen(pscreen
);
156 pctx
->destroy
= fd6_context_destroy
;
157 pctx
->create_blend_state
= fd6_blend_state_create
;
158 pctx
->create_rasterizer_state
= fd6_rasterizer_state_create
;
159 pctx
->create_depth_stencil_alpha_state
= fd6_zsa_state_create
;
162 fd6_compute_init(pctx
);
164 fd6_texture_init(pctx
);
167 fd6_query_context_init(pctx
);
169 pctx
= fd_context_init(&fd6_ctx
->base
, pscreen
, primtypes
, priv
, flags
);
173 /* after fd_context_init() to override set_shader_images() */
174 fd6_image_init(pctx
);
176 util_blitter_set_texture_multisample(fd6_ctx
->base
.blitter
, true);
178 /* fd_context_init overwrites delete_rasterizer_state, so set this
180 pctx
->delete_rasterizer_state
= fd6_rasterizer_state_delete
;
181 pctx
->delete_blend_state
= fd6_blend_state_delete
;
182 pctx
->delete_depth_stencil_alpha_state
= fd6_depth_stencil_alpha_state_delete
;
184 /* initial sizes for VSC buffers (or rather the per-pipe sizes
185 * which is used to derive entire buffer size:
187 fd6_ctx
->vsc_draw_strm_pitch
= 0x440;
188 fd6_ctx
->vsc_prim_strm_pitch
= 0x1040;
190 fd6_ctx
->control_mem
= fd_bo_new(screen
->dev
, 0x1000,
191 DRM_FREEDRENO_GEM_TYPE_KMEM
, "control");
193 fd_context_setup_common_vbos(&fd6_ctx
->base
);
195 fd6_blitter_init(pctx
);
197 fd6_ctx
->border_color_uploader
= u_upload_create(pctx
, 4096, 0,
198 PIPE_USAGE_STREAM
, 0);