src/gallium/drivers/freedreno/a6xx/fd6_draw.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #include "pipe/p_state.h"
  29 #include "util/u_string.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_prim.h"
  32
  33 #include "freedreno_state.h"
  34 #include "freedreno_resource.h"
  35
  36 #include "fd6_draw.h"
  37 #include "fd6_context.h"
  38 #include "fd6_emit.h"
  39 #include "fd6_program.h"
  40 #include "fd6_format.h"
  41 #include "fd6_vsc.h"
  42 #include "fd6_zsa.h"
  43
  44 #include "fd6_pack.h"
  45
  46 static void
  47 draw_emit_indirect(struct fd_ringbuffer *ring,
  48                                    struct CP_DRAW_INDX_OFFSET_0 *draw0,
  49                                    const struct pipe_draw_info *info,
  50                                    unsigned index_offset)
  51 {
  52         struct fd_resource *ind = fd_resource(info->indirect->buffer);
  53
  54         if (info->index_size) {
  55                 struct pipe_resource *idx = info->index.resource;
  56                 unsigned max_indicies = (idx->width0 - index_offset) / info->index_size;
  57
  58                 OUT_PKT(ring, CP_DRAW_INDX_INDIRECT,
  59                                 pack_CP_DRAW_INDX_OFFSET_0(*draw0),
  60                                 A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE(
  61                                                 fd_resource(idx)->bo, index_offset),
  62                                 A5XX_CP_DRAW_INDX_INDIRECT_3(.max_indices = max_indicies),
  63                                 A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT(
  64                                                 ind->bo, info->indirect->offset)
  65                         );
  66         } else {
  67                 OUT_PKT(ring, CP_DRAW_INDIRECT,
  68                                 pack_CP_DRAW_INDX_OFFSET_0(*draw0),
  69                                 A5XX_CP_DRAW_INDIRECT_INDIRECT(
  70                                                 ind->bo, info->indirect->offset)
  71                         );
  72         }
  73 }
  74
  75 static void
  76 draw_emit(struct fd_ringbuffer *ring,
  77                   struct CP_DRAW_INDX_OFFSET_0 *draw0,
  78                   const struct pipe_draw_info *info,
  79                   unsigned index_offset)
  80 {
  81         if (info->index_size) {
  82                 assert(!info->has_user_indices);
  83
  84                 struct pipe_resource *idx_buffer = info->index.resource;
  85                 uint32_t idx_size = info->index_size * info->count;
  86                 uint32_t idx_offset = index_offset + info->start * info->index_size;
  87
  88                 OUT_PKT(ring, CP_DRAW_INDX_OFFSET,
  89                                 pack_CP_DRAW_INDX_OFFSET_0(*draw0),
  90                                 CP_DRAW_INDX_OFFSET_1(.num_instances = info->instance_count),
  91                                 CP_DRAW_INDX_OFFSET_2(.num_indices = info->count),
  92                                 CP_DRAW_INDX_OFFSET_3(0),
  93                                 A5XX_CP_DRAW_INDX_OFFSET_INDX_BASE(
  94                                                 fd_resource(idx_buffer)->bo, idx_offset),
  95                                 A5XX_CP_DRAW_INDX_OFFSET_6(.indx_size = idx_size)
  96                         );
  97         } else {
  98                 OUT_PKT(ring, CP_DRAW_INDX_OFFSET,
  99                                 pack_CP_DRAW_INDX_OFFSET_0(*draw0),
 100                                 CP_DRAW_INDX_OFFSET_1(.num_instances = info->instance_count),
 101                                 CP_DRAW_INDX_OFFSET_2(.num_indices = info->count)
 102                         );
 103         }
 104 }
 105
 106 /* fixup dirty shader state in case some "unrelated" (from the state-
 107  * tracker's perspective) state change causes us to switch to a
 108  * different variant.
 109  */
 110 static void
 111 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
 112 {
 113         struct fd6_context *fd6_ctx = fd6_context(ctx);
 114         struct ir3_shader_key *last_key = &fd6_ctx->last_key;
 115
 116         if (!ir3_shader_key_equal(last_key, key)) {
 117                 if (ir3_shader_key_changes_fs(last_key, key)) {
 118                         ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG;
 119                         ctx->dirty |= FD_DIRTY_PROG;
 120                 }
 121
 122                 if (ir3_shader_key_changes_vs(last_key, key)) {
 123                         ctx->dirty_shader[PIPE_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG;
 124                         ctx->dirty |= FD_DIRTY_PROG;
 125                 }
 126
 127                 fd6_ctx->last_key = *key;
 128         }
 129 }
 130
 131 static void
 132 fixup_draw_state(struct fd_context *ctx, struct fd6_emit *emit)
 133 {
 134         if (ctx->last.dirty ||
 135                         (ctx->last.primitive_restart != emit->primitive_restart)) {
 136                 /* rasterizer state is effected by primitive-restart: */
 137                 ctx->dirty |= FD_DIRTY_RASTERIZER;
 138                 ctx->last.primitive_restart = emit->primitive_restart;
 139         }
 140 }
 141
 142 static bool
 143 fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
 144              unsigned index_offset)
 145 {
 146         struct fd6_context *fd6_ctx = fd6_context(ctx);
 147         struct fd6_emit emit = {
 148                 .ctx = ctx,
 149                 .vtx  = &ctx->vtx,
 150                 .info = info,
 151                 .key = {
 152                         .vs = ctx->prog.vs,
 153                         .gs = ctx->prog.gs,
 154                         .fs = ctx->prog.fs,
 155                         .key = {
 156                                 .color_two_side = ctx->rasterizer->light_twoside,
 157                                 .vclamp_color = ctx->rasterizer->clamp_vertex_color,
 158                                 .fclamp_color = ctx->rasterizer->clamp_fragment_color,
 159                                 .rasterflat = ctx->rasterizer->flatshade,
 160                                 .ucp_enables = ctx->rasterizer->clip_plane_enable,
 161                                 .has_per_samp = (fd6_ctx->fsaturate || fd6_ctx->vsaturate),
 162                                 .vsaturate_s = fd6_ctx->vsaturate_s,
 163                                 .vsaturate_t = fd6_ctx->vsaturate_t,
 164                                 .vsaturate_r = fd6_ctx->vsaturate_r,
 165                                 .fsaturate_s = fd6_ctx->fsaturate_s,
 166                                 .fsaturate_t = fd6_ctx->fsaturate_t,
 167                                 .fsaturate_r = fd6_ctx->fsaturate_r,
 168                                 .vsamples = ctx->tex[PIPE_SHADER_VERTEX].samples,
 169                                 .fsamples = ctx->tex[PIPE_SHADER_FRAGMENT].samples,
 170                                 .sample_shading = (ctx->min_samples > 1),
 171                                 .msaa = (ctx->framebuffer.samples > 1),
 172                         },
 173                 },
 174                 .rasterflat = ctx->rasterizer->flatshade,
 175                 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 176                 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 177                 .primitive_restart = info->primitive_restart && info->index_size,
 178         };
 179
 180         if (info->mode == PIPE_PRIM_PATCHES) {
 181                 emit.key.hs = ctx->prog.hs;
 182                 emit.key.ds = ctx->prog.ds;
 183
 184                 shader_info *ds_info = &emit.key.ds->nir->info;
 185                 emit.key.key.tessellation = ir3_tess_mode(ds_info->tess.primitive_mode);
 186         }
 187
 188         if (emit.key.gs)
 189                 emit.key.key.has_gs = true;
 190
 191         if (!(emit.key.hs || emit.key.ds || emit.key.gs || info->indirect))
 192                 fd6_vsc_update_sizes(ctx->batch, info);
 193
 194         fixup_shader_state(ctx, &emit.key.key);
 195
 196         if (!(ctx->dirty & FD_DIRTY_PROG)) {
 197                 emit.prog = fd6_ctx->prog;
 198         } else {
 199                 fd6_ctx->prog = fd6_emit_get_prog(&emit);
 200         }
 201
 202         /* bail if compile failed: */
 203         if (!fd6_ctx->prog)
 204                 return NULL;
 205
 206         emit.dirty = ctx->dirty;      /* *after* fixup_shader_state() */
 207         emit.bs = fd6_emit_get_prog(&emit)->bs;
 208         emit.vs = fd6_emit_get_prog(&emit)->vs;
 209         emit.hs = fd6_emit_get_prog(&emit)->hs;
 210         emit.ds = fd6_emit_get_prog(&emit)->ds;
 211         emit.gs = fd6_emit_get_prog(&emit)->gs;
 212         emit.fs = fd6_emit_get_prog(&emit)->fs;
 213
 214         ctx->stats.vs_regs += ir3_shader_halfregs(emit.vs);
 215         ctx->stats.hs_regs += COND(emit.hs, ir3_shader_halfregs(emit.hs));
 216         ctx->stats.ds_regs += COND(emit.ds, ir3_shader_halfregs(emit.ds));
 217         ctx->stats.gs_regs += COND(emit.gs, ir3_shader_halfregs(emit.gs));
 218         ctx->stats.fs_regs += ir3_shader_halfregs(emit.fs);
 219
 220         /* figure out whether we need to disable LRZ write for binning
 221          * pass using draw pass's fs:
 222          */
 223         emit.no_lrz_write = emit.fs->writes_pos || emit.fs->no_earlyz;
 224
 225         struct fd_ringbuffer *ring = ctx->batch->draw;
 226
 227         struct CP_DRAW_INDX_OFFSET_0 draw0 = {
 228                         .prim_type = ctx->primtypes[info->mode],
 229                         .vis_cull  = USE_VISIBILITY,
 230                         .gs_enable = !!emit.key.gs,
 231         };
 232
 233         if (info->index_size) {
 234                 draw0.source_select = DI_SRC_SEL_DMA;
 235                 draw0.index_size = fd4_size2indextype(info->index_size);
 236         } else {
 237                 draw0.source_select = DI_SRC_SEL_AUTO_INDEX;
 238         }
 239
 240         if (info->mode == PIPE_PRIM_PATCHES) {
 241                 shader_info *ds_info = &emit.ds->shader->nir->info;
 242                 uint32_t factor_stride;
 243
 244                 switch (ds_info->tess.primitive_mode) {
 245                 case GL_ISOLINES:
 246                         draw0.patch_type = TESS_ISOLINES;
 247                         factor_stride = 12;
 248                         break;
 249                 case GL_TRIANGLES:
 250                         draw0.patch_type = TESS_TRIANGLES;
 251                         factor_stride = 20;
 252                         break;
 253                 case GL_QUADS:
 254                         draw0.patch_type = TESS_QUADS;
 255                         factor_stride = 28;
 256                         break;
 257                 default:
 258                         unreachable("bad tessmode");
 259                 }
 260
 261                 draw0.prim_type = DI_PT_PATCHES0 + info->vertices_per_patch;
 262                 draw0.tess_enable = true;
 263
 264                 ctx->batch->tessellation = true;
 265                 ctx->batch->tessparam_size = MAX2(ctx->batch->tessparam_size,
 266                                 emit.hs->shader->output_size * 4 * info->count);
 267                 ctx->batch->tessfactor_size = MAX2(ctx->batch->tessfactor_size,
 268                                 factor_stride * info->count);
 269
 270                 if (!ctx->batch->tess_addrs_constobj) {
 271                         /* Reserve space for the bo address - we'll write them later in
 272                          * setup_tess_buffers().  We need 2 bo address, but indirect
 273                          * constant upload needs at least 4 vec4s.
 274                          */
 275                         unsigned size = 4 * 16;
 276
 277                         ctx->batch->tess_addrs_constobj = fd_submit_new_ringbuffer(
 278                                 ctx->batch->submit, size, FD_RINGBUFFER_STREAMING);
 279
 280                         ctx->batch->tess_addrs_constobj->cur += size;
 281                 }
 282         }
 283
 284         uint32_t index_start = info->index_size ? info->index_bias : info->start;
 285         if (ctx->last.dirty || (ctx->last.index_start != index_start)) {
 286                 OUT_PKT4(ring, REG_A6XX_VFD_INDEX_OFFSET, 1);
 287                 OUT_RING(ring, index_start); /* VFD_INDEX_OFFSET */
 288                 ctx->last.index_start = index_start;
 289         }
 290
 291         if (ctx->last.dirty || (ctx->last.instance_start != info->start_instance)) {
 292                 OUT_PKT4(ring, REG_A6XX_VFD_INSTANCE_START_OFFSET, 1);
 293                 OUT_RING(ring, info->start_instance); /* VFD_INSTANCE_START_OFFSET */
 294                 ctx->last.instance_start = info->start_instance;
 295         }
 296
 297         uint32_t restart_index = info->primitive_restart ? info->restart_index : 0xffffffff;
 298         if (ctx->last.dirty || (ctx->last.restart_index != restart_index)) {
 299                 OUT_PKT4(ring, REG_A6XX_PC_RESTART_INDEX, 1);
 300                 OUT_RING(ring, restart_index); /* PC_RESTART_INDEX */
 301                 ctx->last.restart_index = restart_index;
 302         }
 303
 304         fixup_draw_state(ctx, &emit);
 305
 306         fd6_emit_state(ring, &emit);
 307
 308         /* for debug after a lock up, write a unique counter value
 309          * to scratch7 for each draw, to make it easier to match up
 310          * register dumps to cmdstream.  The combination of IB
 311          * (scratch6) and DRAW is enough to "triangulate" the
 312          * particular draw that caused lockup.
 313          */
 314         emit_marker6(ring, 7);
 315
 316         if (info->indirect) {
 317                 draw_emit_indirect(ring, &draw0, info, index_offset);
 318         } else {
 319                 draw_emit(ring, &draw0, info, index_offset);
 320         }
 321
 322         emit_marker6(ring, 7);
 323         fd_reset_wfi(ctx->batch);
 324
 325         if (emit.streamout_mask) {
 326                 struct fd_ringbuffer *ring = ctx->batch->draw;
 327
 328                 for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
 329                         if (emit.streamout_mask & (1 << i)) {
 330                                 fd6_event_write(ctx->batch, ring, FLUSH_SO_0 + i, false);
 331                         }
 332                 }
 333         }
 334
 335         fd_context_all_clean(ctx);
 336
 337         return true;
 338 }
 339
 340 static void
 341 fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
 342 {
 343         struct fd_ringbuffer *ring;
 344         struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
 345
 346         if (batch->lrz_clear) {
 347                 fd_ringbuffer_del(batch->lrz_clear);
 348         }
 349
 350         batch->lrz_clear = fd_submit_new_ringbuffer(batch->submit, 0x1000, 0);
 351         ring = batch->lrz_clear;
 352
 353         emit_marker6(ring, 7);
 354         OUT_PKT7(ring, CP_SET_MARKER, 1);
 355         OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
 356         emit_marker6(ring, 7);
 357
 358         OUT_WFI5(ring);
 359
 360         OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
 361         OUT_RING(ring, fd6_ctx->magic.RB_CCU_CNTL_bypass);
 362
 363         OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
 364         OUT_RING(ring, 0x7ffff);
 365
 366         emit_marker6(ring, 7);
 367         OUT_PKT7(ring, CP_SET_MARKER, 1);
 368         OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
 369         emit_marker6(ring, 7);
 370
 371         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
 372         OUT_RING(ring, 0x0);
 373
 374         OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 13);
 375         OUT_RING(ring, 0x00000000);
 376         OUT_RING(ring, 0x00000000);
 377         OUT_RING(ring, 0x00000000);
 378         OUT_RING(ring, 0x00000000);
 379         OUT_RING(ring, 0x00000000);
 380         OUT_RING(ring, 0x00000000);
 381         OUT_RING(ring, 0x00000000);
 382         OUT_RING(ring, 0x00000000);
 383         OUT_RING(ring, 0x00000000);
 384         OUT_RING(ring, 0x00000000);
 385         OUT_RING(ring, 0x00000000);
 386         OUT_RING(ring, 0x00000000);
 387         OUT_RING(ring, 0x00000000);
 388
 389         OUT_PKT4(ring, REG_A6XX_SP_2D_SRC_FORMAT, 1);
 390         OUT_RING(ring, 0x0000f410);
 391
 392         OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
 393         OUT_RING(ring, A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(FMT6_16_UNORM) |
 394                         0x4f00080);
 395
 396         OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
 397         OUT_RING(ring, A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(FMT6_16_UNORM) |
 398                         0x4f00080);
 399
 400         fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
 401         fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
 402
 403         OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
 404         OUT_RING(ring, fui(depth));
 405         OUT_RING(ring, 0x00000000);
 406         OUT_RING(ring, 0x00000000);
 407         OUT_RING(ring, 0x00000000);
 408
 409         OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
 410         OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(FMT6_16_UNORM) |
 411                         A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 412                         A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
 413         OUT_RELOC(ring, zsbuf->lrz, 0, 0, 0);
 414         OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(zsbuf->lrz_pitch * 2));
 415         OUT_RING(ring, 0x00000000);
 416         OUT_RING(ring, 0x00000000);
 417         OUT_RING(ring, 0x00000000);
 418         OUT_RING(ring, 0x00000000);
 419         OUT_RING(ring, 0x00000000);
 420
 421         OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
 422         OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(0));
 423         OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(0));
 424         OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(0));
 425         OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(0));
 426
 427         OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
 428         OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) |
 429                         A6XX_GRAS_2D_DST_TL_Y(0));
 430         OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(zsbuf->lrz_width - 1) |
 431                         A6XX_GRAS_2D_DST_BR_Y(zsbuf->lrz_height - 1));
 432
 433         fd6_event_write(batch, ring, 0x3f, false);
 434
 435         OUT_WFI5(ring);
 436
 437         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
 438         OUT_RING(ring, fd6_ctx->magic.RB_UNKNOWN_8E04_blit);
 439
 440         OUT_PKT7(ring, CP_BLIT, 1);
 441         OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
 442
 443         OUT_WFI5(ring);
 444
 445         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
 446         OUT_RING(ring, 0x0);               /* RB_UNKNOWN_8E04 */
 447
 448         fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
 449         fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
 450         fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
 451
 452         fd6_cache_inv(batch, ring);
 453 }
 454
 455 static bool is_z32(enum pipe_format format)
 456 {
 457         switch (format) {
 458         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 459         case PIPE_FORMAT_Z32_UNORM:
 460         case PIPE_FORMAT_Z32_FLOAT:
 461                 return true;
 462         default:
 463                 return false;
 464         }
 465 }
 466
 467 static bool
 468 fd6_clear(struct fd_context *ctx, unsigned buffers,
 469                 const union pipe_color_union *color, double depth, unsigned stencil)
 470 {
 471         struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
 472         const bool has_depth = pfb->zsbuf;
 473         unsigned color_buffers = buffers >> 2;
 474         unsigned i;
 475
 476         /* If we're clearing after draws, fallback to 3D pipe clears.  We could
 477          * use blitter clears in the draw batch but then we'd have to patch up the
 478          * gmem offsets. This doesn't seem like a useful thing to optimize for
 479          * however.*/
 480         if (ctx->batch->num_draws > 0)
 481                 return false;
 482
 483         foreach_bit(i, color_buffers)
 484                 ctx->batch->clear_color[i] = *color;
 485         if (buffers & PIPE_CLEAR_DEPTH)
 486                 ctx->batch->clear_depth = depth;
 487         if (buffers & PIPE_CLEAR_STENCIL)
 488                 ctx->batch->clear_stencil = stencil;
 489
 490         ctx->batch->fast_cleared |= buffers;
 491
 492         if (has_depth && (buffers & PIPE_CLEAR_DEPTH)) {
 493                 struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
 494                 if (zsbuf->lrz && !is_z32(pfb->zsbuf->format)) {
 495                         zsbuf->lrz_valid = true;
 496                         fd6_clear_lrz(ctx->batch, zsbuf, depth);
 497                 }
 498         }
 499
 500         return true;
 501 }
 502
 503 void
 504 fd6_draw_init(struct pipe_context *pctx)
 505 {
 506         struct fd_context *ctx = fd_context(pctx);
 507         ctx->draw_vbo = fd6_draw_vbo;
 508         ctx->clear = fd6_clear;
 509 }