src/gallium/drivers/freedreno/a6xx/fd6_draw.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #include "pipe/p_state.h"
  29 #include "util/u_string.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_prim.h"
  32
  33 #include "freedreno_state.h"
  34 #include "freedreno_resource.h"
  35
  36 #include "fd6_draw.h"
  37 #include "fd6_context.h"
  38 #include "fd6_emit.h"
  39 #include "fd6_program.h"
  40 #include "fd6_format.h"
  41 #include "fd6_zsa.h"
  42
  43 static void
  44 draw_emit_indirect(struct fd_ringbuffer *ring,
  45                                    uint32_t draw0,
  46                                    const struct pipe_draw_info *info,
  47                                    unsigned index_offset)
  48 {
  49         struct fd_resource *ind = fd_resource(info->indirect->buffer);
  50
  51         if (info->index_size) {
  52                 struct pipe_resource *idx = info->index.resource;
  53                 unsigned max_indicies = (idx->width0 - index_offset) / info->index_size;
  54
  55                 OUT_PKT7(ring, CP_DRAW_INDX_INDIRECT, 6);
  56                 OUT_RING(ring, draw0);
  57                 OUT_RELOC(ring, fd_resource(idx)->bo,
  58                                   index_offset, 0, 0);
  59                 OUT_RING(ring, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies));
  60                 OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
  61         } else {
  62                 OUT_PKT7(ring, CP_DRAW_INDIRECT, 3);
  63                 OUT_RING(ring, draw0);
  64                 OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
  65         }
  66 }
  67
  68 static void
  69 draw_emit(struct fd_ringbuffer *ring,
  70                   uint32_t draw0,
  71                   const struct pipe_draw_info *info,
  72                   unsigned index_offset)
  73 {
  74         if (info->index_size) {
  75                 assert(!info->has_user_indices);
  76
  77                 struct pipe_resource *idx_buffer = info->index.resource;
  78                 uint32_t idx_size = info->index_size * info->count;
  79                 uint32_t idx_offset = index_offset + info->start * info->index_size;
  80
  81                 OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, 7);
  82                 OUT_RING(ring, draw0);
  83                 OUT_RING(ring, info->instance_count);    /* NumInstances */
  84                 OUT_RING(ring, info->count);             /* NumIndices */
  85                 OUT_RING(ring, 0x0);           /* XXX */
  86                 OUT_RELOC(ring, fd_resource(idx_buffer)->bo, idx_offset, 0, 0);
  87                 OUT_RING (ring, idx_size);
  88         } else {
  89                 OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, 3);
  90                 OUT_RING(ring, draw0);
  91                 OUT_RING(ring, info->instance_count);    /* NumInstances */
  92                 OUT_RING(ring, info->count);             /* NumIndices */
  93         }
  94 }
  95
  96 /* fixup dirty shader state in case some "unrelated" (from the state-
  97  * tracker's perspective) state change causes us to switch to a
  98  * different variant.
  99  */
 100 static void
 101 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
 102 {
 103         struct fd6_context *fd6_ctx = fd6_context(ctx);
 104         struct ir3_shader_key *last_key = &fd6_ctx->last_key;
 105
 106         if (!ir3_shader_key_equal(last_key, key)) {
 107                 if (ir3_shader_key_changes_fs(last_key, key)) {
 108                         ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG;
 109                         ctx->dirty |= FD_DIRTY_PROG;
 110                 }
 111
 112                 if (ir3_shader_key_changes_vs(last_key, key)) {
 113                         ctx->dirty_shader[PIPE_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG;
 114                         ctx->dirty |= FD_DIRTY_PROG;
 115                 }
 116
 117                 fd6_ctx->last_key = *key;
 118         }
 119 }
 120
 121 static bool
 122 fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
 123              unsigned index_offset)
 124 {
 125         struct fd6_context *fd6_ctx = fd6_context(ctx);
 126         struct fd6_emit emit = {
 127                 .ctx = ctx,
 128                 .vtx  = &ctx->vtx,
 129                 .info = info,
 130                 .key = {
 131                         .vs = ctx->prog.vs,
 132                         .hs = ctx->prog.hs,
 133                         .ds = ctx->prog.ds,
 134                         .gs = ctx->prog.gs,
 135                         .fs = ctx->prog.fs,
 136                         .key = {
 137                                 .color_two_side = ctx->rasterizer->light_twoside,
 138                                 .vclamp_color = ctx->rasterizer->clamp_vertex_color,
 139                                 .fclamp_color = ctx->rasterizer->clamp_fragment_color,
 140                                 .rasterflat = ctx->rasterizer->flatshade,
 141                                 .ucp_enables = ctx->rasterizer->clip_plane_enable,
 142                                 .has_per_samp = (fd6_ctx->fsaturate || fd6_ctx->vsaturate),
 143                                 .vsaturate_s = fd6_ctx->vsaturate_s,
 144                                 .vsaturate_t = fd6_ctx->vsaturate_t,
 145                                 .vsaturate_r = fd6_ctx->vsaturate_r,
 146                                 .fsaturate_s = fd6_ctx->fsaturate_s,
 147                                 .fsaturate_t = fd6_ctx->fsaturate_t,
 148                                 .fsaturate_r = fd6_ctx->fsaturate_r,
 149                                 .vsamples = ctx->tex[PIPE_SHADER_VERTEX].samples,
 150                                 .fsamples = ctx->tex[PIPE_SHADER_FRAGMENT].samples,
 151                                 .sample_shading = (ctx->min_samples > 1),
 152                                 .msaa = (ctx->framebuffer.samples > 1),
 153                         },
 154                 },
 155                 .rasterflat = ctx->rasterizer->flatshade,
 156                 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 157                 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 158         };
 159
 160         if (emit.key.gs)
 161                 emit.key.key.has_gs = true;
 162
 163         fixup_shader_state(ctx, &emit.key.key);
 164
 165         if (!(ctx->dirty & FD_DIRTY_PROG)) {
 166                 emit.prog = fd6_ctx->prog;
 167         } else {
 168                 fd6_ctx->prog = fd6_emit_get_prog(&emit);
 169         }
 170
 171         /* bail if compile failed: */
 172         if (!fd6_ctx->prog)
 173                 return NULL;
 174
 175         emit.dirty = ctx->dirty;      /* *after* fixup_shader_state() */
 176         emit.bs = fd6_emit_get_prog(&emit)->bs;
 177         emit.vs = fd6_emit_get_prog(&emit)->vs;
 178         emit.hs = fd6_emit_get_prog(&emit)->hs;
 179         emit.ds = fd6_emit_get_prog(&emit)->ds;
 180         emit.gs = fd6_emit_get_prog(&emit)->gs;
 181         emit.fs = fd6_emit_get_prog(&emit)->fs;
 182
 183         ctx->stats.vs_regs += ir3_shader_halfregs(emit.vs);
 184         ctx->stats.hs_regs += COND(emit.hs, ir3_shader_halfregs(emit.hs));
 185         ctx->stats.ds_regs += COND(emit.ds, ir3_shader_halfregs(emit.ds));
 186         ctx->stats.gs_regs += COND(emit.gs, ir3_shader_halfregs(emit.gs));
 187         ctx->stats.fs_regs += ir3_shader_halfregs(emit.fs);
 188
 189         /* figure out whether we need to disable LRZ write for binning
 190          * pass using draw pass's fs:
 191          */
 192         emit.no_lrz_write = emit.fs->writes_pos || emit.fs->no_earlyz;
 193
 194         struct fd_ringbuffer *ring = ctx->batch->draw;
 195         enum pc_di_primtype primtype = ctx->primtypes[info->mode];
 196
 197         fd6_emit_state(ring, &emit);
 198
 199         OUT_PKT4(ring, REG_A6XX_VFD_INDEX_OFFSET, 2);
 200         OUT_RING(ring, info->index_size ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
 201         OUT_RING(ring, info->start_instance);   /* VFD_INSTANCE_START_OFFSET */
 202
 203         OUT_PKT4(ring, REG_A6XX_PC_RESTART_INDEX, 1);
 204         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
 205                         info->restart_index : 0xffffffff);
 206
 207         /* for debug after a lock up, write a unique counter value
 208          * to scratch7 for each draw, to make it easier to match up
 209          * register dumps to cmdstream.  The combination of IB
 210          * (scratch6) and DRAW is enough to "triangulate" the
 211          * particular draw that caused lockup.
 212          */
 213         emit_marker6(ring, 7);
 214
 215         uint32_t draw0 =
 216                 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
 217                 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY);
 218
 219         if (emit.key.gs)
 220                 draw0 |= CP_DRAW_INDX_OFFSET_0_GS_ENABLE;
 221
 222         if (info->index_size) {
 223                 draw0 |=
 224                         CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
 225                         CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(fd4_size2indextype(info->index_size));
 226         } else {
 227                 draw0 |=
 228                         CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX);
 229         }
 230
 231         if (info->indirect) {
 232                 draw_emit_indirect(ring, draw0, info, index_offset);
 233         } else {
 234                 draw_emit(ring, draw0, info, index_offset);
 235         }
 236
 237         emit_marker6(ring, 7);
 238         fd_reset_wfi(ctx->batch);
 239
 240         if (emit.streamout_mask) {
 241                 struct fd_ringbuffer *ring = ctx->batch->draw;
 242
 243                 for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
 244                         if (emit.streamout_mask & (1 << i)) {
 245                                 fd6_event_write(ctx->batch, ring, FLUSH_SO_0 + i, false);
 246                         }
 247                 }
 248         }
 249
 250         fd_context_all_clean(ctx);
 251
 252         return true;
 253 }
 254
 255 static void
 256 fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
 257 {
 258         struct fd_ringbuffer *ring;
 259
 260         // TODO mid-frame clears (ie. app doing crazy stuff)??  Maybe worth
 261         // splitting both clear and lrz clear out into their own rb's.  And
 262         // just throw away any draws prior to clear.  (Anything not fullscreen
 263         // clear, just fallback to generic path that treats it as a normal
 264         // draw
 265
 266         if (!batch->lrz_clear) {
 267                 batch->lrz_clear = fd_submit_new_ringbuffer(batch->submit, 0x1000, 0);
 268         }
 269
 270         ring = batch->lrz_clear;
 271
 272         emit_marker6(ring, 7);
 273         OUT_PKT7(ring, CP_SET_MARKER, 1);
 274         OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
 275         emit_marker6(ring, 7);
 276
 277         OUT_WFI5(ring);
 278
 279         OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
 280         OUT_RING(ring, 0x10000000);
 281
 282         OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
 283         OUT_RING(ring, 0x7ffff);
 284
 285         emit_marker6(ring, 7);
 286         OUT_PKT7(ring, CP_SET_MARKER, 1);
 287         OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0xc));
 288         emit_marker6(ring, 7);
 289
 290         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
 291         OUT_RING(ring, 0x0);
 292
 293         OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 13);
 294         OUT_RING(ring, 0x00000000);
 295         OUT_RING(ring, 0x00000000);
 296         OUT_RING(ring, 0x00000000);
 297         OUT_RING(ring, 0x00000000);
 298         OUT_RING(ring, 0x00000000);
 299         OUT_RING(ring, 0x00000000);
 300         OUT_RING(ring, 0x00000000);
 301         OUT_RING(ring, 0x00000000);
 302         OUT_RING(ring, 0x00000000);
 303         OUT_RING(ring, 0x00000000);
 304         OUT_RING(ring, 0x00000000);
 305         OUT_RING(ring, 0x00000000);
 306         OUT_RING(ring, 0x00000000);
 307
 308         OUT_PKT4(ring, REG_A6XX_SP_2D_SRC_FORMAT, 1);
 309         OUT_RING(ring, 0x0000f410);
 310
 311         OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
 312         OUT_RING(ring, A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(RB6_R16_UNORM) |
 313                         0x4f00080);
 314
 315         OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
 316         OUT_RING(ring, A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(RB6_R16_UNORM) |
 317                         0x4f00080);
 318
 319         fd6_event_write(batch, ring, UNK_1D, true);
 320         fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
 321
 322         OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
 323         OUT_RING(ring, fui(depth));
 324         OUT_RING(ring, 0x00000000);
 325         OUT_RING(ring, 0x00000000);
 326         OUT_RING(ring, 0x00000000);
 327
 328         OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
 329         OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(RB6_R16_UNORM) |
 330                         A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 331                         A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
 332         OUT_RELOCW(ring, zsbuf->lrz, 0, 0, 0);
 333         OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(zsbuf->lrz_pitch * 2));
 334         OUT_RING(ring, 0x00000000);
 335         OUT_RING(ring, 0x00000000);
 336         OUT_RING(ring, 0x00000000);
 337         OUT_RING(ring, 0x00000000);
 338         OUT_RING(ring, 0x00000000);
 339
 340         OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
 341         OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(0));
 342         OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(0));
 343         OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(0));
 344         OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(0));
 345
 346         OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
 347         OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) |
 348                         A6XX_GRAS_2D_DST_TL_Y(0));
 349         OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(zsbuf->lrz_width - 1) |
 350                         A6XX_GRAS_2D_DST_BR_Y(zsbuf->lrz_height - 1));
 351
 352         fd6_event_write(batch, ring, 0x3f, false);
 353
 354         OUT_WFI5(ring);
 355
 356         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
 357         OUT_RING(ring, 0x1000000);
 358
 359         OUT_PKT7(ring, CP_BLIT, 1);
 360         OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
 361
 362         OUT_WFI5(ring);
 363
 364         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
 365         OUT_RING(ring, 0x0);
 366
 367         fd6_event_write(batch, ring, UNK_1D, true);
 368         fd6_event_write(batch, ring, FACENESS_FLUSH, true);
 369         fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
 370
 371         fd6_cache_inv(batch, ring);
 372 }
 373
 374 static bool is_z32(enum pipe_format format)
 375 {
 376         switch (format) {
 377         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 378         case PIPE_FORMAT_Z32_UNORM:
 379         case PIPE_FORMAT_Z32_FLOAT:
 380                 return true;
 381         default:
 382                 return false;
 383         }
 384 }
 385
 386 static bool
 387 fd6_clear(struct fd_context *ctx, unsigned buffers,
 388                 const union pipe_color_union *color, double depth, unsigned stencil)
 389 {
 390         struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
 391         const bool has_depth = pfb->zsbuf;
 392         unsigned color_buffers = buffers >> 2;
 393         unsigned i;
 394
 395         /* If we're clearing after draws, fallback to 3D pipe clears.  We could
 396          * use blitter clears in the draw batch but then we'd have to patch up the
 397          * gmem offsets. This doesn't seem like a useful thing to optimize for
 398          * however.*/
 399         if (ctx->batch->num_draws > 0)
 400                 return false;
 401
 402         foreach_bit(i, color_buffers)
 403                 ctx->batch->clear_color[i] = *color;
 404         if (buffers & PIPE_CLEAR_DEPTH)
 405                 ctx->batch->clear_depth = depth;
 406         if (buffers & PIPE_CLEAR_STENCIL)
 407                 ctx->batch->clear_stencil = stencil;
 408
 409         ctx->batch->fast_cleared |= buffers;
 410
 411         if (has_depth && (buffers & PIPE_CLEAR_DEPTH)) {
 412                 struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
 413                 if (zsbuf->lrz && !is_z32(pfb->zsbuf->format)) {
 414                         zsbuf->lrz_valid = true;
 415                         fd6_clear_lrz(ctx->batch, zsbuf, depth);
 416                 }
 417         }
 418
 419         return true;
 420 }
 421
 422 void
 423 fd6_draw_init(struct pipe_context *pctx)
 424 {
 425         struct fd_context *ctx = fd_context(pctx);
 426         ctx->draw_vbo = fd6_draw_vbo;
 427         ctx->clear = fd6_clear;
 428 }