src/gallium/drivers/freedreno/a6xx/fd6_draw.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #include "pipe/p_state.h"
  29 #include "util/u_string.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_prim.h"
  32
  33 #include "freedreno_state.h"
  34 #include "freedreno_resource.h"
  35
  36 #include "fd6_draw.h"
  37 #include "fd6_context.h"
  38 #include "fd6_emit.h"
  39 #include "fd6_program.h"
  40 #include "fd6_format.h"
  41 #include "fd6_zsa.h"
  42
  43
  44 static void
  45 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
  46                 struct fd6_emit *emit, unsigned index_offset)
  47 {
  48         const struct pipe_draw_info *info = emit->info;
  49         enum pc_di_primtype primtype = ctx->primtypes[info->mode];
  50
  51         fd6_emit_state(ctx, ring, emit);
  52
  53         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
  54                 fd6_emit_vertex_bufs(ring, emit);
  55
  56         OUT_PKT4(ring, REG_A6XX_VFD_INDEX_OFFSET, 2);
  57         OUT_RING(ring, info->index_size ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
  58         OUT_RING(ring, info->start_instance);   /* VFD_INSTANCE_START_OFFSET */
  59
  60         OUT_PKT4(ring, REG_A6XX_PC_RESTART_INDEX, 1);
  61         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
  62                         info->restart_index : 0xffffffff);
  63
  64         fd6_emit_render_cntl(ctx, false, emit->key.binning_pass);
  65         fd6_draw_emit(ctx->batch, ring, primtype,
  66                         emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
  67                         info, index_offset);
  68 }
  69
  70 /* fixup dirty shader state in case some "unrelated" (from the state-
  71  * tracker's perspective) state change causes us to switch to a
  72  * different variant.
  73  */
  74 static void
  75 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
  76 {
  77         struct fd6_context *fd6_ctx = fd6_context(ctx);
  78         struct ir3_shader_key *last_key = &fd6_ctx->last_key;
  79
  80         if (!ir3_shader_key_equal(last_key, key)) {
  81                 if (ir3_shader_key_changes_fs(last_key, key)) {
  82                         ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG;
  83                         ctx->dirty |= FD_DIRTY_PROG;
  84                 }
  85
  86                 if (ir3_shader_key_changes_vs(last_key, key)) {
  87                         ctx->dirty_shader[PIPE_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG;
  88                         ctx->dirty |= FD_DIRTY_PROG;
  89                 }
  90
  91                 fd6_ctx->last_key = *key;
  92         }
  93 }
  94
  95 static bool
  96 fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
  97              unsigned index_offset)
  98 {
  99         struct fd6_context *fd6_ctx = fd6_context(ctx);
 100         struct fd6_emit emit = {
 101                 .debug = &ctx->debug,
 102                 .vtx  = &ctx->vtx,
 103                 .prog = &ctx->prog,
 104                 .info = info,
 105                 .key = {
 106                         .color_two_side = ctx->rasterizer->light_twoside,
 107                         .vclamp_color = ctx->rasterizer->clamp_vertex_color,
 108                         .fclamp_color = ctx->rasterizer->clamp_fragment_color,
 109                         .rasterflat = ctx->rasterizer->flatshade,
 110                         .half_precision = ctx->in_blit &&
 111                                         fd_half_precision(&ctx->batch->framebuffer),
 112                         .ucp_enables = ctx->rasterizer->clip_plane_enable,
 113                         .has_per_samp = (fd6_ctx->fsaturate || fd6_ctx->vsaturate ||
 114                                         fd6_ctx->fastc_srgb || fd6_ctx->vastc_srgb),
 115                         .vsaturate_s = fd6_ctx->vsaturate_s,
 116                         .vsaturate_t = fd6_ctx->vsaturate_t,
 117                         .vsaturate_r = fd6_ctx->vsaturate_r,
 118                         .fsaturate_s = fd6_ctx->fsaturate_s,
 119                         .fsaturate_t = fd6_ctx->fsaturate_t,
 120                         .fsaturate_r = fd6_ctx->fsaturate_r,
 121                         .vastc_srgb = fd6_ctx->vastc_srgb,
 122                         .fastc_srgb = fd6_ctx->fastc_srgb,
 123                         .vsamples = ctx->tex[PIPE_SHADER_VERTEX].samples,
 124                         .fsamples = ctx->tex[PIPE_SHADER_FRAGMENT].samples,
 125                 },
 126                 .rasterflat = ctx->rasterizer->flatshade,
 127                 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 128                 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 129         };
 130
 131         fixup_shader_state(ctx, &emit.key);
 132
 133         unsigned dirty = ctx->dirty;
 134         const struct ir3_shader_variant *vp = fd6_emit_get_vp(&emit);
 135         const struct ir3_shader_variant *fp = fd6_emit_get_fp(&emit);
 136
 137         /* do regular pass first, since that is more likely to fail compiling: */
 138
 139         if (!vp || !fp)
 140                 return false;
 141
 142         ctx->stats.vs_regs += ir3_shader_halfregs(vp);
 143         ctx->stats.fs_regs += ir3_shader_halfregs(fp);
 144
 145         /* figure out whether we need to disable LRZ write for binning
 146          * pass using draw pass's fp:
 147          */
 148         emit.no_lrz_write = fp->writes_pos || fp->has_kill;
 149
 150         emit.key.binning_pass = false;
 151         emit.dirty = dirty;
 152
 153         draw_impl(ctx, ctx->batch->draw, &emit, index_offset);
 154
 155         /* and now binning pass: */
 156         emit.key.binning_pass = true;
 157         emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 158         emit.vp = NULL;   /* we changed key so need to refetch vp */
 159         emit.fp = NULL;
 160         draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
 161
 162         if (emit.streamout_mask) {
 163                 struct fd_ringbuffer *ring = ctx->batch->draw;
 164
 165                 for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
 166                         if (emit.streamout_mask & (1 << i)) {
 167                                 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 168                                 OUT_RING(ring, FLUSH_SO_0 + i);
 169                         }
 170                 }
 171         }
 172
 173         fd_context_all_clean(ctx);
 174
 175         return true;
 176 }
 177
 178 static bool is_z32(enum pipe_format format)
 179 {
 180         switch (format) {
 181         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 182         case PIPE_FORMAT_Z32_UNORM:
 183         case PIPE_FORMAT_Z32_FLOAT:
 184                 return true;
 185         default:
 186                 return false;
 187         }
 188 }
 189
 190 #if 0
 191 static void
 192 fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
 193 {
 194         struct fd_ringbuffer *ring;
 195         uint32_t clear = util_pack_z(PIPE_FORMAT_Z16_UNORM, depth);
 196
 197         // TODO mid-frame clears (ie. app doing crazy stuff)??  Maybe worth
 198         // splitting both clear and lrz clear out into their own rb's.  And
 199         // just throw away any draws prior to clear.  (Anything not fullscreen
 200         // clear, just fallback to generic path that treats it as a normal
 201         // draw
 202
 203         if (!batch->lrz_clear) {
 204                 batch->lrz_clear = fd_ringbuffer_new(batch->ctx->pipe, 0x1000);
 205                 fd_ringbuffer_set_parent(batch->lrz_clear, batch->gmem);
 206         }
 207
 208         ring = batch->lrz_clear;
 209
 210         OUT_WFI5(ring);
 211
 212         OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
 213         OUT_RING(ring, 0x10000000);
 214
 215         OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
 216         OUT_RING(ring, 0x20fffff);
 217
 218         OUT_PKT4(ring, REG_A6XX_GRAS_SU_CNTL, 1);
 219         OUT_RING(ring, A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(0.0));
 220
 221         OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
 222         OUT_RING(ring, 0x00000000);
 223
 224         OUT_PKT4(ring, REG_A6XX_GRAS_CL_CNTL, 1);
 225         OUT_RING(ring, 0x00000181);
 226
 227         OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
 228         OUT_RING(ring, 0x00000000);
 229
 230         OUT_PKT4(ring, REG_A6XX_RB_MRT_BUF_INFO(0), 5);
 231         OUT_RING(ring, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(RB5_R16_UNORM) |
 232                         A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(TILE6_LINEAR) |
 233                         A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX));
 234         OUT_RING(ring, A6XX_RB_MRT_PITCH(zsbuf->lrz_pitch * 2));
 235         OUT_RING(ring, A6XX_RB_MRT_ARRAY_PITCH(fd_bo_size(zsbuf->lrz)));
 236         OUT_RELOCW(ring, zsbuf->lrz, 0x1000, 0, 0);
 237
 238         OUT_PKT4(ring, REG_A6XX_RB_RENDER_CNTL, 1);
 239         OUT_RING(ring, 0x00000000);
 240
 241         OUT_PKT4(ring, REG_A6XX_RB_DEST_MSAA_CNTL, 1);
 242         OUT_RING(ring, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE));
 243
 244         OUT_PKT4(ring, REG_A6XX_RB_BLIT_CNTL, 1);
 245         OUT_RING(ring, A6XX_RB_BLIT_CNTL_BUF(BLIT_MRT0));
 246
 247         OUT_PKT4(ring, REG_A6XX_RB_CLEAR_CNTL, 1);
 248         OUT_RING(ring, A6XX_RB_CLEAR_CNTL_FAST_CLEAR |
 249                         A6XX_RB_CLEAR_CNTL_MASK(0xf));
 250
 251         OUT_PKT4(ring, REG_A6XX_RB_CLEAR_COLOR_DW0, 1);
 252         OUT_RING(ring, clear);  /* RB_CLEAR_COLOR_DW0 */
 253
 254         OUT_PKT4(ring, REG_A6XX_VSC_RESOLVE_CNTL, 2);
 255         OUT_RING(ring, A6XX_VSC_RESOLVE_CNTL_X(zsbuf->lrz_width) |
 256                          A6XX_VSC_RESOLVE_CNTL_Y(zsbuf->lrz_height));
 257         OUT_RING(ring, 0x00000000);   // XXX UNKNOWN_0CDE
 258
 259         OUT_PKT4(ring, REG_A6XX_RB_CNTL, 1);
 260         OUT_RING(ring, A6XX_RB_CNTL_BYPASS);
 261
 262         OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_CNTL_1, 2);
 263         OUT_RING(ring, A6XX_RB_RESOLVE_CNTL_1_X(0) |
 264                         A6XX_RB_RESOLVE_CNTL_1_Y(0));
 265         OUT_RING(ring, A6XX_RB_RESOLVE_CNTL_2_X(zsbuf->lrz_width - 1) |
 266                         A6XX_RB_RESOLVE_CNTL_2_Y(zsbuf->lrz_height - 1));
 267
 268         fd6_emit_blit(batch->ctx, ring);
 269 }
 270 #endif
 271
 272 #if 0
 273 clear_with_cp_blit()
 274 {
 275         /* Clear with CP_BLIT */
 276         WRITE(REG_A6XX_GRAS_2D_BLIT_CNTL, 0x10f43180);
 277
 278         OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 7);
 279         OUT_RING(ring, 0);
 280         OUT_RING(ring, 0);
 281         OUT_RING(ring, 0);
 282         OUT_RING(ring, 0);
 283         OUT_RING(ring, 0);
 284         OUT_RING(ring, 0);
 285         OUT_RING(ring, 0);
 286
 287         WRITE(0xacc0, 0xf181);
 288         WRITE(0xacc0, 0xf181);
 289
 290         WRITE(REG_A6XX_GRAS_2D_BLIT_CNTL, 0x10f43180);
 291         WRITE(REG_A6XX_RB_2D_BLIT_CNTL, 0x10f43180);
 292
 293         OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
 294         OUT_RING(ring, 0);
 295         OUT_RING(ring, 0);
 296         OUT_RING(ring, 0xff);
 297         OUT_RING(ring, 0);
 298
 299         DBG("%x %x %x %x\n", color->ui[0], color->ui[1], color->ui[2], color->ui[3]);
 300
 301         struct pipe_surface *psurf = pfb->cbufs[0];
 302         struct fd_resource *rsc = fd_resource(psurf->texture);
 303         struct fd_resource_slice *slice = fd_resource_slice(rsc, psurf->u.tex.level);
 304
 305         uint32_t offset = fd_resource_offset(rsc, psurf->u.tex.level,
 306                                                                                  psurf->u.tex.first_layer);
 307         uint32_t stride = slice->pitch * rsc->cpp;
 308
 309         enum a6xx_color_fmt format = fd6_pipe2color(pfmt);
 310         OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
 311         OUT_RING(ring,
 312                          A6XX_RB_2D_DST_INFO_COLOR_FORMAT(format) |
 313                          A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 314                          A6XX_RB_2D_DST_INFO_COLOR_SWAP(WXYZ));
 315         OUT_RELOCW(ring, rsc->bo, offset, 0, 0);  /* RB_2D_DST_LO/HI */
 316         OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(stride));
 317         OUT_RING(ring, 0);
 318         OUT_RING(ring, 0);
 319         OUT_RING(ring, 0);
 320         OUT_RING(ring, 0);
 321         OUT_RING(ring, 0);
 322
 323         OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
 324         OUT_RING(ring, 0);
 325         OUT_RING(ring, 0);
 326         OUT_RING(ring, 0);
 327         OUT_RING(ring, 0);
 328
 329         OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
 330         OUT_RING(ring,
 331                          A6XX_GRAS_2D_DST_TL_X(ctx->batch->max_scissor.minx) |
 332                          A6XX_GRAS_2D_DST_TL_Y(ctx->batch->max_scissor.miny));
 333         OUT_RING(ring,
 334                          A6XX_GRAS_2D_DST_BR_X(ctx->batch->max_scissor.maxx) |
 335                          A6XX_GRAS_2D_DST_BR_Y(ctx->batch->max_scissor.maxy));
 336
 337         OUT_PKT7(ring, CP_BLIT, 1);
 338         OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
 339 }
 340 #endif
 341
 342 static bool
 343 fd6_clear(struct fd_context *ctx, unsigned buffers,
 344                 const union pipe_color_union *color, double depth, unsigned stencil)
 345 {
 346         struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
 347         struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
 348         struct fd_ringbuffer *ring = ctx->batch->draw;
 349
 350         if ((buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) &&
 351                         is_z32(pfb->zsbuf->format))
 352                 return false;
 353
 354         ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
 355         ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
 356         ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
 357         ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
 358
 359         fd6_emit_render_cntl(ctx, true, false);
 360
 361         OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
 362         OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_TL_X(scissor->minx) |
 363                          A6XX_RB_BLIT_SCISSOR_TL_Y(scissor->miny));
 364         OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_BR_X(scissor->maxx - 1) |
 365                          A6XX_RB_BLIT_SCISSOR_BR_Y(scissor->maxy - 1));
 366
 367         if (buffers & PIPE_CLEAR_COLOR) {
 368                 for (int i = 0; i < pfb->nr_cbufs; i++) {
 369                         union util_color uc = {0};
 370
 371                         if (!pfb->cbufs[i])
 372                                 continue;
 373
 374                         if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
 375                                 continue;
 376
 377                         enum pipe_format pfmt = pfb->cbufs[i]->format;
 378
 379                         // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
 380                         union pipe_color_union swapped;
 381                         switch (fd6_pipe2swap(pfmt)) {
 382                         case WZYX:
 383                                 swapped.ui[0] = color->ui[0];
 384                                 swapped.ui[1] = color->ui[1];
 385                                 swapped.ui[2] = color->ui[2];
 386                                 swapped.ui[3] = color->ui[3];
 387                                 break;
 388                         case WXYZ:
 389                                 swapped.ui[2] = color->ui[0];
 390                                 swapped.ui[1] = color->ui[1];
 391                                 swapped.ui[0] = color->ui[2];
 392                                 swapped.ui[3] = color->ui[3];
 393                                 break;
 394                         case ZYXW:
 395                                 swapped.ui[3] = color->ui[0];
 396                                 swapped.ui[0] = color->ui[1];
 397                                 swapped.ui[1] = color->ui[2];
 398                                 swapped.ui[2] = color->ui[3];
 399                                 break;
 400                         case XYZW:
 401                                 swapped.ui[3] = color->ui[0];
 402                                 swapped.ui[2] = color->ui[1];
 403                                 swapped.ui[1] = color->ui[2];
 404                                 swapped.ui[0] = color->ui[3];
 405                                 break;
 406                         }
 407
 408                         if (util_format_is_pure_uint(pfmt)) {
 409                                 util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
 410                         } else if (util_format_is_pure_sint(pfmt)) {
 411                                 util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
 412                         } else {
 413                                 util_pack_color(swapped.f, pfmt, &uc);
 414                         }
 415
 416                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
 417                         OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 418                                 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
 419
 420                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
 421                         OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
 422                                 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
 423
 424                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
 425                         OUT_RINGP(ring, i, &ctx->batch->gmem_patches);
 426
 427                         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
 428                         OUT_RING(ring, 0);
 429
 430                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
 431                         OUT_RING(ring, uc.ui[0]);
 432                         OUT_RING(ring, uc.ui[1]);
 433                         OUT_RING(ring, uc.ui[2]);
 434                         OUT_RING(ring, uc.ui[3]);
 435
 436                         fd6_emit_blit(ctx, ring);
 437                 }
 438         }
 439
 440         if (pfb->zsbuf && (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))) {
 441                 enum pipe_format pfmt = pfb->zsbuf->format;
 442                 uint32_t clear = util_pack_z_stencil(pfmt, depth, stencil);
 443                 uint32_t mask = 0;
 444
 445                 if (buffers & PIPE_CLEAR_DEPTH)
 446                         mask |= 0x1;
 447
 448                 if (buffers & PIPE_CLEAR_STENCIL)
 449                         mask |= 0x2;
 450
 451                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
 452                 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 453                         A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
 454
 455                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
 456                 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
 457                         // XXX UNK0 for separate stencil ??
 458                         A6XX_RB_BLIT_INFO_DEPTH |
 459                         A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
 460
 461                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
 462                 OUT_RINGP(ring, MAX_RENDER_TARGETS, &ctx->batch->gmem_patches);
 463
 464                 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
 465                 OUT_RING(ring, 0);
 466
 467                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
 468                 OUT_RING(ring, clear);
 469
 470                 fd6_emit_blit(ctx, ring);
 471
 472 #if 0
 473                 if (pfb->zsbuf && (buffers & PIPE_CLEAR_DEPTH)) {
 474                         struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
 475                         if (zsbuf->lrz) {
 476                                 zsbuf->lrz_valid = true;
 477                                 fd6_clear_lrz(ctx->batch, zsbuf, depth);
 478                         }
 479                 }
 480 #endif
 481         }
 482
 483         return true;
 484 }
 485
 486 void
 487 fd6_draw_init(struct pipe_context *pctx)
 488 {
 489         struct fd_context *ctx = fd_context(pctx);
 490         ctx->draw_vbo = fd6_draw_vbo;
 491         ctx->clear = fd6_clear;
 492 }