src/gallium/drivers/freedreno/a6xx/fd6_draw.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #include "pipe/p_state.h"
  29 #include "util/u_string.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_prim.h"
  32
  33 #include "freedreno_state.h"
  34 #include "freedreno_resource.h"
  35
  36 #include "fd6_draw.h"
  37 #include "fd6_context.h"
  38 #include "fd6_emit.h"
  39 #include "fd6_program.h"
  40 #include "fd6_format.h"
  41 #include "fd6_zsa.h"
  42
  43 /* some bits in common w/ a4xx: */
  44 #include "a4xx/fd4_draw.h"
  45
  46 static inline void
  47 fd6_draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring,
  48                 enum pc_di_primtype primtype,
  49                 enum pc_di_vis_cull_mode vismode,
  50                 const struct pipe_draw_info *info,
  51                 unsigned index_offset)
  52 {
  53         struct pipe_resource *idx_buffer = NULL;
  54         enum a4xx_index_size idx_type;
  55         enum pc_di_src_sel src_sel;
  56         uint32_t idx_size, idx_offset;
  57
  58         if (info->indirect) {
  59                 struct fd_resource *ind = fd_resource(info->indirect->buffer);
  60
  61                 if (info->index_size) {
  62                         struct pipe_resource *idx = info->index.resource;
  63                         unsigned max_indicies = (idx->width0 - info->indirect->offset) /
  64                                         info->index_size;
  65
  66                         OUT_PKT7(ring, CP_DRAW_INDX_INDIRECT, 6);
  67                         OUT_RINGP(ring, DRAW4(primtype, DI_SRC_SEL_DMA,
  68                                         fd4_size2indextype(info->index_size), 0),
  69                                         &batch->draw_patches);
  70                         OUT_RELOC(ring, fd_resource(idx)->bo,
  71                                         index_offset, 0, 0);
  72                         // XXX: Check A5xx vs A6xx
  73                         OUT_RING(ring, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies));
  74                         OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
  75                 } else {
  76                         OUT_PKT7(ring, CP_DRAW_INDIRECT, 3);
  77                         OUT_RINGP(ring, DRAW4(primtype, DI_SRC_SEL_AUTO_INDEX, 0, 0),
  78                                         &batch->draw_patches);
  79                         OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
  80                 }
  81
  82                 return;
  83         }
  84
  85         if (info->index_size) {
  86                 assert(!info->has_user_indices);
  87
  88                 idx_buffer = info->index.resource;
  89                 idx_type = fd4_size2indextype(info->index_size);
  90                 idx_size = info->index_size * info->count;
  91                 idx_offset = index_offset + info->start * info->index_size;
  92                 src_sel = DI_SRC_SEL_DMA;
  93         } else {
  94                 idx_buffer = NULL;
  95                 idx_type = INDEX4_SIZE_32_BIT;
  96                 idx_size = 0;
  97                 idx_offset = 0;
  98                 src_sel = DI_SRC_SEL_AUTO_INDEX;
  99         }
 100
 101         OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, idx_buffer ? 7 : 3);
 102         if (vismode == USE_VISIBILITY) {
 103                 /* leave vis mode blank for now, it will be patched up when
 104                  * we know if we are binning or not
 105                  */
 106                 OUT_RINGP(ring, DRAW4(primtype, src_sel, idx_type, 0) | 0x2000,
 107                                 &batch->draw_patches);
 108         } else {
 109                 OUT_RING(ring, DRAW4(primtype, src_sel, idx_type, vismode) | 0x2000);
 110         }
 111         OUT_RING(ring, info->instance_count);    /* NumInstances */
 112         OUT_RING(ring, info->count);             /* NumIndices */
 113         if (idx_buffer) {
 114                 OUT_RING(ring, 0x0);           /* XXX */
 115                 OUT_RELOC(ring, fd_resource(idx_buffer)->bo, idx_offset, 0, 0);
 116                 OUT_RING (ring, idx_size);
 117         }
 118 }
 119
 120 static void
 121 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
 122                 struct fd6_emit *emit, unsigned index_offset)
 123 {
 124         const struct pipe_draw_info *info = emit->info;
 125         enum pc_di_primtype primtype = ctx->primtypes[info->mode];
 126
 127         fd6_emit_state(ctx, ring, emit);
 128
 129         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
 130                 fd6_emit_vertex_bufs(ring, emit);
 131
 132         OUT_PKT4(ring, REG_A6XX_VFD_INDEX_OFFSET, 2);
 133         OUT_RING(ring, info->index_size ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
 134         OUT_RING(ring, info->start_instance);   /* VFD_INSTANCE_START_OFFSET */
 135
 136         OUT_PKT4(ring, REG_A6XX_PC_RESTART_INDEX, 1);
 137         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
 138                         info->restart_index : 0xffffffff);
 139
 140         fd6_emit_render_cntl(ctx, false, emit->key.binning_pass);
 141
 142         /* for debug after a lock up, write a unique counter value
 143          * to scratch7 for each draw, to make it easier to match up
 144          * register dumps to cmdstream.  The combination of IB
 145          * (scratch6) and DRAW is enough to "triangulate" the
 146          * particular draw that caused lockup.
 147          */
 148         emit_marker6(ring, 7);
 149
 150         fd6_draw_emit(ctx->batch, ring, primtype,
 151                         emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
 152                         info, index_offset);
 153
 154         emit_marker6(ring, 7);
 155         fd_reset_wfi(ctx->batch);
 156 }
 157
 158 /* fixup dirty shader state in case some "unrelated" (from the state-
 159  * tracker's perspective) state change causes us to switch to a
 160  * different variant.
 161  */
 162 static void
 163 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
 164 {
 165         struct fd6_context *fd6_ctx = fd6_context(ctx);
 166         struct ir3_shader_key *last_key = &fd6_ctx->last_key;
 167
 168         if (!ir3_shader_key_equal(last_key, key)) {
 169                 if (ir3_shader_key_changes_fs(last_key, key)) {
 170                         ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG;
 171                         ctx->dirty |= FD_DIRTY_PROG;
 172                 }
 173
 174                 if (ir3_shader_key_changes_vs(last_key, key)) {
 175                         ctx->dirty_shader[PIPE_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG;
 176                         ctx->dirty |= FD_DIRTY_PROG;
 177                 }
 178
 179                 fd6_ctx->last_key = *key;
 180         }
 181 }
 182
 183 static bool
 184 fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
 185              unsigned index_offset)
 186 {
 187         struct fd6_context *fd6_ctx = fd6_context(ctx);
 188         struct fd6_emit emit = {
 189                 .debug = &ctx->debug,
 190                 .vtx  = &ctx->vtx,
 191                 .prog = &ctx->prog,
 192                 .info = info,
 193                 .key = {
 194                         .color_two_side = ctx->rasterizer->light_twoside,
 195                         .vclamp_color = ctx->rasterizer->clamp_vertex_color,
 196                         .fclamp_color = ctx->rasterizer->clamp_fragment_color,
 197                         .rasterflat = ctx->rasterizer->flatshade,
 198                         .half_precision = ctx->in_blit &&
 199                                         fd_half_precision(&ctx->batch->framebuffer),
 200                         .ucp_enables = ctx->rasterizer->clip_plane_enable,
 201                         .has_per_samp = (fd6_ctx->fsaturate || fd6_ctx->vsaturate ||
 202                                         fd6_ctx->fastc_srgb || fd6_ctx->vastc_srgb),
 203                         .vsaturate_s = fd6_ctx->vsaturate_s,
 204                         .vsaturate_t = fd6_ctx->vsaturate_t,
 205                         .vsaturate_r = fd6_ctx->vsaturate_r,
 206                         .fsaturate_s = fd6_ctx->fsaturate_s,
 207                         .fsaturate_t = fd6_ctx->fsaturate_t,
 208                         .fsaturate_r = fd6_ctx->fsaturate_r,
 209                         .vastc_srgb = fd6_ctx->vastc_srgb,
 210                         .fastc_srgb = fd6_ctx->fastc_srgb,
 211                         .vsamples = ctx->tex[PIPE_SHADER_VERTEX].samples,
 212                         .fsamples = ctx->tex[PIPE_SHADER_FRAGMENT].samples,
 213                 },
 214                 .rasterflat = ctx->rasterizer->flatshade,
 215                 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 216                 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 217         };
 218
 219         fixup_shader_state(ctx, &emit.key);
 220
 221         unsigned dirty = ctx->dirty;
 222         const struct ir3_shader_variant *vp = fd6_emit_get_vp(&emit);
 223         const struct ir3_shader_variant *fp = fd6_emit_get_fp(&emit);
 224
 225         /* do regular pass first, since that is more likely to fail compiling: */
 226
 227         if (!vp || !fp)
 228                 return false;
 229
 230         ctx->stats.vs_regs += ir3_shader_halfregs(vp);
 231         ctx->stats.fs_regs += ir3_shader_halfregs(fp);
 232
 233         /* figure out whether we need to disable LRZ write for binning
 234          * pass using draw pass's fp:
 235          */
 236         emit.no_lrz_write = fp->writes_pos || fp->has_kill;
 237
 238         emit.key.binning_pass = false;
 239         emit.dirty = dirty;
 240
 241         draw_impl(ctx, ctx->batch->draw, &emit, index_offset);
 242
 243         /* and now binning pass: */
 244         emit.key.binning_pass = true;
 245         emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 246         emit.vp = NULL;   /* we changed key so need to refetch vp */
 247         emit.fp = NULL;
 248         draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
 249
 250         if (emit.streamout_mask) {
 251                 struct fd_ringbuffer *ring = ctx->batch->draw;
 252
 253                 for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
 254                         if (emit.streamout_mask & (1 << i)) {
 255                                 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 256                                 OUT_RING(ring, FLUSH_SO_0 + i);
 257                         }
 258                 }
 259         }
 260
 261         fd_context_all_clean(ctx);
 262
 263         return true;
 264 }
 265
 266 static bool is_z32(enum pipe_format format)
 267 {
 268         switch (format) {
 269         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 270         case PIPE_FORMAT_Z32_UNORM:
 271         case PIPE_FORMAT_Z32_FLOAT:
 272                 return true;
 273         default:
 274                 return false;
 275         }
 276 }
 277
 278 #if 0
 279 static void
 280 fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
 281 {
 282         struct fd_ringbuffer *ring;
 283         uint32_t clear = util_pack_z(PIPE_FORMAT_Z16_UNORM, depth);
 284
 285         // TODO mid-frame clears (ie. app doing crazy stuff)??  Maybe worth
 286         // splitting both clear and lrz clear out into their own rb's.  And
 287         // just throw away any draws prior to clear.  (Anything not fullscreen
 288         // clear, just fallback to generic path that treats it as a normal
 289         // draw
 290
 291         if (!batch->lrz_clear) {
 292                 batch->lrz_clear = fd_ringbuffer_new(batch->ctx->pipe, 0x1000);
 293                 fd_ringbuffer_set_parent(batch->lrz_clear, batch->gmem);
 294         }
 295
 296         ring = batch->lrz_clear;
 297
 298         OUT_WFI5(ring);
 299
 300         OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
 301         OUT_RING(ring, 0x10000000);
 302
 303         OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
 304         OUT_RING(ring, 0x20fffff);
 305
 306         OUT_PKT4(ring, REG_A6XX_GRAS_SU_CNTL, 1);
 307         OUT_RING(ring, A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(0.0));
 308
 309         OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
 310         OUT_RING(ring, 0x00000000);
 311
 312         OUT_PKT4(ring, REG_A6XX_GRAS_CL_CNTL, 1);
 313         OUT_RING(ring, 0x00000181);
 314
 315         OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
 316         OUT_RING(ring, 0x00000000);
 317
 318         OUT_PKT4(ring, REG_A6XX_RB_MRT_BUF_INFO(0), 5);
 319         OUT_RING(ring, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(RB5_R16_UNORM) |
 320                         A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(TILE6_LINEAR) |
 321                         A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX));
 322         OUT_RING(ring, A6XX_RB_MRT_PITCH(zsbuf->lrz_pitch * 2));
 323         OUT_RING(ring, A6XX_RB_MRT_ARRAY_PITCH(fd_bo_size(zsbuf->lrz)));
 324         OUT_RELOCW(ring, zsbuf->lrz, 0x1000, 0, 0);
 325
 326         OUT_PKT4(ring, REG_A6XX_RB_RENDER_CNTL, 1);
 327         OUT_RING(ring, 0x00000000);
 328
 329         OUT_PKT4(ring, REG_A6XX_RB_DEST_MSAA_CNTL, 1);
 330         OUT_RING(ring, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE));
 331
 332         OUT_PKT4(ring, REG_A6XX_RB_BLIT_CNTL, 1);
 333         OUT_RING(ring, A6XX_RB_BLIT_CNTL_BUF(BLIT_MRT0));
 334
 335         OUT_PKT4(ring, REG_A6XX_RB_CLEAR_CNTL, 1);
 336         OUT_RING(ring, A6XX_RB_CLEAR_CNTL_FAST_CLEAR |
 337                         A6XX_RB_CLEAR_CNTL_MASK(0xf));
 338
 339         OUT_PKT4(ring, REG_A6XX_RB_CLEAR_COLOR_DW0, 1);
 340         OUT_RING(ring, clear);  /* RB_CLEAR_COLOR_DW0 */
 341
 342         OUT_PKT4(ring, REG_A6XX_VSC_RESOLVE_CNTL, 2);
 343         OUT_RING(ring, A6XX_VSC_RESOLVE_CNTL_X(zsbuf->lrz_width) |
 344                          A6XX_VSC_RESOLVE_CNTL_Y(zsbuf->lrz_height));
 345         OUT_RING(ring, 0x00000000);   // XXX UNKNOWN_0CDE
 346
 347         OUT_PKT4(ring, REG_A6XX_RB_CNTL, 1);
 348         OUT_RING(ring, A6XX_RB_CNTL_BYPASS);
 349
 350         OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_CNTL_1, 2);
 351         OUT_RING(ring, A6XX_RB_RESOLVE_CNTL_1_X(0) |
 352                         A6XX_RB_RESOLVE_CNTL_1_Y(0));
 353         OUT_RING(ring, A6XX_RB_RESOLVE_CNTL_2_X(zsbuf->lrz_width - 1) |
 354                         A6XX_RB_RESOLVE_CNTL_2_Y(zsbuf->lrz_height - 1));
 355
 356         fd6_emit_blit(batch->ctx, ring);
 357 }
 358 #endif
 359
 360 #if 0
 361 clear_with_cp_blit()
 362 {
 363         /* Clear with CP_BLIT */
 364         WRITE(REG_A6XX_GRAS_2D_BLIT_CNTL, 0x10f43180);
 365
 366         OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 7);
 367         OUT_RING(ring, 0);
 368         OUT_RING(ring, 0);
 369         OUT_RING(ring, 0);
 370         OUT_RING(ring, 0);
 371         OUT_RING(ring, 0);
 372         OUT_RING(ring, 0);
 373         OUT_RING(ring, 0);
 374
 375         WRITE(0xacc0, 0xf181);
 376         WRITE(0xacc0, 0xf181);
 377
 378         WRITE(REG_A6XX_GRAS_2D_BLIT_CNTL, 0x10f43180);
 379         WRITE(REG_A6XX_RB_2D_BLIT_CNTL, 0x10f43180);
 380
 381         OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
 382         OUT_RING(ring, 0);
 383         OUT_RING(ring, 0);
 384         OUT_RING(ring, 0xff);
 385         OUT_RING(ring, 0);
 386
 387         DBG("%x %x %x %x\n", color->ui[0], color->ui[1], color->ui[2], color->ui[3]);
 388
 389         struct pipe_surface *psurf = pfb->cbufs[0];
 390         struct fd_resource *rsc = fd_resource(psurf->texture);
 391         struct fd_resource_slice *slice = fd_resource_slice(rsc, psurf->u.tex.level);
 392
 393         uint32_t offset = fd_resource_offset(rsc, psurf->u.tex.level,
 394                                                                                  psurf->u.tex.first_layer);
 395         uint32_t stride = slice->pitch * rsc->cpp;
 396
 397         enum a6xx_color_fmt format = fd6_pipe2color(pfmt);
 398         OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
 399         OUT_RING(ring,
 400                          A6XX_RB_2D_DST_INFO_COLOR_FORMAT(format) |
 401                          A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 402                          A6XX_RB_2D_DST_INFO_COLOR_SWAP(WXYZ));
 403         OUT_RELOCW(ring, rsc->bo, offset, 0, 0);  /* RB_2D_DST_LO/HI */
 404         OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(stride));
 405         OUT_RING(ring, 0);
 406         OUT_RING(ring, 0);
 407         OUT_RING(ring, 0);
 408         OUT_RING(ring, 0);
 409         OUT_RING(ring, 0);
 410
 411         OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
 412         OUT_RING(ring, 0);
 413         OUT_RING(ring, 0);
 414         OUT_RING(ring, 0);
 415         OUT_RING(ring, 0);
 416
 417         OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
 418         OUT_RING(ring,
 419                          A6XX_GRAS_2D_DST_TL_X(ctx->batch->max_scissor.minx) |
 420                          A6XX_GRAS_2D_DST_TL_Y(ctx->batch->max_scissor.miny));
 421         OUT_RING(ring,
 422                          A6XX_GRAS_2D_DST_BR_X(ctx->batch->max_scissor.maxx) |
 423                          A6XX_GRAS_2D_DST_BR_Y(ctx->batch->max_scissor.maxy));
 424
 425         OUT_PKT7(ring, CP_BLIT, 1);
 426         OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
 427 }
 428 #endif
 429
 430 static bool
 431 fd6_clear(struct fd_context *ctx, unsigned buffers,
 432                 const union pipe_color_union *color, double depth, unsigned stencil)
 433 {
 434         struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
 435         struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
 436         struct fd_ringbuffer *ring = ctx->batch->draw;
 437
 438         if ((buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) &&
 439                         is_z32(pfb->zsbuf->format))
 440                 return false;
 441
 442         fd6_emit_render_cntl(ctx, true, false);
 443
 444         OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
 445         OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_TL_X(scissor->minx) |
 446                          A6XX_RB_BLIT_SCISSOR_TL_Y(scissor->miny));
 447         OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_BR_X(scissor->maxx - 1) |
 448                          A6XX_RB_BLIT_SCISSOR_BR_Y(scissor->maxy - 1));
 449
 450         if (buffers & PIPE_CLEAR_COLOR) {
 451                 for (int i = 0; i < pfb->nr_cbufs; i++) {
 452                         union util_color uc = {0};
 453
 454                         if (!pfb->cbufs[i])
 455                                 continue;
 456
 457                         if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
 458                                 continue;
 459
 460                         enum pipe_format pfmt = pfb->cbufs[i]->format;
 461
 462                         // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
 463                         union pipe_color_union swapped;
 464                         switch (fd6_pipe2swap(pfmt)) {
 465                         case WZYX:
 466                                 swapped.ui[0] = color->ui[0];
 467                                 swapped.ui[1] = color->ui[1];
 468                                 swapped.ui[2] = color->ui[2];
 469                                 swapped.ui[3] = color->ui[3];
 470                                 break;
 471                         case WXYZ:
 472                                 swapped.ui[2] = color->ui[0];
 473                                 swapped.ui[1] = color->ui[1];
 474                                 swapped.ui[0] = color->ui[2];
 475                                 swapped.ui[3] = color->ui[3];
 476                                 break;
 477                         case ZYXW:
 478                                 swapped.ui[3] = color->ui[0];
 479                                 swapped.ui[0] = color->ui[1];
 480                                 swapped.ui[1] = color->ui[2];
 481                                 swapped.ui[2] = color->ui[3];
 482                                 break;
 483                         case XYZW:
 484                                 swapped.ui[3] = color->ui[0];
 485                                 swapped.ui[2] = color->ui[1];
 486                                 swapped.ui[1] = color->ui[2];
 487                                 swapped.ui[0] = color->ui[3];
 488                                 break;
 489                         }
 490
 491                         if (util_format_is_pure_uint(pfmt)) {
 492                                 util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
 493                         } else if (util_format_is_pure_sint(pfmt)) {
 494                                 util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
 495                         } else {
 496                                 util_pack_color(swapped.f, pfmt, &uc);
 497                         }
 498
 499                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
 500                         OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 501                                 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
 502
 503                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
 504                         OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
 505                                 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
 506
 507                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
 508                         OUT_RINGP(ring, i, &ctx->batch->gmem_patches);
 509
 510                         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
 511                         OUT_RING(ring, 0);
 512
 513                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
 514                         OUT_RING(ring, uc.ui[0]);
 515                         OUT_RING(ring, uc.ui[1]);
 516                         OUT_RING(ring, uc.ui[2]);
 517                         OUT_RING(ring, uc.ui[3]);
 518
 519                         fd6_emit_blit(ctx, ring);
 520                 }
 521         }
 522
 523         if (pfb->zsbuf && (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))) {
 524                 enum pipe_format pfmt = pfb->zsbuf->format;
 525                 uint32_t clear = util_pack_z_stencil(pfmt, depth, stencil);
 526                 uint32_t mask = 0;
 527
 528                 if (buffers & PIPE_CLEAR_DEPTH)
 529                         mask |= 0x1;
 530
 531                 if (buffers & PIPE_CLEAR_STENCIL)
 532                         mask |= 0x2;
 533
 534                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
 535                 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 536                         A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
 537
 538                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
 539                 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
 540                         // XXX UNK0 for separate stencil ??
 541                         A6XX_RB_BLIT_INFO_DEPTH |
 542                         A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
 543
 544                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
 545                 OUT_RINGP(ring, MAX_RENDER_TARGETS, &ctx->batch->gmem_patches);
 546
 547                 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
 548                 OUT_RING(ring, 0);
 549
 550                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
 551                 OUT_RING(ring, clear);
 552
 553                 fd6_emit_blit(ctx, ring);
 554
 555 #if 0
 556                 if (pfb->zsbuf && (buffers & PIPE_CLEAR_DEPTH)) {
 557                         struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
 558                         if (zsbuf->lrz) {
 559                                 zsbuf->lrz_valid = true;
 560                                 fd6_clear_lrz(ctx->batch, zsbuf, depth);
 561                         }
 562                 }
 563 #endif
 564         }
 565
 566         return true;
 567 }
 568
 569 void
 570 fd6_draw_init(struct pipe_context *pctx)
 571 {
 572         struct fd_context *ctx = fd_context(pctx);
 573         ctx->draw_vbo = fd6_draw_vbo;
 574         ctx->clear = fd6_clear;
 575 }