src/gallium/drivers/freedreno/a6xx/fd6_draw.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #include "pipe/p_state.h"
  29 #include "util/u_string.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_prim.h"
  32
  33 #include "freedreno_state.h"
  34 #include "freedreno_resource.h"
  35
  36 #include "fd6_draw.h"
  37 #include "fd6_context.h"
  38 #include "fd6_emit.h"
  39 #include "fd6_program.h"
  40 #include "fd6_format.h"
  41 #include "fd6_zsa.h"
  42
  43 /* some bits in common w/ a4xx: */
  44 #include "a4xx/fd4_draw.h"
  45
  46 static void
  47 draw_emit_indirect(struct fd_batch *batch, struct fd_ringbuffer *ring,
  48                                    enum pc_di_primtype primtype,
  49                                    enum pc_di_vis_cull_mode vismode,
  50                                    const struct pipe_draw_info *info,
  51                                    unsigned index_offset)
  52 {
  53         struct fd_resource *ind = fd_resource(info->indirect->buffer);
  54
  55         if (info->index_size) {
  56                 struct pipe_resource *idx = info->index.resource;
  57                 unsigned max_indicies = (idx->width0 - info->indirect->offset) /
  58                         info->index_size;
  59
  60                 OUT_PKT7(ring, CP_DRAW_INDX_INDIRECT, 6);
  61                 OUT_RINGP(ring, DRAW4(primtype, DI_SRC_SEL_DMA,
  62                                                           fd4_size2indextype(info->index_size), 0),
  63                                   &batch->draw_patches);
  64                 OUT_RELOC(ring, fd_resource(idx)->bo,
  65                                   index_offset, 0, 0);
  66                 // XXX: Check A5xx vs A6xx
  67                 OUT_RING(ring, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies));
  68                 OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
  69         } else {
  70                 OUT_PKT7(ring, CP_DRAW_INDIRECT, 3);
  71                 OUT_RINGP(ring, DRAW4(primtype, DI_SRC_SEL_AUTO_INDEX, 0, 0),
  72                                   &batch->draw_patches);
  73                 OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
  74         }
  75 }
  76
  77 static void
  78 draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring,
  79                   enum pc_di_primtype primtype,
  80                   enum pc_di_vis_cull_mode vismode,
  81                   const struct pipe_draw_info *info,
  82                   unsigned index_offset)
  83 {
  84         if (info->index_size) {
  85                 assert(!info->has_user_indices);
  86
  87                 struct pipe_resource *idx_buffer = info->index.resource;
  88                 uint32_t idx_size = info->index_size * info->count;
  89                 uint32_t idx_offset = index_offset + info->start * info->index_size;
  90
  91                 /* leave vis mode blank for now, it will be patched up when
  92                  * we know if we are binning or not
  93                  */
  94                 uint32_t draw = CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
  95                         CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
  96                         CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(fd4_size2indextype(info->index_size)) |
  97                         0x2000;
  98
  99                 OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, 7);
 100                 if (vismode == USE_VISIBILITY) {
 101                         OUT_RINGP(ring, draw, &batch->draw_patches);
 102                 } else {
 103                         OUT_RING(ring, draw);
 104                 }
 105                 OUT_RING(ring, info->instance_count);    /* NumInstances */
 106                 OUT_RING(ring, info->count);             /* NumIndices */
 107                 OUT_RING(ring, 0x0);           /* XXX */
 108                 OUT_RELOC(ring, fd_resource(idx_buffer)->bo, idx_offset, 0, 0);
 109                 OUT_RING (ring, idx_size);
 110         } else {
 111                 /* leave vis mode blank for now, it will be patched up when
 112                  * we know if we are binning or not
 113                  */
 114                 uint32_t draw = CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
 115                         CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
 116                         0x2000;
 117
 118                 OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, 3);
 119                 if (vismode == USE_VISIBILITY) {
 120                         OUT_RINGP(ring, draw, &batch->draw_patches);
 121                 } else {
 122                         OUT_RING(ring, draw);
 123                 }
 124                 OUT_RING(ring, info->instance_count);    /* NumInstances */
 125                 OUT_RING(ring, info->count);             /* NumIndices */
 126         }
 127 }
 128
 129 static void
 130 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
 131                 struct fd6_emit *emit, unsigned index_offset)
 132 {
 133         const struct pipe_draw_info *info = emit->info;
 134         enum pc_di_primtype primtype = ctx->primtypes[info->mode];
 135
 136         fd6_emit_state(ctx, ring, emit);
 137
 138         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
 139                 fd6_emit_vertex_bufs(ring, emit);
 140
 141         OUT_PKT4(ring, REG_A6XX_VFD_INDEX_OFFSET, 2);
 142         OUT_RING(ring, info->index_size ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
 143         OUT_RING(ring, info->start_instance);   /* VFD_INSTANCE_START_OFFSET */
 144
 145         OUT_PKT4(ring, REG_A6XX_PC_RESTART_INDEX, 1);
 146         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
 147                         info->restart_index : 0xffffffff);
 148
 149         /* for debug after a lock up, write a unique counter value
 150          * to scratch7 for each draw, to make it easier to match up
 151          * register dumps to cmdstream.  The combination of IB
 152          * (scratch6) and DRAW is enough to "triangulate" the
 153          * particular draw that caused lockup.
 154          */
 155         emit_marker6(ring, 7);
 156
 157         if (info->indirect) {
 158                 draw_emit_indirect(ctx->batch, ring, primtype,
 159                                                    emit->binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
 160                                                    info, index_offset);
 161         } else {
 162                 draw_emit(ctx->batch, ring, primtype,
 163                                   emit->binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
 164                                   info, index_offset);
 165         }
 166
 167         emit_marker6(ring, 7);
 168         fd_reset_wfi(ctx->batch);
 169 }
 170
 171 /* fixup dirty shader state in case some "unrelated" (from the state-
 172  * tracker's perspective) state change causes us to switch to a
 173  * different variant.
 174  */
 175 static void
 176 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
 177 {
 178         struct fd6_context *fd6_ctx = fd6_context(ctx);
 179         struct ir3_shader_key *last_key = &fd6_ctx->last_key;
 180
 181         if (!ir3_shader_key_equal(last_key, key)) {
 182                 if (ir3_shader_key_changes_fs(last_key, key)) {
 183                         ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG;
 184                         ctx->dirty |= FD_DIRTY_PROG;
 185                 }
 186
 187                 if (ir3_shader_key_changes_vs(last_key, key)) {
 188                         ctx->dirty_shader[PIPE_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG;
 189                         ctx->dirty |= FD_DIRTY_PROG;
 190                 }
 191
 192                 fd6_ctx->last_key = *key;
 193         }
 194 }
 195
 196 static bool
 197 fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
 198              unsigned index_offset)
 199 {
 200         struct fd6_context *fd6_ctx = fd6_context(ctx);
 201         struct fd6_emit emit = {
 202                 .ctx = ctx,
 203                 .vtx  = &ctx->vtx,
 204                 .info = info,
 205                 .key = {
 206                         .vs = ctx->prog.vp,
 207                         .fs = ctx->prog.fp,
 208                         .key = {
 209                                 .color_two_side = ctx->rasterizer->light_twoside,
 210                                 .vclamp_color = ctx->rasterizer->clamp_vertex_color,
 211                                 .fclamp_color = ctx->rasterizer->clamp_fragment_color,
 212                                 .rasterflat = ctx->rasterizer->flatshade,
 213                                 .ucp_enables = ctx->rasterizer->clip_plane_enable,
 214                                 .has_per_samp = (fd6_ctx->fsaturate || fd6_ctx->vsaturate ||
 215                                                 fd6_ctx->fastc_srgb || fd6_ctx->vastc_srgb),
 216                                 .vsaturate_s = fd6_ctx->vsaturate_s,
 217                                 .vsaturate_t = fd6_ctx->vsaturate_t,
 218                                 .vsaturate_r = fd6_ctx->vsaturate_r,
 219                                 .fsaturate_s = fd6_ctx->fsaturate_s,
 220                                 .fsaturate_t = fd6_ctx->fsaturate_t,
 221                                 .fsaturate_r = fd6_ctx->fsaturate_r,
 222                                 .vastc_srgb = fd6_ctx->vastc_srgb,
 223                                 .fastc_srgb = fd6_ctx->fastc_srgb,
 224                                 .vsamples = ctx->tex[PIPE_SHADER_VERTEX].samples,
 225                                 .fsamples = ctx->tex[PIPE_SHADER_FRAGMENT].samples,
 226                         }
 227                 },
 228                 .rasterflat = ctx->rasterizer->flatshade,
 229                 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 230                 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 231         };
 232
 233         fixup_shader_state(ctx, &emit.key.key);
 234
 235         unsigned dirty = ctx->dirty;
 236
 237         if (!(dirty & FD_DIRTY_PROG)) {
 238                 emit.prog = fd6_ctx->prog;
 239         } else {
 240                 fd6_ctx->prog = fd6_emit_get_prog(&emit);
 241         }
 242
 243         emit.vs = fd6_emit_get_prog(&emit)->vs;
 244         emit.fs = fd6_emit_get_prog(&emit)->fs;
 245
 246         const struct ir3_shader_variant *vp = emit.vs;
 247         const struct ir3_shader_variant *fp = emit.fs;
 248
 249         /* do regular pass first, since that is more likely to fail compiling: */
 250
 251         if (!vp || !fp)
 252                 return false;
 253
 254         ctx->stats.vs_regs += ir3_shader_halfregs(vp);
 255         ctx->stats.fs_regs += ir3_shader_halfregs(fp);
 256
 257         /* figure out whether we need to disable LRZ write for binning
 258          * pass using draw pass's fp:
 259          */
 260         emit.no_lrz_write = fp->writes_pos || fp->has_kill;
 261
 262         emit.binning_pass = false;
 263         emit.dirty = dirty;
 264
 265         draw_impl(ctx, ctx->batch->draw, &emit, index_offset);
 266
 267         /* and now binning pass: */
 268         emit.binning_pass = true;
 269         emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 270         emit.vs = fd6_emit_get_prog(&emit)->bs;
 271
 272         draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
 273
 274         if (emit.streamout_mask) {
 275                 struct fd_ringbuffer *ring = ctx->batch->draw;
 276
 277                 for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
 278                         if (emit.streamout_mask & (1 << i)) {
 279                                 fd6_event_write(ctx->batch, ring, FLUSH_SO_0 + i, false);
 280                         }
 281                 }
 282         }
 283
 284         fd_context_all_clean(ctx);
 285
 286         return true;
 287 }
 288
 289 static bool is_z32(enum pipe_format format)
 290 {
 291         switch (format) {
 292         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 293         case PIPE_FORMAT_Z32_UNORM:
 294         case PIPE_FORMAT_Z32_FLOAT:
 295                 return true;
 296         default:
 297                 return false;
 298         }
 299 }
 300
 301 static void
 302 fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
 303 {
 304         struct fd_ringbuffer *ring;
 305
 306         // TODO mid-frame clears (ie. app doing crazy stuff)??  Maybe worth
 307         // splitting both clear and lrz clear out into their own rb's.  And
 308         // just throw away any draws prior to clear.  (Anything not fullscreen
 309         // clear, just fallback to generic path that treats it as a normal
 310         // draw
 311
 312         if (!batch->lrz_clear) {
 313                 batch->lrz_clear = fd_ringbuffer_new(batch->ctx->pipe, 0x1000);
 314                 fd_ringbuffer_set_parent(batch->lrz_clear, batch->gmem);
 315         }
 316
 317         ring = batch->lrz_clear;
 318
 319         emit_marker6(ring, 7);
 320         OUT_PKT7(ring, CP_SET_MARKER, 1);
 321         OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
 322         emit_marker6(ring, 7);
 323
 324         OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
 325         OUT_RING(ring, 0x10000000);
 326
 327         OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
 328         OUT_RING(ring, 0x7ffff);
 329
 330         emit_marker6(ring, 7);
 331         OUT_PKT7(ring, CP_SET_MARKER, 1);
 332         OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0xc));
 333         emit_marker6(ring, 7);
 334
 335         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
 336         OUT_RING(ring, 0x0);
 337
 338         OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 13);
 339         OUT_RING(ring, 0x00000000);
 340         OUT_RING(ring, 0x00000000);
 341         OUT_RING(ring, 0x00000000);
 342         OUT_RING(ring, 0x00000000);
 343         OUT_RING(ring, 0x00000000);
 344         OUT_RING(ring, 0x00000000);
 345         OUT_RING(ring, 0x00000000);
 346         OUT_RING(ring, 0x00000000);
 347         OUT_RING(ring, 0x00000000);
 348         OUT_RING(ring, 0x00000000);
 349         OUT_RING(ring, 0x00000000);
 350         OUT_RING(ring, 0x00000000);
 351         OUT_RING(ring, 0x00000000);
 352
 353         OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_ACC0, 1);
 354         OUT_RING(ring, 0x0000f410);
 355
 356         OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
 357         OUT_RING(ring, A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(RB6_R16_UNORM) |
 358                         0x4f00080);
 359
 360         OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
 361         OUT_RING(ring, A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(RB6_R16_UNORM) |
 362                         0x4f00080);
 363
 364         fd6_event_write(batch, ring, UNK_1D, true);
 365         fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
 366
 367         OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
 368         OUT_RING(ring, fui(depth));
 369         OUT_RING(ring, 0x00000000);
 370         OUT_RING(ring, 0x00000000);
 371         OUT_RING(ring, 0x00000000);
 372
 373         OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
 374         OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(RB6_R16_UNORM) |
 375                         A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 376                         A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
 377         OUT_RELOCW(ring, zsbuf->lrz, 0, 0, 0);
 378         OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(zsbuf->lrz_pitch * 2));
 379         OUT_RING(ring, 0x00000000);
 380         OUT_RING(ring, 0x00000000);
 381         OUT_RING(ring, 0x00000000);
 382         OUT_RING(ring, 0x00000000);
 383         OUT_RING(ring, 0x00000000);
 384
 385         OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
 386         OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(0));
 387         OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(0));
 388         OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(0));
 389         OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(0));
 390
 391         OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
 392         OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) |
 393                         A6XX_GRAS_2D_DST_TL_Y(0));
 394         OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(zsbuf->lrz_width - 1) |
 395                         A6XX_GRAS_2D_DST_BR_Y(zsbuf->lrz_height - 1));
 396
 397         fd6_event_write(batch, ring, 0x3f, false);
 398
 399         OUT_WFI5(ring);
 400
 401         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
 402         OUT_RING(ring, 0x1000000);
 403
 404         OUT_PKT7(ring, CP_BLIT, 1);
 405         OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
 406
 407         OUT_WFI5(ring);
 408
 409         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
 410         OUT_RING(ring, 0x0);
 411
 412         fd6_event_write(batch, ring, UNK_1D, true);
 413         fd6_event_write(batch, ring, FACENESS_FLUSH, true);
 414         fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
 415
 416         fd6_cache_flush(batch, ring);
 417 }
 418
 419 static bool
 420 fd6_clear(struct fd_context *ctx, unsigned buffers,
 421                 const union pipe_color_union *color, double depth, unsigned stencil)
 422 {
 423         struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
 424         struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
 425         struct fd_ringbuffer *ring = ctx->batch->draw;
 426
 427         if ((buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) &&
 428                         is_z32(pfb->zsbuf->format))
 429                 return false;
 430
 431         OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
 432         OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_TL_X(scissor->minx) |
 433                          A6XX_RB_BLIT_SCISSOR_TL_Y(scissor->miny));
 434         OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_BR_X(scissor->maxx - 1) |
 435                          A6XX_RB_BLIT_SCISSOR_BR_Y(scissor->maxy - 1));
 436
 437         if (buffers & PIPE_CLEAR_COLOR) {
 438                 for (int i = 0; i < pfb->nr_cbufs; i++) {
 439                         union util_color uc = {0};
 440
 441                         if (!pfb->cbufs[i])
 442                                 continue;
 443
 444                         if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
 445                                 continue;
 446
 447                         enum pipe_format pfmt = pfb->cbufs[i]->format;
 448
 449                         // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
 450                         union pipe_color_union swapped;
 451                         switch (fd6_pipe2swap(pfmt)) {
 452                         case WZYX:
 453                                 swapped.ui[0] = color->ui[0];
 454                                 swapped.ui[1] = color->ui[1];
 455                                 swapped.ui[2] = color->ui[2];
 456                                 swapped.ui[3] = color->ui[3];
 457                                 break;
 458                         case WXYZ:
 459                                 swapped.ui[2] = color->ui[0];
 460                                 swapped.ui[1] = color->ui[1];
 461                                 swapped.ui[0] = color->ui[2];
 462                                 swapped.ui[3] = color->ui[3];
 463                                 break;
 464                         case ZYXW:
 465                                 swapped.ui[3] = color->ui[0];
 466                                 swapped.ui[0] = color->ui[1];
 467                                 swapped.ui[1] = color->ui[2];
 468                                 swapped.ui[2] = color->ui[3];
 469                                 break;
 470                         case XYZW:
 471                                 swapped.ui[3] = color->ui[0];
 472                                 swapped.ui[2] = color->ui[1];
 473                                 swapped.ui[1] = color->ui[2];
 474                                 swapped.ui[0] = color->ui[3];
 475                                 break;
 476                         }
 477
 478                         if (util_format_is_pure_uint(pfmt)) {
 479                                 util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
 480                         } else if (util_format_is_pure_sint(pfmt)) {
 481                                 util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
 482                         } else {
 483                                 util_pack_color(swapped.f, pfmt, &uc);
 484                         }
 485
 486                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
 487                         OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 488                                 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
 489
 490                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
 491                         OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
 492                                 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
 493
 494                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
 495                         OUT_RINGP(ring, i, &ctx->batch->gmem_patches);
 496
 497                         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
 498                         OUT_RING(ring, 0);
 499
 500                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
 501                         OUT_RING(ring, uc.ui[0]);
 502                         OUT_RING(ring, uc.ui[1]);
 503                         OUT_RING(ring, uc.ui[2]);
 504                         OUT_RING(ring, uc.ui[3]);
 505
 506                         fd6_emit_blit(ctx->batch, ring);
 507                 }
 508         }
 509
 510         if (pfb->zsbuf && (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))) {
 511                 enum pipe_format pfmt = pfb->zsbuf->format;
 512                 uint32_t clear = util_pack_z_stencil(pfmt, depth, stencil);
 513                 uint32_t mask = 0;
 514
 515                 if (buffers & PIPE_CLEAR_DEPTH)
 516                         mask |= 0x1;
 517
 518                 if (buffers & PIPE_CLEAR_STENCIL)
 519                         mask |= 0x2;
 520
 521                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
 522                 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 523                         A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
 524
 525                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
 526                 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
 527                         // XXX UNK0 for separate stencil ??
 528                         A6XX_RB_BLIT_INFO_DEPTH |
 529                         A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
 530
 531                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
 532                 OUT_RINGP(ring, MAX_RENDER_TARGETS, &ctx->batch->gmem_patches);
 533
 534                 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
 535                 OUT_RING(ring, 0);
 536
 537                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
 538                 OUT_RING(ring, clear);
 539
 540                 fd6_emit_blit(ctx->batch, ring);
 541
 542                 if (pfb->zsbuf && (buffers & PIPE_CLEAR_DEPTH)) {
 543                         struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
 544                         if (zsbuf->lrz) {
 545                                 zsbuf->lrz_valid = true;
 546                                 fd6_clear_lrz(ctx->batch, zsbuf, depth);
 547                         }
 548                 }
 549         }
 550
 551         return true;
 552 }
 553
 554 void
 555 fd6_draw_init(struct pipe_context *pctx)
 556 {
 557         struct fd_context *ctx = fd_context(pctx);
 558         ctx->draw_vbo = fd6_draw_vbo;
 559         ctx->clear = fd6_clear;
 560 }