src/gallium/drivers/freedreno/a6xx/fd6_draw.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #include "pipe/p_state.h"
  29 #include "util/u_string.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_prim.h"
  32
  33 #include "freedreno_state.h"
  34 #include "freedreno_resource.h"
  35
  36 #include "fd6_draw.h"
  37 #include "fd6_context.h"
  38 #include "fd6_emit.h"
  39 #include "fd6_program.h"
  40 #include "fd6_format.h"
  41 #include "fd6_zsa.h"
  42
  43 /* some bits in common w/ a4xx: */
  44 #include "a4xx/fd4_draw.h"
  45
  46 static void
  47 draw_emit_indirect(struct fd_batch *batch, struct fd_ringbuffer *ring,
  48                                    enum pc_di_primtype primtype,
  49                                    enum pc_di_vis_cull_mode vismode,
  50                                    const struct pipe_draw_info *info,
  51                                    unsigned index_offset)
  52 {
  53         struct fd_resource *ind = fd_resource(info->indirect->buffer);
  54
  55         if (info->index_size) {
  56                 struct pipe_resource *idx = info->index.resource;
  57                 unsigned max_indicies = (idx->width0 - info->indirect->offset) /
  58                         info->index_size;
  59
  60                 OUT_PKT7(ring, CP_DRAW_INDX_INDIRECT, 6);
  61                 OUT_RINGP(ring, DRAW4(primtype, DI_SRC_SEL_DMA,
  62                                                           fd4_size2indextype(info->index_size), 0),
  63                                   &batch->draw_patches);
  64                 OUT_RELOC(ring, fd_resource(idx)->bo,
  65                                   index_offset, 0, 0);
  66                 // XXX: Check A5xx vs A6xx
  67                 OUT_RING(ring, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies));
  68                 OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
  69         } else {
  70                 OUT_PKT7(ring, CP_DRAW_INDIRECT, 3);
  71                 OUT_RINGP(ring, DRAW4(primtype, DI_SRC_SEL_AUTO_INDEX, 0, 0),
  72                                   &batch->draw_patches);
  73                 OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
  74         }
  75 }
  76
  77 static void
  78 draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring,
  79                   enum pc_di_primtype primtype,
  80                   enum pc_di_vis_cull_mode vismode,
  81                   const struct pipe_draw_info *info,
  82                   unsigned index_offset)
  83 {
  84         struct pipe_resource *idx_buffer = NULL;
  85         enum a4xx_index_size idx_type;
  86         enum pc_di_src_sel src_sel;
  87         uint32_t idx_size, idx_offset;
  88
  89         if (info->index_size) {
  90                 assert(!info->has_user_indices);
  91
  92                 idx_buffer = info->index.resource;
  93                 idx_type = fd4_size2indextype(info->index_size);
  94                 idx_size = info->index_size * info->count;
  95                 idx_offset = index_offset + info->start * info->index_size;
  96                 src_sel = DI_SRC_SEL_DMA;
  97         } else {
  98                 idx_buffer = NULL;
  99                 idx_type = INDEX4_SIZE_32_BIT;
 100                 idx_size = 0;
 101                 idx_offset = 0;
 102                 src_sel = DI_SRC_SEL_AUTO_INDEX;
 103         }
 104
 105         OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, idx_buffer ? 7 : 3);
 106         if (vismode == USE_VISIBILITY) {
 107                 /* leave vis mode blank for now, it will be patched up when
 108                  * we know if we are binning or not
 109                  */
 110                 OUT_RINGP(ring, DRAW4(primtype, src_sel, idx_type, 0) | 0x2000,
 111                                 &batch->draw_patches);
 112         } else {
 113                 OUT_RING(ring, DRAW4(primtype, src_sel, idx_type, vismode) | 0x2000);
 114         }
 115         OUT_RING(ring, info->instance_count);    /* NumInstances */
 116         OUT_RING(ring, info->count);             /* NumIndices */
 117         if (idx_buffer) {
 118                 OUT_RING(ring, 0x0);           /* XXX */
 119                 OUT_RELOC(ring, fd_resource(idx_buffer)->bo, idx_offset, 0, 0);
 120                 OUT_RING (ring, idx_size);
 121         }
 122 }
 123
 124 static void
 125 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
 126                 struct fd6_emit *emit, unsigned index_offset)
 127 {
 128         const struct pipe_draw_info *info = emit->info;
 129         enum pc_di_primtype primtype = ctx->primtypes[info->mode];
 130
 131         fd6_emit_state(ctx, ring, emit);
 132
 133         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
 134                 fd6_emit_vertex_bufs(ring, emit);
 135
 136         OUT_PKT4(ring, REG_A6XX_VFD_INDEX_OFFSET, 2);
 137         OUT_RING(ring, info->index_size ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
 138         OUT_RING(ring, info->start_instance);   /* VFD_INSTANCE_START_OFFSET */
 139
 140         OUT_PKT4(ring, REG_A6XX_PC_RESTART_INDEX, 1);
 141         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
 142                         info->restart_index : 0xffffffff);
 143
 144         fd6_emit_render_cntl(ctx, false, emit->key.binning_pass);
 145
 146         /* for debug after a lock up, write a unique counter value
 147          * to scratch7 for each draw, to make it easier to match up
 148          * register dumps to cmdstream.  The combination of IB
 149          * (scratch6) and DRAW is enough to "triangulate" the
 150          * particular draw that caused lockup.
 151          */
 152         emit_marker6(ring, 7);
 153
 154         if (info->indirect) {
 155                 draw_emit_indirect(ctx->batch, ring, primtype,
 156                                                    emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
 157                                                    info, index_offset);
 158         } else {
 159                 draw_emit(ctx->batch, ring, primtype,
 160                                   emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
 161                                   info, index_offset);
 162         }
 163
 164         emit_marker6(ring, 7);
 165         fd_reset_wfi(ctx->batch);
 166 }
 167
 168 /* fixup dirty shader state in case some "unrelated" (from the state-
 169  * tracker's perspective) state change causes us to switch to a
 170  * different variant.
 171  */
 172 static void
 173 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
 174 {
 175         struct fd6_context *fd6_ctx = fd6_context(ctx);
 176         struct ir3_shader_key *last_key = &fd6_ctx->last_key;
 177
 178         if (!ir3_shader_key_equal(last_key, key)) {
 179                 if (ir3_shader_key_changes_fs(last_key, key)) {
 180                         ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG;
 181                         ctx->dirty |= FD_DIRTY_PROG;
 182                 }
 183
 184                 if (ir3_shader_key_changes_vs(last_key, key)) {
 185                         ctx->dirty_shader[PIPE_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG;
 186                         ctx->dirty |= FD_DIRTY_PROG;
 187                 }
 188
 189                 fd6_ctx->last_key = *key;
 190         }
 191 }
 192
 193 static bool
 194 fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
 195              unsigned index_offset)
 196 {
 197         struct fd6_context *fd6_ctx = fd6_context(ctx);
 198         struct fd6_emit emit = {
 199                 .debug = &ctx->debug,
 200                 .vtx  = &ctx->vtx,
 201                 .prog = &ctx->prog,
 202                 .info = info,
 203                 .key = {
 204                         .color_two_side = ctx->rasterizer->light_twoside,
 205                         .vclamp_color = ctx->rasterizer->clamp_vertex_color,
 206                         .fclamp_color = ctx->rasterizer->clamp_fragment_color,
 207                         .rasterflat = ctx->rasterizer->flatshade,
 208                         .half_precision = ctx->in_blit &&
 209                                         fd_half_precision(&ctx->batch->framebuffer),
 210                         .ucp_enables = ctx->rasterizer->clip_plane_enable,
 211                         .has_per_samp = (fd6_ctx->fsaturate || fd6_ctx->vsaturate ||
 212                                         fd6_ctx->fastc_srgb || fd6_ctx->vastc_srgb),
 213                         .vsaturate_s = fd6_ctx->vsaturate_s,
 214                         .vsaturate_t = fd6_ctx->vsaturate_t,
 215                         .vsaturate_r = fd6_ctx->vsaturate_r,
 216                         .fsaturate_s = fd6_ctx->fsaturate_s,
 217                         .fsaturate_t = fd6_ctx->fsaturate_t,
 218                         .fsaturate_r = fd6_ctx->fsaturate_r,
 219                         .vastc_srgb = fd6_ctx->vastc_srgb,
 220                         .fastc_srgb = fd6_ctx->fastc_srgb,
 221                         .vsamples = ctx->tex[PIPE_SHADER_VERTEX].samples,
 222                         .fsamples = ctx->tex[PIPE_SHADER_FRAGMENT].samples,
 223                 },
 224                 .rasterflat = ctx->rasterizer->flatshade,
 225                 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 226                 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 227         };
 228
 229         fixup_shader_state(ctx, &emit.key);
 230
 231         unsigned dirty = ctx->dirty;
 232         const struct ir3_shader_variant *vp = fd6_emit_get_vp(&emit);
 233         const struct ir3_shader_variant *fp = fd6_emit_get_fp(&emit);
 234
 235         /* do regular pass first, since that is more likely to fail compiling: */
 236
 237         if (!vp || !fp)
 238                 return false;
 239
 240         ctx->stats.vs_regs += ir3_shader_halfregs(vp);
 241         ctx->stats.fs_regs += ir3_shader_halfregs(fp);
 242
 243         /* figure out whether we need to disable LRZ write for binning
 244          * pass using draw pass's fp:
 245          */
 246         emit.no_lrz_write = fp->writes_pos || fp->has_kill;
 247
 248         emit.key.binning_pass = false;
 249         emit.dirty = dirty;
 250
 251         draw_impl(ctx, ctx->batch->draw, &emit, index_offset);
 252
 253         /* and now binning pass: */
 254         emit.key.binning_pass = true;
 255         emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 256         emit.vp = NULL;   /* we changed key so need to refetch vp */
 257         emit.fp = NULL;
 258         draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
 259
 260         if (emit.streamout_mask) {
 261                 struct fd_ringbuffer *ring = ctx->batch->draw;
 262
 263                 for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
 264                         if (emit.streamout_mask & (1 << i)) {
 265                                 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 266                                 OUT_RING(ring, FLUSH_SO_0 + i);
 267                         }
 268                 }
 269         }
 270
 271         fd_context_all_clean(ctx);
 272
 273         return true;
 274 }
 275
 276 static bool is_z32(enum pipe_format format)
 277 {
 278         switch (format) {
 279         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 280         case PIPE_FORMAT_Z32_UNORM:
 281         case PIPE_FORMAT_Z32_FLOAT:
 282                 return true;
 283         default:
 284                 return false;
 285         }
 286 }
 287
 288 #if 0
 289 static void
 290 fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
 291 {
 292         struct fd_ringbuffer *ring;
 293         uint32_t clear = util_pack_z(PIPE_FORMAT_Z16_UNORM, depth);
 294
 295         // TODO mid-frame clears (ie. app doing crazy stuff)??  Maybe worth
 296         // splitting both clear and lrz clear out into their own rb's.  And
 297         // just throw away any draws prior to clear.  (Anything not fullscreen
 298         // clear, just fallback to generic path that treats it as a normal
 299         // draw
 300
 301         if (!batch->lrz_clear) {
 302                 batch->lrz_clear = fd_ringbuffer_new(batch->ctx->pipe, 0x1000);
 303                 fd_ringbuffer_set_parent(batch->lrz_clear, batch->gmem);
 304         }
 305
 306         ring = batch->lrz_clear;
 307
 308         OUT_WFI5(ring);
 309
 310         OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
 311         OUT_RING(ring, 0x10000000);
 312
 313         OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
 314         OUT_RING(ring, 0x20fffff);
 315
 316         OUT_PKT4(ring, REG_A6XX_GRAS_SU_CNTL, 1);
 317         OUT_RING(ring, A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(0.0));
 318
 319         OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
 320         OUT_RING(ring, 0x00000000);
 321
 322         OUT_PKT4(ring, REG_A6XX_GRAS_CL_CNTL, 1);
 323         OUT_RING(ring, 0x00000181);
 324
 325         OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
 326         OUT_RING(ring, 0x00000000);
 327
 328         OUT_PKT4(ring, REG_A6XX_RB_MRT_BUF_INFO(0), 5);
 329         OUT_RING(ring, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(RB5_R16_UNORM) |
 330                         A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(TILE6_LINEAR) |
 331                         A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX));
 332         OUT_RING(ring, A6XX_RB_MRT_PITCH(zsbuf->lrz_pitch * 2));
 333         OUT_RING(ring, A6XX_RB_MRT_ARRAY_PITCH(fd_bo_size(zsbuf->lrz)));
 334         OUT_RELOCW(ring, zsbuf->lrz, 0x1000, 0, 0);
 335
 336         OUT_PKT4(ring, REG_A6XX_RB_RENDER_CNTL, 1);
 337         OUT_RING(ring, 0x00000000);
 338
 339         OUT_PKT4(ring, REG_A6XX_RB_DEST_MSAA_CNTL, 1);
 340         OUT_RING(ring, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE));
 341
 342         OUT_PKT4(ring, REG_A6XX_RB_BLIT_CNTL, 1);
 343         OUT_RING(ring, A6XX_RB_BLIT_CNTL_BUF(BLIT_MRT0));
 344
 345         OUT_PKT4(ring, REG_A6XX_RB_CLEAR_CNTL, 1);
 346         OUT_RING(ring, A6XX_RB_CLEAR_CNTL_FAST_CLEAR |
 347                         A6XX_RB_CLEAR_CNTL_MASK(0xf));
 348
 349         OUT_PKT4(ring, REG_A6XX_RB_CLEAR_COLOR_DW0, 1);
 350         OUT_RING(ring, clear);  /* RB_CLEAR_COLOR_DW0 */
 351
 352         OUT_PKT4(ring, REG_A6XX_VSC_RESOLVE_CNTL, 2);
 353         OUT_RING(ring, A6XX_VSC_RESOLVE_CNTL_X(zsbuf->lrz_width) |
 354                          A6XX_VSC_RESOLVE_CNTL_Y(zsbuf->lrz_height));
 355         OUT_RING(ring, 0x00000000);   // XXX UNKNOWN_0CDE
 356
 357         OUT_PKT4(ring, REG_A6XX_RB_CNTL, 1);
 358         OUT_RING(ring, A6XX_RB_CNTL_BYPASS);
 359
 360         OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_CNTL_1, 2);
 361         OUT_RING(ring, A6XX_RB_RESOLVE_CNTL_1_X(0) |
 362                         A6XX_RB_RESOLVE_CNTL_1_Y(0));
 363         OUT_RING(ring, A6XX_RB_RESOLVE_CNTL_2_X(zsbuf->lrz_width - 1) |
 364                         A6XX_RB_RESOLVE_CNTL_2_Y(zsbuf->lrz_height - 1));
 365
 366         fd6_emit_blit(batch->ctx, ring);
 367 }
 368 #endif
 369
 370 #if 0
 371 clear_with_cp_blit()
 372 {
 373         /* Clear with CP_BLIT */
 374         WRITE(REG_A6XX_GRAS_2D_BLIT_CNTL, 0x10f43180);
 375
 376         OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 7);
 377         OUT_RING(ring, 0);
 378         OUT_RING(ring, 0);
 379         OUT_RING(ring, 0);
 380         OUT_RING(ring, 0);
 381         OUT_RING(ring, 0);
 382         OUT_RING(ring, 0);
 383         OUT_RING(ring, 0);
 384
 385         WRITE(0xacc0, 0xf181);
 386         WRITE(0xacc0, 0xf181);
 387
 388         WRITE(REG_A6XX_GRAS_2D_BLIT_CNTL, 0x10f43180);
 389         WRITE(REG_A6XX_RB_2D_BLIT_CNTL, 0x10f43180);
 390
 391         OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
 392         OUT_RING(ring, 0);
 393         OUT_RING(ring, 0);
 394         OUT_RING(ring, 0xff);
 395         OUT_RING(ring, 0);
 396
 397         DBG("%x %x %x %x\n", color->ui[0], color->ui[1], color->ui[2], color->ui[3]);
 398
 399         struct pipe_surface *psurf = pfb->cbufs[0];
 400         struct fd_resource *rsc = fd_resource(psurf->texture);
 401         struct fd_resource_slice *slice = fd_resource_slice(rsc, psurf->u.tex.level);
 402
 403         uint32_t offset = fd_resource_offset(rsc, psurf->u.tex.level,
 404                                                                                  psurf->u.tex.first_layer);
 405         uint32_t stride = slice->pitch * rsc->cpp;
 406
 407         enum a6xx_color_fmt format = fd6_pipe2color(pfmt);
 408         OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
 409         OUT_RING(ring,
 410                          A6XX_RB_2D_DST_INFO_COLOR_FORMAT(format) |
 411                          A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 412                          A6XX_RB_2D_DST_INFO_COLOR_SWAP(WXYZ));
 413         OUT_RELOCW(ring, rsc->bo, offset, 0, 0);  /* RB_2D_DST_LO/HI */
 414         OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(stride));
 415         OUT_RING(ring, 0);
 416         OUT_RING(ring, 0);
 417         OUT_RING(ring, 0);
 418         OUT_RING(ring, 0);
 419         OUT_RING(ring, 0);
 420
 421         OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
 422         OUT_RING(ring, 0);
 423         OUT_RING(ring, 0);
 424         OUT_RING(ring, 0);
 425         OUT_RING(ring, 0);
 426
 427         OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
 428         OUT_RING(ring,
 429                          A6XX_GRAS_2D_DST_TL_X(ctx->batch->max_scissor.minx) |
 430                          A6XX_GRAS_2D_DST_TL_Y(ctx->batch->max_scissor.miny));
 431         OUT_RING(ring,
 432                          A6XX_GRAS_2D_DST_BR_X(ctx->batch->max_scissor.maxx) |
 433                          A6XX_GRAS_2D_DST_BR_Y(ctx->batch->max_scissor.maxy));
 434
 435         OUT_PKT7(ring, CP_BLIT, 1);
 436         OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
 437 }
 438 #endif
 439
 440 static bool
 441 fd6_clear(struct fd_context *ctx, unsigned buffers,
 442                 const union pipe_color_union *color, double depth, unsigned stencil)
 443 {
 444         struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
 445         struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
 446         struct fd_ringbuffer *ring = ctx->batch->draw;
 447
 448         if ((buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) &&
 449                         is_z32(pfb->zsbuf->format))
 450                 return false;
 451
 452         fd6_emit_render_cntl(ctx, true, false);
 453
 454         OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
 455         OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_TL_X(scissor->minx) |
 456                          A6XX_RB_BLIT_SCISSOR_TL_Y(scissor->miny));
 457         OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_BR_X(scissor->maxx - 1) |
 458                          A6XX_RB_BLIT_SCISSOR_BR_Y(scissor->maxy - 1));
 459
 460         if (buffers & PIPE_CLEAR_COLOR) {
 461                 for (int i = 0; i < pfb->nr_cbufs; i++) {
 462                         union util_color uc = {0};
 463
 464                         if (!pfb->cbufs[i])
 465                                 continue;
 466
 467                         if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
 468                                 continue;
 469
 470                         enum pipe_format pfmt = pfb->cbufs[i]->format;
 471
 472                         // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
 473                         union pipe_color_union swapped;
 474                         switch (fd6_pipe2swap(pfmt)) {
 475                         case WZYX:
 476                                 swapped.ui[0] = color->ui[0];
 477                                 swapped.ui[1] = color->ui[1];
 478                                 swapped.ui[2] = color->ui[2];
 479                                 swapped.ui[3] = color->ui[3];
 480                                 break;
 481                         case WXYZ:
 482                                 swapped.ui[2] = color->ui[0];
 483                                 swapped.ui[1] = color->ui[1];
 484                                 swapped.ui[0] = color->ui[2];
 485                                 swapped.ui[3] = color->ui[3];
 486                                 break;
 487                         case ZYXW:
 488                                 swapped.ui[3] = color->ui[0];
 489                                 swapped.ui[0] = color->ui[1];
 490                                 swapped.ui[1] = color->ui[2];
 491                                 swapped.ui[2] = color->ui[3];
 492                                 break;
 493                         case XYZW:
 494                                 swapped.ui[3] = color->ui[0];
 495                                 swapped.ui[2] = color->ui[1];
 496                                 swapped.ui[1] = color->ui[2];
 497                                 swapped.ui[0] = color->ui[3];
 498                                 break;
 499                         }
 500
 501                         if (util_format_is_pure_uint(pfmt)) {
 502                                 util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
 503                         } else if (util_format_is_pure_sint(pfmt)) {
 504                                 util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
 505                         } else {
 506                                 util_pack_color(swapped.f, pfmt, &uc);
 507                         }
 508
 509                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
 510                         OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 511                                 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
 512
 513                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
 514                         OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
 515                                 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
 516
 517                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
 518                         OUT_RINGP(ring, i, &ctx->batch->gmem_patches);
 519
 520                         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
 521                         OUT_RING(ring, 0);
 522
 523                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
 524                         OUT_RING(ring, uc.ui[0]);
 525                         OUT_RING(ring, uc.ui[1]);
 526                         OUT_RING(ring, uc.ui[2]);
 527                         OUT_RING(ring, uc.ui[3]);
 528
 529                         fd6_emit_blit(ctx, ring);
 530                 }
 531         }
 532
 533         if (pfb->zsbuf && (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))) {
 534                 enum pipe_format pfmt = pfb->zsbuf->format;
 535                 uint32_t clear = util_pack_z_stencil(pfmt, depth, stencil);
 536                 uint32_t mask = 0;
 537
 538                 if (buffers & PIPE_CLEAR_DEPTH)
 539                         mask |= 0x1;
 540
 541                 if (buffers & PIPE_CLEAR_STENCIL)
 542                         mask |= 0x2;
 543
 544                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
 545                 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 546                         A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
 547
 548                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
 549                 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
 550                         // XXX UNK0 for separate stencil ??
 551                         A6XX_RB_BLIT_INFO_DEPTH |
 552                         A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
 553
 554                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
 555                 OUT_RINGP(ring, MAX_RENDER_TARGETS, &ctx->batch->gmem_patches);
 556
 557                 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
 558                 OUT_RING(ring, 0);
 559
 560                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
 561                 OUT_RING(ring, clear);
 562
 563                 fd6_emit_blit(ctx, ring);
 564
 565 #if 0
 566                 if (pfb->zsbuf && (buffers & PIPE_CLEAR_DEPTH)) {
 567                         struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
 568                         if (zsbuf->lrz) {
 569                                 zsbuf->lrz_valid = true;
 570                                 fd6_clear_lrz(ctx->batch, zsbuf, depth);
 571                         }
 572                 }
 573 #endif
 574         }
 575
 576         return true;
 577 }
 578
 579 void
 580 fd6_draw_init(struct pipe_context *pctx)
 581 {
 582         struct fd_context *ctx = fd_context(pctx);
 583         ctx->draw_vbo = fd6_draw_vbo;
 584         ctx->clear = fd6_clear;
 585 }