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2260f17b6a175936b3ccfa46e6cb6643f48c4e62
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_helpers.h"
32 #include "util/format/u_format.h"
33 #include "util/u_viewport.h"
34
35 #include "freedreno_log.h"
36 #include "freedreno_resource.h"
37 #include "freedreno_query_hw.h"
38
39 #include "fd6_emit.h"
40 #include "fd6_blend.h"
41 #include "fd6_const.h"
42 #include "fd6_context.h"
43 #include "fd6_image.h"
44 #include "fd6_pack.h"
45 #include "fd6_program.h"
46 #include "fd6_rasterizer.h"
47 #include "fd6_texture.h"
48 #include "fd6_format.h"
49 #include "fd6_zsa.h"
50
51 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
52 * the same as a6xx then move this somewhere common ;-)
53 *
54 * Entry layout looks like (total size, 0x60 bytes):
55 */
56
57 struct PACKED bcolor_entry {
58 uint32_t fp32[4];
59 uint16_t ui16[4];
60 int16_t si16[4];
61 uint16_t fp16[4];
62 uint16_t rgb565;
63 uint16_t rgb5a1;
64 uint16_t rgba4;
65 uint8_t __pad0[2];
66 uint8_t ui8[4];
67 int8_t si8[4];
68 uint32_t rgb10a2;
69 uint32_t z24; /* also s8? */
70 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
71 uint8_t __pad1[56];
72 };
73
74 #define FD6_BORDER_COLOR_SIZE sizeof(struct bcolor_entry)
75 #define FD6_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD6_BORDER_COLOR_SIZE)
76
77 static void
78 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
79 {
80 unsigned i, j;
81 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
82
83 for (i = 0; i < tex->num_samplers; i++) {
84 struct bcolor_entry *e = &entries[i];
85 struct pipe_sampler_state *sampler = tex->samplers[i];
86 union pipe_color_union *bc;
87
88 if (!sampler)
89 continue;
90
91 bc = &sampler->border_color;
92
93 /*
94 * XXX HACK ALERT XXX
95 *
96 * The border colors need to be swizzled in a particular
97 * format-dependent order. Even though samplers don't know about
98 * formats, we can assume that with a GL state tracker, there's a
99 * 1:1 correspondence between sampler and texture. Take advantage
100 * of that knowledge.
101 */
102 if ((i >= tex->num_textures) || !tex->textures[i])
103 continue;
104
105 struct pipe_sampler_view *view = tex->textures[i];
106 enum pipe_format format = view->format;
107 const struct util_format_description *desc =
108 util_format_description(format);
109
110 e->rgb565 = 0;
111 e->rgb5a1 = 0;
112 e->rgba4 = 0;
113 e->rgb10a2 = 0;
114 e->z24 = 0;
115
116 unsigned char swiz[4];
117
118 fd6_tex_swiz(format, swiz,
119 view->swizzle_r, view->swizzle_g,
120 view->swizzle_b, view->swizzle_a);
121
122 for (j = 0; j < 4; j++) {
123 int c = swiz[j];
124 int cd = c;
125
126 /*
127 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the
128 * stencil border color value in bc->ui[0] but according
129 * to desc->swizzle and desc->channel, the .x/.w component
130 * is NONE and the stencil value is in the y component.
131 * Meanwhile the hardware wants this in the .w component
132 * for x24s8 and the .x component for x32_s8x24.
133 */
134 if ((format == PIPE_FORMAT_X24S8_UINT) ||
135 (format == PIPE_FORMAT_X32_S8X24_UINT)) {
136 if (j == 0) {
137 c = 1;
138 cd = (format == PIPE_FORMAT_X32_S8X24_UINT) ? 0 : 3;
139 } else {
140 continue;
141 }
142 }
143
144 if (c >= 4)
145 continue;
146
147 if (desc->channel[c].pure_integer) {
148 uint16_t clamped;
149 switch (desc->channel[c].size) {
150 case 2:
151 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
152 clamped = CLAMP(bc->ui[j], 0, 0x3);
153 break;
154 case 8:
155 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
156 clamped = CLAMP(bc->i[j], -128, 127);
157 else
158 clamped = CLAMP(bc->ui[j], 0, 255);
159 break;
160 case 10:
161 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
162 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
163 break;
164 case 16:
165 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
166 clamped = CLAMP(bc->i[j], -32768, 32767);
167 else
168 clamped = CLAMP(bc->ui[j], 0, 65535);
169 break;
170 default:
171 assert(!"Unexpected bit size");
172 case 32:
173 clamped = 0;
174 break;
175 }
176 e->fp32[cd] = bc->ui[j];
177 e->fp16[cd] = clamped;
178 } else {
179 float f = bc->f[j];
180 float f_u = CLAMP(f, 0, 1);
181 float f_s = CLAMP(f, -1, 1);
182
183 e->fp32[c] = fui(f);
184 e->fp16[c] = util_float_to_half(f);
185 e->srgb[c] = util_float_to_half(f_u);
186 e->ui16[c] = f_u * 0xffff;
187 e->si16[c] = f_s * 0x7fff;
188 e->ui8[c] = f_u * 0xff;
189 e->si8[c] = f_s * 0x7f;
190 if (c == 1)
191 e->rgb565 |= (int)(f_u * 0x3f) << 5;
192 else if (c < 3)
193 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
194 if (c == 3)
195 e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
196 else
197 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
198 if (c == 3)
199 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
200 else
201 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
202 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
203 if (c == 0)
204 e->z24 = f_u * 0xffffff;
205 }
206 }
207
208 #ifdef DEBUG
209 memset(&e->__pad0, 0, sizeof(e->__pad0));
210 memset(&e->__pad1, 0, sizeof(e->__pad1));
211 #endif
212 }
213 }
214
215 static void
216 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
217 {
218 struct fd6_context *fd6_ctx = fd6_context(ctx);
219 struct bcolor_entry *entries;
220 unsigned off;
221 void *ptr;
222
223 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
224
225 u_upload_alloc(fd6_ctx->border_color_uploader,
226 0, FD6_BORDER_COLOR_UPLOAD_SIZE,
227 FD6_BORDER_COLOR_UPLOAD_SIZE, &off,
228 &fd6_ctx->border_color_buf,
229 &ptr);
230
231 entries = ptr;
232
233 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
234 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
235 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
236
237 OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
238 OUT_RELOC(ring, fd_resource(fd6_ctx->border_color_buf)->bo, off, 0, 0);
239
240 u_upload_unmap(fd6_ctx->border_color_uploader);
241 }
242
243 static void
244 fd6_emit_fb_tex(struct fd_ringbuffer *state, struct fd_context *ctx)
245 {
246 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
247 struct pipe_surface *psurf = pfb->cbufs[0];
248 struct fd_resource *rsc = fd_resource(psurf->texture);
249
250 uint32_t texconst0 = fd6_tex_const_0(psurf->texture, psurf->u.tex.level,
251 psurf->format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
252 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W);
253
254 /* always TILE6_2 mode in GMEM.. which also means no swap: */
255 texconst0 &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
256 texconst0 |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
257
258 OUT_RING(state, texconst0);
259 OUT_RING(state, A6XX_TEX_CONST_1_WIDTH(pfb->width) |
260 A6XX_TEX_CONST_1_HEIGHT(pfb->height));
261 OUT_RINGP(state, A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D),
262 &ctx->batch->fb_read_patches);
263 OUT_RING(state, A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size));
264
265 OUT_RING(state, A6XX_TEX_CONST_4_BASE_LO(ctx->screen->gmem_base));
266 OUT_RING(state, A6XX_TEX_CONST_5_BASE_HI(ctx->screen->gmem_base >> 32) |
267 A6XX_TEX_CONST_5_DEPTH(1));
268 OUT_RING(state, 0); /* texconst6 */
269 OUT_RING(state, 0); /* texconst7 */
270 OUT_RING(state, 0); /* texconst8 */
271 OUT_RING(state, 0); /* texconst9 */
272 OUT_RING(state, 0); /* texconst10 */
273 OUT_RING(state, 0); /* texconst11 */
274 OUT_RING(state, 0);
275 OUT_RING(state, 0);
276 OUT_RING(state, 0);
277 OUT_RING(state, 0);
278 }
279
280 bool
281 fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
282 enum pipe_shader_type type, struct fd_texture_stateobj *tex,
283 unsigned bcolor_offset,
284 /* can be NULL if no image/SSBO/fb state to merge in: */
285 const struct ir3_shader_variant *v, struct fd_context *ctx)
286 {
287 bool needs_border = false;
288 unsigned opcode, tex_samp_reg, tex_const_reg, tex_count_reg;
289 enum a6xx_state_block sb;
290
291 switch (type) {
292 case PIPE_SHADER_VERTEX:
293 sb = SB6_VS_TEX;
294 opcode = CP_LOAD_STATE6_GEOM;
295 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
296 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
297 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
298 break;
299 case PIPE_SHADER_TESS_CTRL:
300 sb = SB6_HS_TEX;
301 opcode = CP_LOAD_STATE6_GEOM;
302 tex_samp_reg = REG_A6XX_SP_HS_TEX_SAMP_LO;
303 tex_const_reg = REG_A6XX_SP_HS_TEX_CONST_LO;
304 tex_count_reg = REG_A6XX_SP_HS_TEX_COUNT;
305 break;
306 case PIPE_SHADER_TESS_EVAL:
307 sb = SB6_DS_TEX;
308 opcode = CP_LOAD_STATE6_GEOM;
309 tex_samp_reg = REG_A6XX_SP_DS_TEX_SAMP_LO;
310 tex_const_reg = REG_A6XX_SP_DS_TEX_CONST_LO;
311 tex_count_reg = REG_A6XX_SP_DS_TEX_COUNT;
312 break;
313 case PIPE_SHADER_GEOMETRY:
314 sb = SB6_GS_TEX;
315 opcode = CP_LOAD_STATE6_GEOM;
316 tex_samp_reg = REG_A6XX_SP_GS_TEX_SAMP_LO;
317 tex_const_reg = REG_A6XX_SP_GS_TEX_CONST_LO;
318 tex_count_reg = REG_A6XX_SP_GS_TEX_COUNT;
319 break;
320 case PIPE_SHADER_FRAGMENT:
321 sb = SB6_FS_TEX;
322 opcode = CP_LOAD_STATE6_FRAG;
323 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
324 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
325 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
326 break;
327 case PIPE_SHADER_COMPUTE:
328 sb = SB6_CS_TEX;
329 opcode = CP_LOAD_STATE6_FRAG;
330 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
331 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
332 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
333 break;
334 default:
335 unreachable("bad state block");
336 }
337
338 if (tex->num_samplers > 0) {
339 struct fd_ringbuffer *state =
340 fd_ringbuffer_new_object(pipe, tex->num_samplers * 4 * 4);
341 for (unsigned i = 0; i < tex->num_samplers; i++) {
342 static const struct fd6_sampler_stateobj dummy_sampler = {};
343 const struct fd6_sampler_stateobj *sampler = tex->samplers[i] ?
344 fd6_sampler_stateobj(tex->samplers[i]) : &dummy_sampler;
345 OUT_RING(state, sampler->texsamp0);
346 OUT_RING(state, sampler->texsamp1);
347 OUT_RING(state, sampler->texsamp2 |
348 A6XX_TEX_SAMP_2_BCOLOR_OFFSET((i + bcolor_offset) * sizeof(struct bcolor_entry)));
349 OUT_RING(state, sampler->texsamp3);
350 needs_border |= sampler->needs_border;
351 }
352
353 /* output sampler state: */
354 OUT_PKT7(ring, opcode, 3);
355 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
356 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
357 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
358 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
359 CP_LOAD_STATE6_0_NUM_UNIT(tex->num_samplers));
360 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
361
362 OUT_PKT4(ring, tex_samp_reg, 2);
363 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
364
365 fd_ringbuffer_del(state);
366 }
367
368 unsigned num_merged_textures = tex->num_textures;
369 unsigned num_textures = tex->num_textures;
370 if (v) {
371 num_merged_textures += v->image_mapping.num_tex;
372
373 if (v->fb_read)
374 num_merged_textures++;
375
376 /* There could be more bound textures than what the shader uses.
377 * Which isn't known at shader compile time. So in the case we
378 * are merging tex state, only emit the textures that the shader
379 * uses (since the image/SSBO related tex state comes immediately
380 * after)
381 */
382 num_textures = v->image_mapping.tex_base;
383 }
384
385 if (num_merged_textures > 0) {
386 struct fd_ringbuffer *state =
387 fd_ringbuffer_new_object(pipe, num_merged_textures * 16 * 4);
388 for (unsigned i = 0; i < num_textures; i++) {
389 static const struct fd6_pipe_sampler_view dummy_view = {};
390 const struct fd6_pipe_sampler_view *view = tex->textures[i] ?
391 fd6_pipe_sampler_view(tex->textures[i]) : &dummy_view;
392 struct fd_resource *rsc = NULL;
393
394 if (view->base.texture)
395 rsc = fd_resource(view->base.texture);
396
397 OUT_RING(state, view->texconst0);
398 OUT_RING(state, view->texconst1);
399 OUT_RING(state, view->texconst2);
400 OUT_RING(state, view->texconst3);
401
402 if (rsc) {
403 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
404 rsc = rsc->stencil;
405 OUT_RELOC(state, rsc->bo, view->offset,
406 (uint64_t)view->texconst5 << 32, 0);
407 } else {
408 OUT_RING(state, 0x00000000);
409 OUT_RING(state, view->texconst5);
410 }
411
412 OUT_RING(state, view->texconst6);
413
414 if (rsc && view->ubwc_enabled) {
415 OUT_RELOC(state, rsc->bo, view->ubwc_offset, 0, 0);
416 } else {
417 OUT_RING(state, 0);
418 OUT_RING(state, 0);
419 }
420
421 OUT_RING(state, view->texconst9);
422 OUT_RING(state, view->texconst10);
423 OUT_RING(state, view->texconst11);
424 OUT_RING(state, 0);
425 OUT_RING(state, 0);
426 OUT_RING(state, 0);
427 OUT_RING(state, 0);
428 }
429
430 if (v) {
431 const struct ir3_ibo_mapping *mapping = &v->image_mapping;
432 struct fd_shaderbuf_stateobj *buf = &ctx->shaderbuf[type];
433 struct fd_shaderimg_stateobj *img = &ctx->shaderimg[type];
434
435 for (unsigned i = 0; i < mapping->num_tex; i++) {
436 unsigned idx = mapping->tex_to_image[i];
437 if (idx & IBO_SSBO) {
438 fd6_emit_ssbo_tex(state, &buf->sb[idx & ~IBO_SSBO]);
439 } else {
440 fd6_emit_image_tex(state, &img->si[idx]);
441 }
442 }
443
444 if (v->fb_read) {
445 fd6_emit_fb_tex(state, ctx);
446 }
447 }
448
449 /* emit texture state: */
450 OUT_PKT7(ring, opcode, 3);
451 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
452 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
453 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
454 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
455 CP_LOAD_STATE6_0_NUM_UNIT(num_merged_textures));
456 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
457
458 OUT_PKT4(ring, tex_const_reg, 2);
459 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
460
461 fd_ringbuffer_del(state);
462 }
463
464 OUT_PKT4(ring, tex_count_reg, 1);
465 OUT_RING(ring, num_merged_textures);
466
467 return needs_border;
468 }
469
470 /* Emits combined texture state, which also includes any Image/SSBO
471 * related texture state merged in (because we must have all texture
472 * state for a given stage in a single buffer). In the fast-path, if
473 * we don't need to merge in any image/ssbo related texture state, we
474 * just use cached texture stateobj. Otherwise we generate a single-
475 * use stateobj.
476 *
477 * TODO Is there some sane way we can still use cached texture stateobj
478 * with image/ssbo in use?
479 *
480 * returns whether border_color is required:
481 */
482 static bool
483 fd6_emit_combined_textures(struct fd_ringbuffer *ring, struct fd6_emit *emit,
484 enum pipe_shader_type type, const struct ir3_shader_variant *v)
485 {
486 struct fd_context *ctx = emit->ctx;
487 bool needs_border = false;
488
489 static const struct {
490 enum fd6_state_id state_id;
491 unsigned enable_mask;
492 } s[PIPE_SHADER_TYPES] = {
493 [PIPE_SHADER_VERTEX] = { FD6_GROUP_VS_TEX, ENABLE_ALL },
494 [PIPE_SHADER_TESS_CTRL] = { FD6_GROUP_HS_TEX, ENABLE_ALL },
495 [PIPE_SHADER_TESS_EVAL] = { FD6_GROUP_DS_TEX, ENABLE_ALL },
496 [PIPE_SHADER_GEOMETRY] = { FD6_GROUP_GS_TEX, ENABLE_ALL },
497 [PIPE_SHADER_FRAGMENT] = { FD6_GROUP_FS_TEX, ENABLE_DRAW },
498 };
499
500 debug_assert(s[type].state_id);
501
502 if (!v->image_mapping.num_tex && !v->fb_read) {
503 /* in the fast-path, when we don't have to mix in any image/SSBO
504 * related texture state, we can just lookup the stateobj and
505 * re-emit that:
506 *
507 * Also, framebuffer-read is a slow-path because an extra
508 * texture needs to be inserted.
509 *
510 * TODO we can probably simmplify things if we also treated
511 * border_color as a slow-path.. this way the tex state key
512 * wouldn't depend on bcolor_offset.. but fb_read might rather
513 * be *somehow* a fast-path if we eventually used it for PLS.
514 * I suppose there would be no harm in just *always* inserting
515 * an fb_read texture?
516 */
517 if ((ctx->dirty_shader[type] & FD_DIRTY_SHADER_TEX) &&
518 ctx->tex[type].num_textures > 0) {
519 struct fd6_texture_state *tex = fd6_texture_state(ctx,
520 type, &ctx->tex[type]);
521
522 needs_border |= tex->needs_border;
523
524 fd6_emit_add_group(emit, tex->stateobj, s[type].state_id,
525 s[type].enable_mask);
526 }
527 } else {
528 /* In the slow-path, create a one-shot texture state object
529 * if either TEX|PROG|SSBO|IMAGE state is dirty:
530 */
531 if ((ctx->dirty_shader[type] &
532 (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
533 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) ||
534 v->fb_read) {
535 struct fd_texture_stateobj *tex = &ctx->tex[type];
536 struct fd_ringbuffer *stateobj =
537 fd_submit_new_ringbuffer(ctx->batch->submit,
538 0x1000, FD_RINGBUFFER_STREAMING);
539 unsigned bcolor_offset =
540 fd6_border_color_offset(ctx, type, tex);
541
542 needs_border |= fd6_emit_textures(ctx->pipe, stateobj, type, tex,
543 bcolor_offset, v, ctx);
544
545 fd6_emit_take_group(emit, stateobj, s[type].state_id,
546 s[type].enable_mask);
547 }
548 }
549
550 return needs_border;
551 }
552
553 static struct fd_ringbuffer *
554 build_vbo_state(struct fd6_emit *emit)
555 {
556 const struct fd_vertex_state *vtx = emit->vtx;
557
558 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
559 4 * (1 + vtx->vertexbuf.count * 4), FD_RINGBUFFER_STREAMING);
560
561 OUT_PKT4(ring, REG_A6XX_VFD_FETCH(0), 4 * vtx->vertexbuf.count);
562 for (int32_t j = 0; j < vtx->vertexbuf.count; j++) {
563 const struct pipe_vertex_buffer *vb = &vtx->vertexbuf.vb[j];
564 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
565 if (rsc == NULL) {
566 OUT_RING(ring, 0);
567 OUT_RING(ring, 0);
568 OUT_RING(ring, 0);
569 OUT_RING(ring, 0);
570 } else {
571 uint32_t off = vb->buffer_offset;
572 uint32_t size = fd_bo_size(rsc->bo) - off;
573
574 OUT_RELOC(ring, rsc->bo, off, 0, 0);
575 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
576 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
577 }
578 }
579
580 return ring;
581 }
582
583 static enum a6xx_ztest_mode
584 compute_ztest_mode(struct fd6_emit *emit, bool lrz_valid)
585 {
586 struct fd_context *ctx = emit->ctx;
587 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
588 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
589 const struct ir3_shader_variant *fs = emit->fs;
590
591 if (fs->no_earlyz || fs->writes_pos) {
592 return A6XX_LATE_Z;
593 } else if ((fs->has_kill || zsa->alpha_test) &&
594 (zsa->base.depth.writemask || !pfb->zsbuf)) {
595 /* Slightly odd, but seems like the hw wants us to select
596 * LATE_Z mode if there is no depth buffer + discard. Either
597 * that, or when occlusion query is enabled. See:
598 *
599 * dEQP-GLES31.functional.fbo.no_attachments.*
600 */
601 return lrz_valid ? A6XX_EARLY_LRZ_LATE_Z : A6XX_LATE_Z;
602 } else {
603 return A6XX_EARLY_Z;
604 }
605 }
606
607 /**
608 * Calculate normalized LRZ state based on zsa/prog/blend state, updating
609 * the zsbuf's lrz state as necessary to detect the cases where we need
610 * to invalidate lrz.
611 */
612 static struct fd6_lrz_state
613 compute_lrz_state(struct fd6_emit *emit, bool binning_pass)
614 {
615 struct fd_context *ctx = emit->ctx;
616 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
617 const struct ir3_shader_variant *fs = emit->fs;
618 struct fd6_lrz_state lrz;
619
620 if (!pfb->zsbuf) {
621 memset(&lrz, 0, sizeof(lrz));
622 if (!binning_pass) {
623 lrz.z_mode = compute_ztest_mode(emit, false);
624 }
625 return lrz;
626 }
627
628 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
629 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
630 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
631
632 lrz = zsa->lrz;
633
634 /* normalize lrz state: */
635 if (blend->reads_dest || fs->writes_pos || fs->no_earlyz || fs->has_kill) {
636 lrz.write = false;
637 if (binning_pass)
638 lrz.enable = false;
639 }
640
641 /* if we change depthfunc direction, bail out on using LRZ. The
642 * LRZ buffer encodes a min/max depth value per block, but if
643 * we switch from GT/GE <-> LT/LE, those values cannot be
644 * interpreted properly.
645 */
646 if (zsa->base.depth.enabled &&
647 (rsc->lrz_direction != FD_LRZ_UNKNOWN) &&
648 (rsc->lrz_direction != lrz.direction)) {
649 rsc->lrz_valid = false;
650 }
651
652 if (zsa->invalidate_lrz || !rsc->lrz_valid) {
653 rsc->lrz_valid = false;
654 memset(&lrz, 0, sizeof(lrz));
655 }
656
657 if (fs->no_earlyz || fs->writes_pos) {
658 lrz.enable = false;
659 lrz.write = false;
660 lrz.test = false;
661 }
662
663 if (!binning_pass) {
664 lrz.z_mode = compute_ztest_mode(emit, rsc->lrz_valid);
665 }
666
667 /* Once we start writing to the real depth buffer, we lock in the
668 * direction for LRZ.. if we have to skip a LRZ write for any
669 * reason, it is still safe to have LRZ until there is a direction
670 * reversal. Prior to the reversal, since we disabled LRZ writes
671 * in the "unsafe" cases, this just means that the LRZ test may
672 * not early-discard some things that end up not passing a later
673 * test (ie. be overly concervative). But once you have a reversal
674 * of direction, it is possible to increase/decrease the z value
675 * to the point where the overly-conservative test is incorrect.
676 */
677 if (zsa->base.depth.writemask) {
678 rsc->lrz_direction = lrz.direction;
679 }
680
681 return lrz;
682 }
683
684 static struct fd_ringbuffer *
685 build_lrz(struct fd6_emit *emit, bool binning_pass)
686 {
687 struct fd_context *ctx = emit->ctx;
688 struct fd6_context *fd6_ctx = fd6_context(ctx);
689 struct fd6_lrz_state lrz =
690 compute_lrz_state(emit, binning_pass);
691
692 /* If the LRZ state has not changed, we can skip the emit: */
693 if (!ctx->last.dirty &&
694 !memcmp(&fd6_ctx->last.lrz[binning_pass], &lrz, sizeof(lrz)))
695 return NULL;
696
697 fd6_ctx->last.lrz[binning_pass] = lrz;
698
699 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(ctx->batch->submit,
700 8*4, FD_RINGBUFFER_STREAMING);
701
702 OUT_REG(ring, A6XX_GRAS_LRZ_CNTL(
703 .enable = lrz.enable,
704 .lrz_write = lrz.write,
705 .greater = lrz.direction == FD_LRZ_GREATER,
706 .z_test_enable = lrz.test,
707 ));
708 OUT_REG(ring, A6XX_RB_LRZ_CNTL(
709 .enable = lrz.enable,
710 ));
711
712 OUT_REG(ring, A6XX_RB_DEPTH_PLANE_CNTL(
713 .z_mode = lrz.z_mode,
714 ));
715
716 OUT_REG(ring, A6XX_GRAS_SU_DEPTH_PLANE_CNTL(
717 .z_mode = lrz.z_mode,
718 ));
719
720 return ring;
721 }
722
723 static void
724 fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3_stream_output_info *info)
725 {
726 struct fd_context *ctx = emit->ctx;
727 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
728 struct fd_streamout_stateobj *so = &ctx->streamout;
729
730 emit->streamout_mask = 0;
731
732 for (unsigned i = 0; i < so->num_targets; i++) {
733 struct pipe_stream_output_target *target = so->targets[i];
734
735 if (!target)
736 continue;
737
738 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(i), 3);
739 /* VPC_SO[i].BUFFER_BASE_LO: */
740 OUT_RELOC(ring, fd_resource(target->buffer)->bo, target->buffer_offset, 0, 0);
741 OUT_RING(ring, target->buffer_size - target->buffer_offset);
742
743 if (so->reset & (1 << i)) {
744 unsigned offset = (so->offsets[i] * info->stride[i] * 4);
745 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(i), 1);
746 OUT_RING(ring, offset);
747 } else {
748 OUT_PKT7(ring, CP_MEM_TO_REG, 3);
749 OUT_RING(ring, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i)) |
750 CP_MEM_TO_REG_0_SHIFT_BY_2 | CP_MEM_TO_REG_0_UNK31 |
751 CP_MEM_TO_REG_0_CNT(0));
752 OUT_RELOC(ring, control_ptr(fd6_context(ctx), flush_base[i].offset));
753 }
754
755 OUT_PKT4(ring, REG_A6XX_VPC_SO_FLUSH_BASE_LO(i), 2);
756 OUT_RELOC(ring, control_ptr(fd6_context(ctx), flush_base[i]));
757
758 so->reset &= ~(1 << i);
759
760 emit->streamout_mask |= (1 << i);
761 }
762
763 if (emit->streamout_mask) {
764 fd6_emit_add_group(emit, prog->streamout_stateobj, FD6_GROUP_SO, ENABLE_ALL);
765 } else {
766 /* If we transition from a draw with streamout to one without, turn
767 * off streamout.
768 */
769 if (ctx->last.streamout_mask != 0) {
770 struct fd_ringbuffer *obj = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
771 5 * 4, FD_RINGBUFFER_STREAMING);
772
773 OUT_PKT7(obj, CP_CONTEXT_REG_BUNCH, 4);
774 OUT_RING(obj, REG_A6XX_VPC_SO_CNTL);
775 OUT_RING(obj, 0);
776 OUT_RING(obj, REG_A6XX_VPC_SO_BUF_CNTL);
777 OUT_RING(obj, 0);
778
779 fd6_emit_take_group(emit, obj, FD6_GROUP_SO, ENABLE_ALL);
780 }
781 }
782
783 ctx->last.streamout_mask = emit->streamout_mask;
784 }
785
786 void
787 fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
788 {
789 struct fd_context *ctx = emit->ctx;
790 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
791 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
792 const struct ir3_shader_variant *vs = emit->vs;
793 const struct ir3_shader_variant *hs = emit->hs;
794 const struct ir3_shader_variant *ds = emit->ds;
795 const struct ir3_shader_variant *gs = emit->gs;
796 const struct ir3_shader_variant *fs = emit->fs;
797 const enum fd_dirty_3d_state dirty = emit->dirty;
798 bool needs_border = false;
799
800 emit_marker6(ring, 5);
801
802 /* NOTE: we track fb_read differently than _BLEND_ENABLED since
803 * we might at some point decide to do sysmem in some cases when
804 * blend is enabled:
805 */
806 if (fs->fb_read)
807 ctx->batch->gmem_reason |= FD_GMEM_FB_READ;
808
809 if (emit->dirty & FD_DIRTY_VTXSTATE) {
810 struct fd6_vertex_stateobj *vtx = fd6_vertex_stateobj(ctx->vtx.vtx);
811
812 fd6_emit_add_group(emit, vtx->stateobj, FD6_GROUP_VTXSTATE, ENABLE_ALL);
813 }
814
815 if (emit->dirty & FD_DIRTY_VTXBUF) {
816 struct fd_ringbuffer *state;
817
818 state = build_vbo_state(emit);
819 fd6_emit_take_group(emit, state, FD6_GROUP_VBO, ENABLE_ALL);
820 }
821
822 if (dirty & FD_DIRTY_ZSA) {
823 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
824
825 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
826 fd6_emit_add_group(emit, zsa->stateobj_no_alpha, FD6_GROUP_ZSA, ENABLE_ALL);
827 else
828 fd6_emit_add_group(emit, zsa->stateobj, FD6_GROUP_ZSA, ENABLE_ALL);
829 }
830
831 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG)) {
832 struct fd_ringbuffer *state;
833
834 state = build_lrz(emit, false);
835 if (state) {
836 fd6_emit_take_group(emit, state, FD6_GROUP_LRZ, ENABLE_DRAW);
837 }
838
839 state = build_lrz(emit, true);
840 if (state) {
841 fd6_emit_take_group(emit, state,
842 FD6_GROUP_LRZ_BINNING, CP_SET_DRAW_STATE__0_BINNING);
843 }
844 }
845
846 if (dirty & FD_DIRTY_STENCIL_REF) {
847 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
848
849 OUT_PKT4(ring, REG_A6XX_RB_STENCILREF, 1);
850 OUT_RING(ring, A6XX_RB_STENCILREF_REF(sr->ref_value[0]) |
851 A6XX_RB_STENCILREF_BFREF(sr->ref_value[1]));
852 }
853
854 /* NOTE: scissor enabled bit is part of rasterizer state, but
855 * fd_rasterizer_state_bind() will mark scissor dirty if needed:
856 */
857 if (dirty & FD_DIRTY_SCISSOR) {
858 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
859 emit->ctx->batch->submit, 3*4, FD_RINGBUFFER_STREAMING);
860 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
861
862 OUT_REG(ring,
863 A6XX_GRAS_SC_SCREEN_SCISSOR_TL(0,
864 .x = scissor->minx,
865 .y = scissor->miny
866 ),
867 A6XX_GRAS_SC_SCREEN_SCISSOR_BR(0,
868 .x = MAX2(scissor->maxx, 1) - 1,
869 .y = MAX2(scissor->maxy, 1) - 1
870 )
871 );
872
873 fd6_emit_take_group(emit, ring, FD6_GROUP_SCISSOR, ENABLE_ALL);
874
875 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
876 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
877 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
878 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
879 }
880
881 if (dirty & FD_DIRTY_VIEWPORT) {
882 struct pipe_scissor_state *scissor = &ctx->viewport_scissor;
883
884 OUT_REG(ring,
885 A6XX_GRAS_CL_VPORT_XOFFSET(0, ctx->viewport.translate[0]),
886 A6XX_GRAS_CL_VPORT_XSCALE(0, ctx->viewport.scale[0]),
887 A6XX_GRAS_CL_VPORT_YOFFSET(0, ctx->viewport.translate[1]),
888 A6XX_GRAS_CL_VPORT_YSCALE(0, ctx->viewport.scale[1]),
889 A6XX_GRAS_CL_VPORT_ZOFFSET(0, ctx->viewport.translate[2]),
890 A6XX_GRAS_CL_VPORT_ZSCALE(0, ctx->viewport.scale[2])
891 );
892
893 OUT_REG(ring,
894 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(0,
895 .x = scissor->minx,
896 .y = scissor->miny
897 ),
898 A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(0,
899 .x = MAX2(scissor->maxx, 1) - 1,
900 .y = MAX2(scissor->maxy, 1) - 1
901 )
902 );
903
904 unsigned guardband_x = fd_calc_guardband(scissor->maxx - scissor->minx);
905 unsigned guardband_y = fd_calc_guardband(scissor->maxy - scissor->miny);
906
907 OUT_REG(ring, A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ(
908 .horz = guardband_x,
909 .vert = guardband_y
910 )
911 );
912 }
913
914 if (dirty & FD_DIRTY_PROG) {
915 fd6_emit_add_group(emit, prog->config_stateobj, FD6_GROUP_PROG_CONFIG, ENABLE_ALL);
916 fd6_emit_add_group(emit, prog->stateobj, FD6_GROUP_PROG, ENABLE_DRAW);
917 fd6_emit_add_group(emit, prog->binning_stateobj,
918 FD6_GROUP_PROG_BINNING, CP_SET_DRAW_STATE__0_BINNING);
919
920 /* emit remaining streaming program state, ie. what depends on
921 * other emit state, so cannot be pre-baked.
922 */
923 struct fd_ringbuffer *streaming = fd6_program_interp_state(emit);
924
925 fd6_emit_take_group(emit, streaming, FD6_GROUP_PROG_INTERP, ENABLE_DRAW);
926 }
927
928 if (dirty & FD_DIRTY_RASTERIZER) {
929 struct fd_ringbuffer *stateobj =
930 fd6_rasterizer_state(ctx, emit->primitive_restart);
931 fd6_emit_add_group(emit, stateobj,
932 FD6_GROUP_RASTERIZER, ENABLE_ALL);
933 }
934
935 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER_DISCARD | FD_DIRTY_PROG)) {
936 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
937 emit->ctx->batch->submit, 5 * 4, FD_RINGBUFFER_STREAMING);
938
939 unsigned nr = pfb->nr_cbufs;
940
941 if (ctx->rasterizer->rasterizer_discard)
942 nr = 0;
943
944 OUT_PKT4(ring, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
945 OUT_RING(ring, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
946 COND(fs->writes_smask && pfb->samples > 1,
947 A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
948 OUT_RING(ring, A6XX_RB_FS_OUTPUT_CNTL1_MRT(nr));
949
950 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL1, 1);
951 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL1_MRT(nr));
952
953 fd6_emit_take_group(emit, ring, FD6_GROUP_PROG_FB_RAST, ENABLE_DRAW);
954 }
955
956 fd6_emit_consts(emit);
957
958 struct ir3_stream_output_info *info = &fd6_last_shader(prog)->shader->stream_output;
959 if (info->num_outputs)
960 fd6_emit_streamout(ring, emit, info);
961
962 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK)) {
963 struct fd6_blend_variant *blend = fd6_blend_variant(ctx->blend,
964 pfb->samples, ctx->sample_mask);
965 fd6_emit_add_group(emit, blend->stateobj, FD6_GROUP_BLEND, ENABLE_DRAW);
966 }
967
968 if (dirty & FD_DIRTY_BLEND_COLOR) {
969 struct pipe_blend_color *bcolor = &ctx->blend_color;
970 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
971 emit->ctx->batch->submit, 5*4, FD_RINGBUFFER_STREAMING);
972
973 OUT_REG(ring,
974 A6XX_RB_BLEND_RED_F32(bcolor->color[0]),
975 A6XX_RB_BLEND_GREEN_F32(bcolor->color[1]),
976 A6XX_RB_BLEND_BLUE_F32(bcolor->color[2]),
977 A6XX_RB_BLEND_ALPHA_F32(bcolor->color[3])
978 );
979
980 fd6_emit_take_group(emit, ring, FD6_GROUP_BLEND_COLOR, ENABLE_DRAW);
981 }
982
983 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_VERTEX, vs);
984 if (hs) {
985 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_TESS_CTRL, hs);
986 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_TESS_EVAL, ds);
987 }
988 if (gs) {
989 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_GEOMETRY, gs);
990 }
991 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_FRAGMENT, fs);
992
993 if (needs_border)
994 emit_border_color(ctx, ring);
995
996 if (hs) {
997 debug_assert(ir3_shader_nibo(hs) == 0);
998 debug_assert(ir3_shader_nibo(ds) == 0);
999 }
1000 if (gs) {
1001 debug_assert(ir3_shader_nibo(gs) == 0);
1002 }
1003
1004 #define DIRTY_IBO (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE | \
1005 FD_DIRTY_SHADER_PROG)
1006 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & DIRTY_IBO) {
1007 struct fd_ringbuffer *state =
1008 fd6_build_ibo_state(ctx, fs, PIPE_SHADER_FRAGMENT);
1009 struct fd_ringbuffer *obj = fd_submit_new_ringbuffer(
1010 ctx->batch->submit, 0x100, FD_RINGBUFFER_STREAMING);
1011
1012 OUT_PKT7(obj, CP_LOAD_STATE6, 3);
1013 OUT_RING(obj, CP_LOAD_STATE6_0_DST_OFF(0) |
1014 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1015 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1016 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_IBO) |
1017 CP_LOAD_STATE6_0_NUM_UNIT(ir3_shader_nibo(fs)));
1018 OUT_RB(obj, state);
1019
1020 OUT_PKT4(obj, REG_A6XX_SP_IBO_LO, 2);
1021 OUT_RB(obj, state);
1022
1023 /* TODO if we used CP_SET_DRAW_STATE for compute shaders, we could
1024 * de-duplicate this from program->config_stateobj
1025 */
1026 OUT_PKT4(obj, REG_A6XX_SP_IBO_COUNT, 1);
1027 OUT_RING(obj, ir3_shader_nibo(fs));
1028
1029 fd6_emit_ibo_consts(emit, fs, PIPE_SHADER_FRAGMENT, ring);
1030
1031 fd6_emit_take_group(emit, obj, FD6_GROUP_IBO, ENABLE_DRAW);
1032 fd_ringbuffer_del(state);
1033 }
1034
1035 if (emit->num_groups > 0) {
1036 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3 * emit->num_groups);
1037 for (unsigned i = 0; i < emit->num_groups; i++) {
1038 struct fd6_state_group *g = &emit->groups[i];
1039 unsigned n = g->stateobj ?
1040 fd_ringbuffer_size(g->stateobj) / 4 : 0;
1041
1042 debug_assert((g->enable_mask & ~ENABLE_ALL) == 0);
1043
1044 if (n == 0) {
1045 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1046 CP_SET_DRAW_STATE__0_DISABLE |
1047 g->enable_mask |
1048 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
1049 OUT_RING(ring, 0x00000000);
1050 OUT_RING(ring, 0x00000000);
1051 } else {
1052 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(n) |
1053 g->enable_mask |
1054 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
1055 OUT_RB(ring, g->stateobj);
1056 }
1057
1058 if (g->stateobj)
1059 fd_ringbuffer_del(g->stateobj);
1060 }
1061 emit->num_groups = 0;
1062 }
1063 }
1064
1065 void
1066 fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
1067 struct ir3_shader_variant *cp)
1068 {
1069 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
1070
1071 if (dirty & (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
1072 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) {
1073 struct fd_texture_stateobj *tex = &ctx->tex[PIPE_SHADER_COMPUTE];
1074 unsigned bcolor_offset = fd6_border_color_offset(ctx, PIPE_SHADER_COMPUTE, tex);
1075
1076 bool needs_border = fd6_emit_textures(ctx->pipe, ring, PIPE_SHADER_COMPUTE, tex,
1077 bcolor_offset, cp, ctx);
1078
1079 if (needs_border)
1080 emit_border_color(ctx, ring);
1081
1082 OUT_PKT4(ring, REG_A6XX_SP_VS_TEX_COUNT, 1);
1083 OUT_RING(ring, 0);
1084
1085 OUT_PKT4(ring, REG_A6XX_SP_HS_TEX_COUNT, 1);
1086 OUT_RING(ring, 0);
1087
1088 OUT_PKT4(ring, REG_A6XX_SP_DS_TEX_COUNT, 1);
1089 OUT_RING(ring, 0);
1090
1091 OUT_PKT4(ring, REG_A6XX_SP_GS_TEX_COUNT, 1);
1092 OUT_RING(ring, 0);
1093
1094 OUT_PKT4(ring, REG_A6XX_SP_FS_TEX_COUNT, 1);
1095 OUT_RING(ring, 0);
1096 }
1097
1098 if (dirty & (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)) {
1099 struct fd_ringbuffer *state =
1100 fd6_build_ibo_state(ctx, cp, PIPE_SHADER_COMPUTE);
1101
1102 OUT_PKT7(ring, CP_LOAD_STATE6_FRAG, 3);
1103 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
1104 CP_LOAD_STATE6_0_STATE_TYPE(ST6_IBO) |
1105 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1106 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_CS_SHADER) |
1107 CP_LOAD_STATE6_0_NUM_UNIT(ir3_shader_nibo(cp)));
1108 OUT_RB(ring, state);
1109
1110 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_LO, 2);
1111 OUT_RB(ring, state);
1112
1113 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_COUNT, 1);
1114 OUT_RING(ring, ir3_shader_nibo(cp));
1115
1116 fd_ringbuffer_del(state);
1117 }
1118 }
1119
1120
1121 /* emit setup at begin of new cmdstream buffer (don't rely on previous
1122 * state, there could have been a context switch between ioctls):
1123 */
1124 void
1125 fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
1126 {
1127 //struct fd_context *ctx = batch->ctx;
1128
1129 fd_log(batch, "START RESTORE");
1130
1131 fd6_cache_inv(batch, ring);
1132
1133 OUT_REG(ring, A6XX_HLSQ_INVALIDATE_CMD(
1134 .vs_state = true,
1135 .hs_state = true,
1136 .ds_state = true,
1137 .gs_state = true,
1138 .fs_state = true,
1139 .cs_state = true,
1140 .gfx_ibo = true,
1141 .cs_ibo = true,
1142 .gfx_shared_const = true,
1143 .cs_shared_const = true,
1144 .gfx_bindless = 0x1f,
1145 .cs_bindless = 0x1f
1146 ));
1147
1148 OUT_WFI5(ring);
1149
1150 WRITE(REG_A6XX_RB_UNKNOWN_8E04, 0x0);
1151 WRITE(REG_A6XX_SP_UNKNOWN_AE04, 0x8);
1152 WRITE(REG_A6XX_SP_UNKNOWN_AE00, 0);
1153 WRITE(REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
1154 WRITE(REG_A6XX_SP_UNKNOWN_B605, 0x44);
1155 WRITE(REG_A6XX_SP_UNKNOWN_B600, 0x100000);
1156 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
1157 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
1158
1159 WRITE(REG_A6XX_VPC_UNKNOWN_9600, 0);
1160 WRITE(REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
1161 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE04, 0x80000);
1162 WRITE(REG_A6XX_SP_UNKNOWN_AE03, 0x1430);
1163 WRITE(REG_A6XX_SP_IBO_COUNT, 0);
1164 WRITE(REG_A6XX_SP_UNKNOWN_B182, 0);
1165 WRITE(REG_A6XX_HLSQ_SHARED_CONSTS, 0);
1166 WRITE(REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
1167 WRITE(REG_A6XX_UCHE_CLIENT_PF, 4);
1168 WRITE(REG_A6XX_RB_UNKNOWN_8E01, 0x1);
1169 WRITE(REG_A6XX_SP_UNKNOWN_AB00, 0x5);
1170 WRITE(REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
1171 WRITE(REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
1172 WRITE(REG_A6XX_PC_MODE_CNTL, 0x1f);
1173
1174 WRITE(REG_A6XX_GRAS_UNKNOWN_8101, 0);
1175 WRITE(REG_A6XX_GRAS_SAMPLE_CNTL, 0);
1176 WRITE(REG_A6XX_GRAS_UNKNOWN_8110, 0x2);
1177
1178 WRITE(REG_A6XX_RB_UNKNOWN_8818, 0);
1179 WRITE(REG_A6XX_RB_UNKNOWN_8819, 0);
1180 WRITE(REG_A6XX_RB_UNKNOWN_881A, 0);
1181 WRITE(REG_A6XX_RB_UNKNOWN_881B, 0);
1182 WRITE(REG_A6XX_RB_UNKNOWN_881C, 0);
1183 WRITE(REG_A6XX_RB_UNKNOWN_881D, 0);
1184 WRITE(REG_A6XX_RB_UNKNOWN_881E, 0);
1185 WRITE(REG_A6XX_RB_UNKNOWN_88F0, 0);
1186
1187 WRITE(REG_A6XX_VPC_POINT_COORD_INVERT,
1188 A6XX_VPC_POINT_COORD_INVERT(0).value);
1189 WRITE(REG_A6XX_VPC_UNKNOWN_9300, 0);
1190
1191 WRITE(REG_A6XX_VPC_SO_DISABLE, A6XX_VPC_SO_DISABLE(true).value);
1192
1193 WRITE(REG_A6XX_PC_UNKNOWN_9990, 0);
1194 WRITE(REG_A6XX_PC_UNKNOWN_9980, 0);
1195
1196 WRITE(REG_A6XX_PC_UNKNOWN_9B07, 0);
1197
1198 WRITE(REG_A6XX_SP_UNKNOWN_A81B, 0);
1199
1200 WRITE(REG_A6XX_SP_UNKNOWN_B183, 0);
1201
1202 WRITE(REG_A6XX_GRAS_UNKNOWN_8099, 0);
1203 WRITE(REG_A6XX_GRAS_VS_LAYER_CNTL, 0);
1204 WRITE(REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1205 WRITE(REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1206 WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
1207 WRITE(REG_A6XX_VPC_UNKNOWN_9211, 0);
1208 WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
1209 WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
1210 WRITE(REG_A6XX_SP_TP_SAMPLE_CONFIG, 0);
1211 /* NOTE blob seems to (mostly?) use 0xb2 for SP_TP_UNKNOWN_B309
1212 * but this seems to kill texture gather offsets.
1213 */
1214 WRITE(REG_A6XX_SP_TP_UNKNOWN_B309, 0xa2);
1215 WRITE(REG_A6XX_RB_SAMPLE_CONFIG, 0);
1216 WRITE(REG_A6XX_GRAS_SAMPLE_CONFIG, 0);
1217 WRITE(REG_A6XX_RB_Z_BOUNDS_MIN, 0);
1218 WRITE(REG_A6XX_RB_Z_BOUNDS_MAX, 0);
1219 WRITE(REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1220
1221 emit_marker6(ring, 7);
1222
1223 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
1224 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
1225
1226 WRITE(REG_A6XX_VFD_UNKNOWN_A008, 0);
1227
1228 OUT_PKT4(ring, REG_A6XX_PC_MODE_CNTL, 1);
1229 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
1230
1231 /* we don't use this yet.. probably best to disable.. */
1232 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1233 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1234 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1235 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1236 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1237 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1238
1239 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1240 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
1241
1242 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1243 OUT_RING(ring, 0x00000000);
1244
1245 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
1246 OUT_RING(ring, 0x00000000);
1247
1248 fd_log(batch, "END RESTORE");
1249 }
1250
1251 static void
1252 fd6_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
1253 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
1254 unsigned sizedwords)
1255 {
1256 struct fd_bo *src_bo = fd_resource(src)->bo;
1257 struct fd_bo *dst_bo = fd_resource(dst)->bo;
1258 unsigned i;
1259
1260 for (i = 0; i < sizedwords; i++) {
1261 OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
1262 OUT_RING(ring, 0x00000000);
1263 OUT_RELOC(ring, dst_bo, dst_off, 0, 0);
1264 OUT_RELOC(ring, src_bo, src_off, 0, 0);
1265
1266 dst_off += 4;
1267 src_off += 4;
1268 }
1269 }
1270
1271 /* this is *almost* the same as fd6_cache_flush().. which I guess
1272 * could be re-worked to be something a bit more generic w/ param
1273 * indicating what needs to be flushed.. although that would mean
1274 * figuring out which events trigger what state to flush..
1275 */
1276 static void
1277 fd6_framebuffer_barrier(struct fd_context *ctx)
1278 {
1279 struct fd6_context *fd6_ctx = fd6_context(ctx);
1280 struct fd_batch *batch = ctx->batch;
1281 struct fd_ringbuffer *ring = batch->draw;
1282 unsigned seqno;
1283
1284 seqno = fd6_event_write(batch, ring, RB_DONE_TS, true);
1285
1286 OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);
1287 OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
1288 CP_WAIT_REG_MEM_0_POLL_MEMORY);
1289 OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
1290 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(seqno));
1291 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(~0));
1292 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
1293
1294 fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
1295 fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
1296
1297 seqno = fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
1298
1299 fd6_event_write(batch, ring, 0x31, false);
1300
1301 OUT_PKT7(ring, CP_WAIT_MEM_GTE, 4);
1302 OUT_RING(ring, CP_WAIT_MEM_GTE_0_RESERVED(0));
1303 OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
1304 OUT_RING(ring, CP_WAIT_MEM_GTE_3_REF(seqno));
1305 }
1306
1307 void
1308 fd6_emit_init_screen(struct pipe_screen *pscreen)
1309 {
1310 struct fd_screen *screen = fd_screen(pscreen);
1311 screen->emit_ib = fd6_emit_ib;
1312 screen->mem_to_mem = fd6_mem_to_mem;
1313 }
1314
1315 void
1316 fd6_emit_init(struct pipe_context *pctx)
1317 {
1318 struct fd_context *ctx = fd_context(pctx);
1319 ctx->framebuffer_barrier = fd6_framebuffer_barrier;
1320 }