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freedreno: Use explicit *_NONE enum for undefined formats
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_helpers.h"
32 #include "util/format/u_format.h"
33 #include "util/u_viewport.h"
34
35 #include "freedreno_log.h"
36 #include "freedreno_resource.h"
37 #include "freedreno_query_hw.h"
38
39 #include "fd6_emit.h"
40 #include "fd6_blend.h"
41 #include "fd6_const.h"
42 #include "fd6_context.h"
43 #include "fd6_image.h"
44 #include "fd6_pack.h"
45 #include "fd6_program.h"
46 #include "fd6_rasterizer.h"
47 #include "fd6_texture.h"
48 #include "fd6_format.h"
49 #include "fd6_zsa.h"
50
51 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
52 * the same as a6xx then move this somewhere common ;-)
53 *
54 * Entry layout looks like (total size, 0x60 bytes):
55 */
56
57 struct PACKED bcolor_entry {
58 uint32_t fp32[4];
59 uint16_t ui16[4];
60 int16_t si16[4];
61 uint16_t fp16[4];
62 uint16_t rgb565;
63 uint16_t rgb5a1;
64 uint16_t rgba4;
65 uint8_t __pad0[2];
66 uint8_t ui8[4];
67 int8_t si8[4];
68 uint32_t rgb10a2;
69 uint32_t z24; /* also s8? */
70 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
71 uint8_t __pad1[56];
72 };
73
74 #define FD6_BORDER_COLOR_SIZE sizeof(struct bcolor_entry)
75 #define FD6_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD6_BORDER_COLOR_SIZE)
76
77 static void
78 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
79 {
80 unsigned i, j;
81 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
82
83 for (i = 0; i < tex->num_samplers; i++) {
84 struct bcolor_entry *e = &entries[i];
85 struct pipe_sampler_state *sampler = tex->samplers[i];
86 union pipe_color_union *bc;
87
88 if (!sampler)
89 continue;
90
91 bc = &sampler->border_color;
92
93 /*
94 * XXX HACK ALERT XXX
95 *
96 * The border colors need to be swizzled in a particular
97 * format-dependent order. Even though samplers don't know about
98 * formats, we can assume that with a GL state tracker, there's a
99 * 1:1 correspondence between sampler and texture. Take advantage
100 * of that knowledge.
101 */
102 if ((i >= tex->num_textures) || !tex->textures[i])
103 continue;
104
105 struct pipe_sampler_view *view = tex->textures[i];
106 enum pipe_format format = view->format;
107 const struct util_format_description *desc =
108 util_format_description(format);
109
110 e->rgb565 = 0;
111 e->rgb5a1 = 0;
112 e->rgba4 = 0;
113 e->rgb10a2 = 0;
114 e->z24 = 0;
115
116 unsigned char swiz[4];
117
118 fd6_tex_swiz(format, swiz,
119 view->swizzle_r, view->swizzle_g,
120 view->swizzle_b, view->swizzle_a);
121
122 for (j = 0; j < 4; j++) {
123 int c = swiz[j];
124 int cd = c;
125
126 /*
127 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the
128 * stencil border color value in bc->ui[0] but according
129 * to desc->swizzle and desc->channel, the .x/.w component
130 * is NONE and the stencil value is in the y component.
131 * Meanwhile the hardware wants this in the .w component
132 * for x24s8 and the .x component for x32_s8x24.
133 */
134 if ((format == PIPE_FORMAT_X24S8_UINT) ||
135 (format == PIPE_FORMAT_X32_S8X24_UINT)) {
136 if (j == 0) {
137 c = 1;
138 cd = (format == PIPE_FORMAT_X32_S8X24_UINT) ? 0 : 3;
139 } else {
140 continue;
141 }
142 }
143
144 if (c >= 4)
145 continue;
146
147 if (desc->channel[c].pure_integer) {
148 uint16_t clamped;
149 switch (desc->channel[c].size) {
150 case 2:
151 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
152 clamped = CLAMP(bc->ui[j], 0, 0x3);
153 break;
154 case 8:
155 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
156 clamped = CLAMP(bc->i[j], -128, 127);
157 else
158 clamped = CLAMP(bc->ui[j], 0, 255);
159 break;
160 case 10:
161 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
162 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
163 break;
164 case 16:
165 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
166 clamped = CLAMP(bc->i[j], -32768, 32767);
167 else
168 clamped = CLAMP(bc->ui[j], 0, 65535);
169 break;
170 default:
171 assert(!"Unexpected bit size");
172 case 32:
173 clamped = 0;
174 break;
175 }
176 e->fp32[cd] = bc->ui[j];
177 e->fp16[cd] = clamped;
178 } else {
179 float f = bc->f[j];
180 float f_u = CLAMP(f, 0, 1);
181 float f_s = CLAMP(f, -1, 1);
182
183 e->fp32[c] = fui(f);
184 e->fp16[c] = util_float_to_half(f);
185 e->srgb[c] = util_float_to_half(f_u);
186 e->ui16[c] = f_u * 0xffff;
187 e->si16[c] = f_s * 0x7fff;
188 e->ui8[c] = f_u * 0xff;
189 e->si8[c] = f_s * 0x7f;
190 if (c == 1)
191 e->rgb565 |= (int)(f_u * 0x3f) << 5;
192 else if (c < 3)
193 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
194 if (c == 3)
195 e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
196 else
197 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
198 if (c == 3)
199 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
200 else
201 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
202 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
203 if (c == 0)
204 e->z24 = f_u * 0xffffff;
205 }
206 }
207
208 #ifdef DEBUG
209 memset(&e->__pad0, 0, sizeof(e->__pad0));
210 memset(&e->__pad1, 0, sizeof(e->__pad1));
211 #endif
212 }
213 }
214
215 static void
216 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
217 {
218 struct fd6_context *fd6_ctx = fd6_context(ctx);
219 struct bcolor_entry *entries;
220 unsigned off;
221 void *ptr;
222
223 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
224
225 u_upload_alloc(fd6_ctx->border_color_uploader,
226 0, FD6_BORDER_COLOR_UPLOAD_SIZE,
227 FD6_BORDER_COLOR_UPLOAD_SIZE, &off,
228 &fd6_ctx->border_color_buf,
229 &ptr);
230
231 entries = ptr;
232
233 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
234 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
235 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
236
237 OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
238 OUT_RELOC(ring, fd_resource(fd6_ctx->border_color_buf)->bo, off, 0, 0);
239
240 u_upload_unmap(fd6_ctx->border_color_uploader);
241 }
242
243 static void
244 fd6_emit_fb_tex(struct fd_ringbuffer *state, struct fd_context *ctx)
245 {
246 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
247 struct pipe_surface *psurf = pfb->cbufs[0];
248 struct fd_resource *rsc = fd_resource(psurf->texture);
249
250 uint32_t texconst0 = fd6_tex_const_0(psurf->texture, psurf->u.tex.level,
251 psurf->format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
252 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W);
253
254 /* always TILE6_2 mode in GMEM.. which also means no swap: */
255 texconst0 &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
256 texconst0 |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
257
258 OUT_RING(state, texconst0);
259 OUT_RING(state, A6XX_TEX_CONST_1_WIDTH(pfb->width) |
260 A6XX_TEX_CONST_1_HEIGHT(pfb->height));
261 OUT_RINGP(state, A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
262 A6XX_TEX_CONST_2_FETCHSIZE(TFETCH6_2_BYTE),
263 &ctx->batch->fb_read_patches);
264 OUT_RING(state, A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size));
265
266 OUT_RING(state, A6XX_TEX_CONST_4_BASE_LO(ctx->screen->gmem_base));
267 OUT_RING(state, A6XX_TEX_CONST_5_BASE_HI(ctx->screen->gmem_base >> 32) |
268 A6XX_TEX_CONST_5_DEPTH(1));
269 OUT_RING(state, 0); /* texconst6 */
270 OUT_RING(state, 0); /* texconst7 */
271 OUT_RING(state, 0); /* texconst8 */
272 OUT_RING(state, 0); /* texconst9 */
273 OUT_RING(state, 0); /* texconst10 */
274 OUT_RING(state, 0); /* texconst11 */
275 OUT_RING(state, 0);
276 OUT_RING(state, 0);
277 OUT_RING(state, 0);
278 OUT_RING(state, 0);
279 }
280
281 bool
282 fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
283 enum pipe_shader_type type, struct fd_texture_stateobj *tex,
284 unsigned bcolor_offset,
285 /* can be NULL if no image/SSBO/fb state to merge in: */
286 const struct ir3_shader_variant *v, struct fd_context *ctx)
287 {
288 bool needs_border = false;
289 unsigned opcode, tex_samp_reg, tex_const_reg, tex_count_reg;
290 enum a6xx_state_block sb;
291
292 switch (type) {
293 case PIPE_SHADER_VERTEX:
294 sb = SB6_VS_TEX;
295 opcode = CP_LOAD_STATE6_GEOM;
296 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
297 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
298 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
299 break;
300 case PIPE_SHADER_TESS_CTRL:
301 sb = SB6_HS_TEX;
302 opcode = CP_LOAD_STATE6_GEOM;
303 tex_samp_reg = REG_A6XX_SP_HS_TEX_SAMP_LO;
304 tex_const_reg = REG_A6XX_SP_HS_TEX_CONST_LO;
305 tex_count_reg = REG_A6XX_SP_HS_TEX_COUNT;
306 break;
307 case PIPE_SHADER_TESS_EVAL:
308 sb = SB6_DS_TEX;
309 opcode = CP_LOAD_STATE6_GEOM;
310 tex_samp_reg = REG_A6XX_SP_DS_TEX_SAMP_LO;
311 tex_const_reg = REG_A6XX_SP_DS_TEX_CONST_LO;
312 tex_count_reg = REG_A6XX_SP_DS_TEX_COUNT;
313 break;
314 case PIPE_SHADER_GEOMETRY:
315 sb = SB6_GS_TEX;
316 opcode = CP_LOAD_STATE6_GEOM;
317 tex_samp_reg = REG_A6XX_SP_GS_TEX_SAMP_LO;
318 tex_const_reg = REG_A6XX_SP_GS_TEX_CONST_LO;
319 tex_count_reg = REG_A6XX_SP_GS_TEX_COUNT;
320 break;
321 case PIPE_SHADER_FRAGMENT:
322 sb = SB6_FS_TEX;
323 opcode = CP_LOAD_STATE6_FRAG;
324 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
325 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
326 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
327 break;
328 case PIPE_SHADER_COMPUTE:
329 sb = SB6_CS_TEX;
330 opcode = CP_LOAD_STATE6_FRAG;
331 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
332 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
333 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
334 break;
335 default:
336 unreachable("bad state block");
337 }
338
339 if (tex->num_samplers > 0) {
340 struct fd_ringbuffer *state =
341 fd_ringbuffer_new_object(pipe, tex->num_samplers * 4 * 4);
342 for (unsigned i = 0; i < tex->num_samplers; i++) {
343 static const struct fd6_sampler_stateobj dummy_sampler = {};
344 const struct fd6_sampler_stateobj *sampler = tex->samplers[i] ?
345 fd6_sampler_stateobj(tex->samplers[i]) : &dummy_sampler;
346 OUT_RING(state, sampler->texsamp0);
347 OUT_RING(state, sampler->texsamp1);
348 OUT_RING(state, sampler->texsamp2 |
349 A6XX_TEX_SAMP_2_BCOLOR_OFFSET((i + bcolor_offset) * sizeof(struct bcolor_entry)));
350 OUT_RING(state, sampler->texsamp3);
351 needs_border |= sampler->needs_border;
352 }
353
354 /* output sampler state: */
355 OUT_PKT7(ring, opcode, 3);
356 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
357 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
358 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
359 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
360 CP_LOAD_STATE6_0_NUM_UNIT(tex->num_samplers));
361 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
362
363 OUT_PKT4(ring, tex_samp_reg, 2);
364 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
365
366 fd_ringbuffer_del(state);
367 }
368
369 unsigned num_merged_textures = tex->num_textures;
370 unsigned num_textures = tex->num_textures;
371 if (v) {
372 num_merged_textures += v->image_mapping.num_tex;
373
374 if (v->fb_read)
375 num_merged_textures++;
376
377 /* There could be more bound textures than what the shader uses.
378 * Which isn't known at shader compile time. So in the case we
379 * are merging tex state, only emit the textures that the shader
380 * uses (since the image/SSBO related tex state comes immediately
381 * after)
382 */
383 num_textures = v->image_mapping.tex_base;
384 }
385
386 if (num_merged_textures > 0) {
387 struct fd_ringbuffer *state =
388 fd_ringbuffer_new_object(pipe, num_merged_textures * 16 * 4);
389 for (unsigned i = 0; i < num_textures; i++) {
390 static const struct fd6_pipe_sampler_view dummy_view = {};
391 const struct fd6_pipe_sampler_view *view = tex->textures[i] ?
392 fd6_pipe_sampler_view(tex->textures[i]) : &dummy_view;
393 struct fd_resource *rsc = NULL;
394
395 if (view->base.texture)
396 rsc = fd_resource(view->base.texture);
397
398 OUT_RING(state, view->texconst0);
399 OUT_RING(state, view->texconst1);
400 OUT_RING(state, view->texconst2);
401 OUT_RING(state, view->texconst3);
402
403 if (rsc) {
404 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
405 rsc = rsc->stencil;
406 OUT_RELOC(state, rsc->bo, view->offset,
407 (uint64_t)view->texconst5 << 32, 0);
408 } else {
409 OUT_RING(state, 0x00000000);
410 OUT_RING(state, view->texconst5);
411 }
412
413 OUT_RING(state, view->texconst6);
414
415 if (rsc && view->ubwc_enabled) {
416 OUT_RELOC(state, rsc->bo, view->ubwc_offset, 0, 0);
417 } else {
418 OUT_RING(state, 0);
419 OUT_RING(state, 0);
420 }
421
422 OUT_RING(state, view->texconst9);
423 OUT_RING(state, view->texconst10);
424 OUT_RING(state, view->texconst11);
425 OUT_RING(state, 0);
426 OUT_RING(state, 0);
427 OUT_RING(state, 0);
428 OUT_RING(state, 0);
429 }
430
431 if (v) {
432 const struct ir3_ibo_mapping *mapping = &v->image_mapping;
433 struct fd_shaderbuf_stateobj *buf = &ctx->shaderbuf[type];
434 struct fd_shaderimg_stateobj *img = &ctx->shaderimg[type];
435
436 for (unsigned i = 0; i < mapping->num_tex; i++) {
437 unsigned idx = mapping->tex_to_image[i];
438 if (idx & IBO_SSBO) {
439 fd6_emit_ssbo_tex(state, &buf->sb[idx & ~IBO_SSBO]);
440 } else {
441 fd6_emit_image_tex(state, &img->si[idx]);
442 }
443 }
444
445 if (v->fb_read) {
446 fd6_emit_fb_tex(state, ctx);
447 }
448 }
449
450 /* emit texture state: */
451 OUT_PKT7(ring, opcode, 3);
452 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
453 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
454 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
455 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
456 CP_LOAD_STATE6_0_NUM_UNIT(num_merged_textures));
457 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
458
459 OUT_PKT4(ring, tex_const_reg, 2);
460 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
461
462 fd_ringbuffer_del(state);
463 }
464
465 OUT_PKT4(ring, tex_count_reg, 1);
466 OUT_RING(ring, num_merged_textures);
467
468 return needs_border;
469 }
470
471 /* Emits combined texture state, which also includes any Image/SSBO
472 * related texture state merged in (because we must have all texture
473 * state for a given stage in a single buffer). In the fast-path, if
474 * we don't need to merge in any image/ssbo related texture state, we
475 * just use cached texture stateobj. Otherwise we generate a single-
476 * use stateobj.
477 *
478 * TODO Is there some sane way we can still use cached texture stateobj
479 * with image/ssbo in use?
480 *
481 * returns whether border_color is required:
482 */
483 static bool
484 fd6_emit_combined_textures(struct fd_ringbuffer *ring, struct fd6_emit *emit,
485 enum pipe_shader_type type, const struct ir3_shader_variant *v)
486 {
487 struct fd_context *ctx = emit->ctx;
488 bool needs_border = false;
489
490 static const struct {
491 enum fd6_state_id state_id;
492 unsigned enable_mask;
493 } s[PIPE_SHADER_TYPES] = {
494 [PIPE_SHADER_VERTEX] = { FD6_GROUP_VS_TEX, ENABLE_ALL },
495 [PIPE_SHADER_TESS_CTRL] = { FD6_GROUP_HS_TEX, ENABLE_ALL },
496 [PIPE_SHADER_TESS_EVAL] = { FD6_GROUP_DS_TEX, ENABLE_ALL },
497 [PIPE_SHADER_GEOMETRY] = { FD6_GROUP_GS_TEX, ENABLE_ALL },
498 [PIPE_SHADER_FRAGMENT] = { FD6_GROUP_FS_TEX, ENABLE_DRAW },
499 };
500
501 debug_assert(s[type].state_id);
502
503 if (!v->image_mapping.num_tex && !v->fb_read) {
504 /* in the fast-path, when we don't have to mix in any image/SSBO
505 * related texture state, we can just lookup the stateobj and
506 * re-emit that:
507 *
508 * Also, framebuffer-read is a slow-path because an extra
509 * texture needs to be inserted.
510 *
511 * TODO we can probably simmplify things if we also treated
512 * border_color as a slow-path.. this way the tex state key
513 * wouldn't depend on bcolor_offset.. but fb_read might rather
514 * be *somehow* a fast-path if we eventually used it for PLS.
515 * I suppose there would be no harm in just *always* inserting
516 * an fb_read texture?
517 */
518 if ((ctx->dirty_shader[type] & FD_DIRTY_SHADER_TEX) &&
519 ctx->tex[type].num_textures > 0) {
520 struct fd6_texture_state *tex = fd6_texture_state(ctx,
521 type, &ctx->tex[type]);
522
523 needs_border |= tex->needs_border;
524
525 fd6_emit_add_group(emit, tex->stateobj, s[type].state_id,
526 s[type].enable_mask);
527 }
528 } else {
529 /* In the slow-path, create a one-shot texture state object
530 * if either TEX|PROG|SSBO|IMAGE state is dirty:
531 */
532 if ((ctx->dirty_shader[type] &
533 (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
534 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) ||
535 v->fb_read) {
536 struct fd_texture_stateobj *tex = &ctx->tex[type];
537 struct fd_ringbuffer *stateobj =
538 fd_submit_new_ringbuffer(ctx->batch->submit,
539 0x1000, FD_RINGBUFFER_STREAMING);
540 unsigned bcolor_offset =
541 fd6_border_color_offset(ctx, type, tex);
542
543 needs_border |= fd6_emit_textures(ctx->pipe, stateobj, type, tex,
544 bcolor_offset, v, ctx);
545
546 fd6_emit_take_group(emit, stateobj, s[type].state_id,
547 s[type].enable_mask);
548 }
549 }
550
551 return needs_border;
552 }
553
554 static struct fd_ringbuffer *
555 build_vbo_state(struct fd6_emit *emit, const struct ir3_shader_variant *vp)
556 {
557 const struct fd_vertex_state *vtx = emit->vtx;
558
559 /* Determine which inputs need VFD state */
560 int32_t map[32];
561 int32_t cnt = 0;
562 for (int32_t i = 0; i <= vp->inputs_count; i++) {
563 if (vp->inputs[i].sysval)
564 continue;
565 if (vp->inputs[i].compmask) {
566 map[cnt++] = i;
567 }
568 }
569
570 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
571 4 * (5 + cnt * 7), FD_RINGBUFFER_STREAMING);
572
573 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_0, 1);
574 OUT_RING(ring, A6XX_VFD_CONTROL_0_FETCH_CNT(cnt) |
575 A6XX_VFD_CONTROL_0_DECODE_CNT(cnt));
576
577 OUT_PKT4(ring, REG_A6XX_VFD_FETCH(0), 4 * cnt);
578 for (int32_t j = 0; j < cnt; j++) {
579 int32_t i = map[j];
580 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
581 const struct pipe_vertex_buffer *vb =
582 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
583 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
584 uint32_t off = vb->buffer_offset + elem->src_offset;
585 uint32_t size = fd_bo_size(rsc->bo) - off;
586
587 #ifdef DEBUG
588 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
589 */
590 if (off > fd_bo_size(rsc->bo)) {
591 OUT_RING(ring, 0);
592 OUT_RING(ring, 0);
593 OUT_RING(ring, 0);
594 OUT_RING(ring, 0);
595 continue;
596 }
597 #endif
598
599 OUT_RELOC(ring, rsc->bo, off, 0, 0);
600 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
601 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
602 }
603
604 OUT_PKT4(ring, REG_A6XX_VFD_DECODE(0), 2 * cnt);
605 for (int32_t j = 0; j < cnt; j++) {
606 int32_t i = map[j];
607 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
608 enum pipe_format pfmt = elem->src_format;
609 enum a6xx_format fmt = fd6_pipe2vtx(pfmt);
610 bool isint = util_format_is_pure_integer(pfmt);
611 debug_assert(fmt != FMT6_NONE);
612
613 OUT_RING(ring, A6XX_VFD_DECODE_INSTR_IDX(j) |
614 A6XX_VFD_DECODE_INSTR_FORMAT(fmt) |
615 COND(elem->instance_divisor, A6XX_VFD_DECODE_INSTR_INSTANCED) |
616 A6XX_VFD_DECODE_INSTR_SWAP(fd6_pipe2swap(pfmt)) |
617 A6XX_VFD_DECODE_INSTR_UNK30 |
618 COND(!isint, A6XX_VFD_DECODE_INSTR_FLOAT));
619 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
620 }
621
622 OUT_PKT4(ring, REG_A6XX_VFD_DEST_CNTL(0), cnt);
623 for (int32_t j = 0; j < cnt; j++) {
624 int32_t i = map[j];
625
626 OUT_RING(ring, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
627 A6XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
628 }
629
630 return ring;
631 }
632
633 static struct fd_ringbuffer *
634 build_lrz(struct fd6_emit *emit, bool binning_pass)
635 {
636 struct fd_context *ctx = emit->ctx;
637 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
638 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
639 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
640 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
641 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
642 uint32_t rb_lrz_cntl = zsa->rb_lrz_cntl;
643
644 if (zsa->invalidate_lrz) {
645 rsc->lrz_valid = false;
646 gras_lrz_cntl = 0;
647 rb_lrz_cntl = 0;
648 } else if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid) {
649 gras_lrz_cntl = 0;
650 rb_lrz_cntl = 0;
651 } else if (binning_pass && blend->lrz_write && zsa->lrz_write) {
652 gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_LRZ_WRITE;
653 }
654
655 struct fd6_context *fd6_ctx = fd6_context(ctx);
656 if ((fd6_ctx->last.lrz[binning_pass].gras_lrz_cntl == gras_lrz_cntl) &&
657 (fd6_ctx->last.lrz[binning_pass].rb_lrz_cntl == rb_lrz_cntl) &&
658 !ctx->last.dirty)
659 return NULL;
660
661 fd6_ctx->last.lrz[binning_pass].gras_lrz_cntl = gras_lrz_cntl;
662 fd6_ctx->last.lrz[binning_pass].rb_lrz_cntl = rb_lrz_cntl;
663
664 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(ctx->batch->submit,
665 16, FD_RINGBUFFER_STREAMING);
666
667 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
668 OUT_RING(ring, gras_lrz_cntl);
669
670 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
671 OUT_RING(ring, rb_lrz_cntl);
672
673 return ring;
674 }
675
676 static void
677 fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3_stream_output_info *info)
678 {
679 struct fd_context *ctx = emit->ctx;
680 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
681 struct fd_streamout_stateobj *so = &ctx->streamout;
682
683 emit->streamout_mask = 0;
684
685 for (unsigned i = 0; i < so->num_targets; i++) {
686 struct pipe_stream_output_target *target = so->targets[i];
687
688 if (!target)
689 continue;
690
691 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(i), 3);
692 /* VPC_SO[i].BUFFER_BASE_LO: */
693 OUT_RELOC(ring, fd_resource(target->buffer)->bo, target->buffer_offset, 0, 0);
694 OUT_RING(ring, target->buffer_size - target->buffer_offset);
695
696 if (so->reset & (1 << i)) {
697 unsigned offset = (so->offsets[i] * info->stride[i] * 4);
698 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(i), 1);
699 OUT_RING(ring, offset);
700 } else {
701 OUT_PKT7(ring, CP_MEM_TO_REG, 3);
702 OUT_RING(ring, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i)) |
703 CP_MEM_TO_REG_0_SHIFT_BY_2 | CP_MEM_TO_REG_0_UNK31 |
704 CP_MEM_TO_REG_0_CNT(0));
705 OUT_RELOC(ring, control_ptr(fd6_context(ctx), flush_base[i].offset));
706 }
707
708 OUT_PKT4(ring, REG_A6XX_VPC_SO_FLUSH_BASE_LO(i), 2);
709 OUT_RELOC(ring, control_ptr(fd6_context(ctx), flush_base[i]));
710
711 so->reset &= ~(1 << i);
712
713 emit->streamout_mask |= (1 << i);
714 }
715
716 if (emit->streamout_mask) {
717 fd6_emit_add_group(emit, prog->streamout_stateobj, FD6_GROUP_SO, ENABLE_ALL);
718 } else {
719 /* If we transition from a draw with streamout to one without, turn
720 * off streamout.
721 */
722 if (ctx->last.streamout_mask != 0) {
723 struct fd_ringbuffer *obj = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
724 5 * 4, FD_RINGBUFFER_STREAMING);
725
726 OUT_PKT7(obj, CP_CONTEXT_REG_BUNCH, 4);
727 OUT_RING(obj, REG_A6XX_VPC_SO_CNTL);
728 OUT_RING(obj, 0);
729 OUT_RING(obj, REG_A6XX_VPC_SO_BUF_CNTL);
730 OUT_RING(obj, 0);
731
732 fd6_emit_take_group(emit, obj, FD6_GROUP_SO, ENABLE_ALL);
733 }
734 }
735
736 ctx->last.streamout_mask = emit->streamout_mask;
737 }
738
739 void
740 fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
741 {
742 struct fd_context *ctx = emit->ctx;
743 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
744 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
745 const struct ir3_shader_variant *vs = emit->vs;
746 const struct ir3_shader_variant *hs = emit->hs;
747 const struct ir3_shader_variant *ds = emit->ds;
748 const struct ir3_shader_variant *gs = emit->gs;
749 const struct ir3_shader_variant *fs = emit->fs;
750 const enum fd_dirty_3d_state dirty = emit->dirty;
751 bool needs_border = false;
752
753 emit_marker6(ring, 5);
754
755 /* NOTE: we track fb_read differently than _BLEND_ENABLED since
756 * we might at some point decide to do sysmem in some cases when
757 * blend is enabled:
758 */
759 if (fs->fb_read)
760 ctx->batch->gmem_reason |= FD_GMEM_FB_READ;
761
762 if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE)) {
763 struct fd_ringbuffer *state;
764
765 state = build_vbo_state(emit, emit->vs);
766 fd6_emit_take_group(emit, state, FD6_GROUP_VBO, ENABLE_ALL);
767 }
768
769 if (dirty & FD_DIRTY_ZSA) {
770 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
771
772 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
773 fd6_emit_add_group(emit, zsa->stateobj_no_alpha, FD6_GROUP_ZSA, ENABLE_ALL);
774 else
775 fd6_emit_add_group(emit, zsa->stateobj, FD6_GROUP_ZSA, ENABLE_ALL);
776 }
777
778 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG)) && pfb->zsbuf) {
779 struct fd_ringbuffer *state;
780
781 state = build_lrz(emit, false);
782 if (state) {
783 fd6_emit_take_group(emit, state, FD6_GROUP_LRZ, ENABLE_DRAW);
784 }
785
786 state = build_lrz(emit, true);
787 if (state) {
788 fd6_emit_take_group(emit, state,
789 FD6_GROUP_LRZ_BINNING, CP_SET_DRAW_STATE__0_BINNING);
790 }
791 }
792
793 if (dirty & FD_DIRTY_STENCIL_REF) {
794 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
795
796 OUT_PKT4(ring, REG_A6XX_RB_STENCILREF, 1);
797 OUT_RING(ring, A6XX_RB_STENCILREF_REF(sr->ref_value[0]) |
798 A6XX_RB_STENCILREF_BFREF(sr->ref_value[1]));
799 }
800
801 /* NOTE: scissor enabled bit is part of rasterizer state, but
802 * fd_rasterizer_state_bind() will mark scissor dirty if needed:
803 */
804 if (dirty & FD_DIRTY_SCISSOR) {
805 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
806 emit->ctx->batch->submit, 3*4, FD_RINGBUFFER_STREAMING);
807 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
808
809 OUT_REG(ring,
810 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0(
811 .x = scissor->minx,
812 .y = scissor->miny
813 ),
814 A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0(
815 .x = MAX2(scissor->maxx, 1) - 1,
816 .y = MAX2(scissor->maxy, 1) - 1
817 )
818 );
819
820 fd6_emit_take_group(emit, ring, FD6_GROUP_SCISSOR, ENABLE_ALL);
821
822 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
823 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
824 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
825 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
826 }
827
828 if (dirty & FD_DIRTY_VIEWPORT) {
829 struct pipe_scissor_state *scissor = &ctx->viewport_scissor;
830
831 OUT_REG(ring,
832 A6XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]),
833 A6XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]),
834 A6XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]),
835 A6XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]),
836 A6XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]),
837 A6XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2])
838 );
839
840 OUT_REG(ring,
841 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0(
842 .x = scissor->minx,
843 .y = scissor->miny
844 ),
845 A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0(
846 .x = MAX2(scissor->maxx, 1) - 1,
847 .y = MAX2(scissor->maxy, 1) - 1
848 )
849 );
850
851 unsigned guardband_x = fd_calc_guardband(scissor->maxx - scissor->minx);
852 unsigned guardband_y = fd_calc_guardband(scissor->maxy - scissor->miny);
853
854 OUT_REG(ring, A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ(
855 .horz = guardband_x,
856 .vert = guardband_y
857 )
858 );
859 }
860
861 if (dirty & FD_DIRTY_PROG) {
862 fd6_emit_add_group(emit, prog->config_stateobj, FD6_GROUP_PROG_CONFIG, ENABLE_ALL);
863 fd6_emit_add_group(emit, prog->stateobj, FD6_GROUP_PROG, ENABLE_DRAW);
864 fd6_emit_add_group(emit, prog->binning_stateobj,
865 FD6_GROUP_PROG_BINNING, CP_SET_DRAW_STATE__0_BINNING);
866
867 /* emit remaining streaming program state, ie. what depends on
868 * other emit state, so cannot be pre-baked.
869 */
870 struct fd_ringbuffer *streaming = fd6_program_interp_state(emit);
871
872 fd6_emit_take_group(emit, streaming, FD6_GROUP_PROG_INTERP, ENABLE_DRAW);
873 }
874
875 if (dirty & FD_DIRTY_RASTERIZER) {
876 struct fd_ringbuffer *stateobj =
877 fd6_rasterizer_state(ctx, emit->primitive_restart);
878 fd6_emit_add_group(emit, stateobj,
879 FD6_GROUP_RASTERIZER, ENABLE_ALL);
880 }
881
882 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER_DISCARD | FD_DIRTY_PROG)) {
883 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
884 emit->ctx->batch->submit, 5 * 4, FD_RINGBUFFER_STREAMING);
885
886 unsigned nr = pfb->nr_cbufs;
887
888 if (ctx->rasterizer->rasterizer_discard)
889 nr = 0;
890
891 OUT_PKT4(ring, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
892 OUT_RING(ring, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
893 COND(fs->writes_smask && pfb->samples > 1,
894 A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
895 OUT_RING(ring, A6XX_RB_FS_OUTPUT_CNTL1_MRT(nr));
896
897 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL1, 1);
898 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL1_MRT(nr));
899
900 fd6_emit_take_group(emit, ring, FD6_GROUP_PROG_FB_RAST, ENABLE_DRAW);
901 }
902
903 fd6_emit_consts(emit);
904
905 struct ir3_stream_output_info *info = &fd6_last_shader(prog)->shader->stream_output;
906 if (info->num_outputs)
907 fd6_emit_streamout(ring, emit, info);
908
909 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK)) {
910 struct fd6_blend_variant *blend = fd6_blend_variant(ctx->blend,
911 pfb->samples, ctx->sample_mask);
912 fd6_emit_add_group(emit, blend->stateobj, FD6_GROUP_BLEND, ENABLE_DRAW);
913 }
914
915 if (dirty & FD_DIRTY_BLEND_COLOR) {
916 struct pipe_blend_color *bcolor = &ctx->blend_color;
917 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
918 emit->ctx->batch->submit, 5*4, FD_RINGBUFFER_STREAMING);
919
920 OUT_REG(ring,
921 A6XX_RB_BLEND_RED_F32(bcolor->color[0]),
922 A6XX_RB_BLEND_GREEN_F32(bcolor->color[1]),
923 A6XX_RB_BLEND_BLUE_F32(bcolor->color[2]),
924 A6XX_RB_BLEND_ALPHA_F32(bcolor->color[3])
925 );
926
927 fd6_emit_take_group(emit, ring, FD6_GROUP_BLEND_COLOR, ENABLE_DRAW);
928 }
929
930 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_VERTEX, vs);
931 if (hs) {
932 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_TESS_CTRL, hs);
933 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_TESS_EVAL, ds);
934 }
935 if (gs) {
936 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_GEOMETRY, gs);
937 }
938 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_FRAGMENT, fs);
939
940 if (needs_border)
941 emit_border_color(ctx, ring);
942
943 if (hs) {
944 debug_assert(ir3_shader_nibo(hs) == 0);
945 debug_assert(ir3_shader_nibo(ds) == 0);
946 }
947 if (gs) {
948 debug_assert(ir3_shader_nibo(gs) == 0);
949 }
950
951 #define DIRTY_IBO (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE | \
952 FD_DIRTY_SHADER_PROG)
953 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & DIRTY_IBO) {
954 struct fd_ringbuffer *state =
955 fd6_build_ibo_state(ctx, fs, PIPE_SHADER_FRAGMENT);
956 struct fd_ringbuffer *obj = fd_submit_new_ringbuffer(
957 ctx->batch->submit, 0x100, FD_RINGBUFFER_STREAMING);
958
959 OUT_PKT7(obj, CP_LOAD_STATE6, 3);
960 OUT_RING(obj, CP_LOAD_STATE6_0_DST_OFF(0) |
961 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
962 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
963 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_IBO) |
964 CP_LOAD_STATE6_0_NUM_UNIT(ir3_shader_nibo(fs)));
965 OUT_RB(obj, state);
966
967 OUT_PKT4(obj, REG_A6XX_SP_IBO_LO, 2);
968 OUT_RB(obj, state);
969
970 /* TODO if we used CP_SET_DRAW_STATE for compute shaders, we could
971 * de-duplicate this from program->config_stateobj
972 */
973 OUT_PKT4(obj, REG_A6XX_SP_IBO_COUNT, 1);
974 OUT_RING(obj, ir3_shader_nibo(fs));
975
976 fd6_emit_ibo_consts(emit, fs, PIPE_SHADER_FRAGMENT, ring);
977
978 fd6_emit_take_group(emit, obj, FD6_GROUP_IBO, ENABLE_DRAW);
979 fd_ringbuffer_del(state);
980 }
981
982 if (emit->num_groups > 0) {
983 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3 * emit->num_groups);
984 for (unsigned i = 0; i < emit->num_groups; i++) {
985 struct fd6_state_group *g = &emit->groups[i];
986 unsigned n = g->stateobj ?
987 fd_ringbuffer_size(g->stateobj) / 4 : 0;
988
989 debug_assert((g->enable_mask & ~ENABLE_ALL) == 0);
990
991 if (n == 0) {
992 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
993 CP_SET_DRAW_STATE__0_DISABLE |
994 g->enable_mask |
995 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
996 OUT_RING(ring, 0x00000000);
997 OUT_RING(ring, 0x00000000);
998 } else {
999 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(n) |
1000 g->enable_mask |
1001 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
1002 OUT_RB(ring, g->stateobj);
1003 }
1004
1005 if (g->stateobj)
1006 fd_ringbuffer_del(g->stateobj);
1007 }
1008 emit->num_groups = 0;
1009 }
1010 }
1011
1012 void
1013 fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
1014 struct ir3_shader_variant *cp)
1015 {
1016 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
1017
1018 if (dirty & (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
1019 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) {
1020 struct fd_texture_stateobj *tex = &ctx->tex[PIPE_SHADER_COMPUTE];
1021 unsigned bcolor_offset = fd6_border_color_offset(ctx, PIPE_SHADER_COMPUTE, tex);
1022
1023 bool needs_border = fd6_emit_textures(ctx->pipe, ring, PIPE_SHADER_COMPUTE, tex,
1024 bcolor_offset, cp, ctx);
1025
1026 if (needs_border)
1027 emit_border_color(ctx, ring);
1028
1029 OUT_PKT4(ring, REG_A6XX_SP_VS_TEX_COUNT, 1);
1030 OUT_RING(ring, 0);
1031
1032 OUT_PKT4(ring, REG_A6XX_SP_HS_TEX_COUNT, 1);
1033 OUT_RING(ring, 0);
1034
1035 OUT_PKT4(ring, REG_A6XX_SP_DS_TEX_COUNT, 1);
1036 OUT_RING(ring, 0);
1037
1038 OUT_PKT4(ring, REG_A6XX_SP_GS_TEX_COUNT, 1);
1039 OUT_RING(ring, 0);
1040
1041 OUT_PKT4(ring, REG_A6XX_SP_FS_TEX_COUNT, 1);
1042 OUT_RING(ring, 0);
1043 }
1044
1045 if (dirty & (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)) {
1046 struct fd_ringbuffer *state =
1047 fd6_build_ibo_state(ctx, cp, PIPE_SHADER_COMPUTE);
1048
1049 OUT_PKT7(ring, CP_LOAD_STATE6_FRAG, 3);
1050 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
1051 CP_LOAD_STATE6_0_STATE_TYPE(ST6_IBO) |
1052 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1053 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_CS_SHADER) |
1054 CP_LOAD_STATE6_0_NUM_UNIT(ir3_shader_nibo(cp)));
1055 OUT_RB(ring, state);
1056
1057 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_LO, 2);
1058 OUT_RB(ring, state);
1059
1060 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_COUNT, 1);
1061 OUT_RING(ring, ir3_shader_nibo(cp));
1062
1063 fd_ringbuffer_del(state);
1064 }
1065 }
1066
1067
1068 /* emit setup at begin of new cmdstream buffer (don't rely on previous
1069 * state, there could have been a context switch between ioctls):
1070 */
1071 void
1072 fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
1073 {
1074 //struct fd_context *ctx = batch->ctx;
1075
1076 fd_log(batch, "START RESTORE");
1077
1078 fd6_cache_inv(batch, ring);
1079
1080 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1081 OUT_RING(ring, 0xfffff);
1082
1083 OUT_WFI5(ring);
1084
1085 WRITE(REG_A6XX_RB_UNKNOWN_8E04, 0x0);
1086 WRITE(REG_A6XX_SP_UNKNOWN_AE04, 0x8);
1087 WRITE(REG_A6XX_SP_UNKNOWN_AE00, 0);
1088 WRITE(REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
1089 WRITE(REG_A6XX_SP_UNKNOWN_B605, 0x44);
1090 WRITE(REG_A6XX_SP_UNKNOWN_B600, 0x100000);
1091 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
1092 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
1093
1094 WRITE(REG_A6XX_VPC_UNKNOWN_9600, 0);
1095 WRITE(REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
1096 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE04, 0x80000);
1097 WRITE(REG_A6XX_SP_UNKNOWN_AE03, 0x1430);
1098 WRITE(REG_A6XX_SP_IBO_COUNT, 0);
1099 WRITE(REG_A6XX_SP_UNKNOWN_B182, 0);
1100 WRITE(REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
1101 WRITE(REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
1102 WRITE(REG_A6XX_UCHE_CLIENT_PF, 4);
1103 WRITE(REG_A6XX_RB_UNKNOWN_8E01, 0x1);
1104 WRITE(REG_A6XX_SP_UNKNOWN_AB00, 0x5);
1105 WRITE(REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
1106 WRITE(REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
1107 WRITE(REG_A6XX_PC_MODE_CNTL, 0x1f);
1108
1109 OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
1110 OUT_RING(ring, 0);
1111
1112 WRITE(REG_A6XX_GRAS_UNKNOWN_8101, 0);
1113 WRITE(REG_A6XX_GRAS_SAMPLE_CNTL, 0);
1114 WRITE(REG_A6XX_GRAS_UNKNOWN_8110, 0x2);
1115
1116 WRITE(REG_A6XX_RB_UNKNOWN_8818, 0);
1117 WRITE(REG_A6XX_RB_UNKNOWN_8819, 0);
1118 WRITE(REG_A6XX_RB_UNKNOWN_881A, 0);
1119 WRITE(REG_A6XX_RB_UNKNOWN_881B, 0);
1120 WRITE(REG_A6XX_RB_UNKNOWN_881C, 0);
1121 WRITE(REG_A6XX_RB_UNKNOWN_881D, 0);
1122 WRITE(REG_A6XX_RB_UNKNOWN_881E, 0);
1123 WRITE(REG_A6XX_RB_UNKNOWN_88F0, 0);
1124
1125 WRITE(REG_A6XX_VPC_UNKNOWN_9236,
1126 A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(0));
1127 WRITE(REG_A6XX_VPC_UNKNOWN_9300, 0);
1128
1129 WRITE(REG_A6XX_VPC_SO_OVERRIDE, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
1130
1131 WRITE(REG_A6XX_PC_UNKNOWN_9990, 0);
1132 WRITE(REG_A6XX_PC_UNKNOWN_9980, 0);
1133
1134 WRITE(REG_A6XX_PC_UNKNOWN_9B07, 0);
1135
1136 WRITE(REG_A6XX_SP_UNKNOWN_A81B, 0);
1137
1138 WRITE(REG_A6XX_SP_UNKNOWN_B183, 0);
1139
1140 WRITE(REG_A6XX_GRAS_UNKNOWN_8099, 0);
1141 WRITE(REG_A6XX_GRAS_UNKNOWN_809B, 0);
1142 WRITE(REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1143 WRITE(REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1144 WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
1145 WRITE(REG_A6XX_VPC_UNKNOWN_9211, 0);
1146 WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
1147 WRITE(REG_A6XX_PC_UNKNOWN_9981, 0x3);
1148 WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
1149 WRITE(REG_A6XX_VPC_UNKNOWN_9108, 0x3);
1150 WRITE(REG_A6XX_SP_TP_SAMPLE_CONFIG, 0);
1151 /* NOTE blob seems to (mostly?) use 0xb2 for SP_TP_UNKNOWN_B309
1152 * but this seems to kill texture gather offsets.
1153 */
1154 WRITE(REG_A6XX_SP_TP_UNKNOWN_B309, 0xa2);
1155 WRITE(REG_A6XX_RB_SAMPLE_CONFIG, 0);
1156 WRITE(REG_A6XX_GRAS_SAMPLE_CONFIG, 0);
1157 WRITE(REG_A6XX_RB_UNKNOWN_8878, 0);
1158 WRITE(REG_A6XX_RB_UNKNOWN_8879, 0);
1159 WRITE(REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1160
1161 emit_marker6(ring, 7);
1162
1163 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
1164 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
1165
1166 WRITE(REG_A6XX_VFD_UNKNOWN_A008, 0);
1167
1168 OUT_PKT4(ring, REG_A6XX_PC_MODE_CNTL, 1);
1169 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
1170
1171 /* we don't use this yet.. probably best to disable.. */
1172 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1173 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1174 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1175 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1176 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1177 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1178
1179 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1180 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
1181
1182 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1183 OUT_RING(ring, 0x00000000);
1184
1185 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
1186 OUT_RING(ring, 0x00000000);
1187
1188 fd_log(batch, "END RESTORE");
1189 }
1190
1191 static void
1192 fd6_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
1193 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
1194 unsigned sizedwords)
1195 {
1196 struct fd_bo *src_bo = fd_resource(src)->bo;
1197 struct fd_bo *dst_bo = fd_resource(dst)->bo;
1198 unsigned i;
1199
1200 for (i = 0; i < sizedwords; i++) {
1201 OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
1202 OUT_RING(ring, 0x00000000);
1203 OUT_RELOC(ring, dst_bo, dst_off, 0, 0);
1204 OUT_RELOC(ring, src_bo, src_off, 0, 0);
1205
1206 dst_off += 4;
1207 src_off += 4;
1208 }
1209 }
1210
1211 /* this is *almost* the same as fd6_cache_flush().. which I guess
1212 * could be re-worked to be something a bit more generic w/ param
1213 * indicating what needs to be flushed.. although that would mean
1214 * figuring out which events trigger what state to flush..
1215 */
1216 static void
1217 fd6_framebuffer_barrier(struct fd_context *ctx)
1218 {
1219 struct fd6_context *fd6_ctx = fd6_context(ctx);
1220 struct fd_batch *batch = ctx->batch;
1221 struct fd_ringbuffer *ring = batch->draw;
1222 unsigned seqno;
1223
1224 seqno = fd6_event_write(batch, ring, RB_DONE_TS, true);
1225
1226 OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);
1227 OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
1228 CP_WAIT_REG_MEM_0_POLL_MEMORY);
1229 OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
1230 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(seqno));
1231 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(~0));
1232 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
1233
1234 fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
1235 fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
1236
1237 seqno = fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
1238
1239 fd6_event_write(batch, ring, 0x31, false);
1240
1241 OUT_PKT7(ring, CP_WAIT_MEM_GTE, 4);
1242 OUT_RING(ring, CP_WAIT_MEM_GTE_0_RESERVED(0));
1243 OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
1244 OUT_RING(ring, CP_WAIT_MEM_GTE_3_REF(seqno));
1245 }
1246
1247 void
1248 fd6_emit_init_screen(struct pipe_screen *pscreen)
1249 {
1250 struct fd_screen *screen = fd_screen(pscreen);
1251 screen->emit_ib = fd6_emit_ib;
1252 screen->mem_to_mem = fd6_mem_to_mem;
1253 }
1254
1255 void
1256 fd6_emit_init(struct pipe_context *pctx)
1257 {
1258 struct fd_context *ctx = fd_context(pctx);
1259 ctx->framebuffer_barrier = fd6_framebuffer_barrier;
1260 }