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freedreno/a6xx: combine sample mask into blend state
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_helpers.h"
32 #include "util/format/u_format.h"
33 #include "util/u_viewport.h"
34
35 #include "freedreno_log.h"
36 #include "freedreno_resource.h"
37 #include "freedreno_query_hw.h"
38
39 #include "fd6_emit.h"
40 #include "fd6_blend.h"
41 #include "fd6_context.h"
42 #include "fd6_image.h"
43 #include "fd6_program.h"
44 #include "fd6_rasterizer.h"
45 #include "fd6_texture.h"
46 #include "fd6_format.h"
47 #include "fd6_zsa.h"
48
49 /* regid: base const register
50 * prsc or dwords: buffer containing constant values
51 * sizedwords: size of const value buffer
52 */
53 static void
54 fd6_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
55 uint32_t regid, uint32_t offset, uint32_t sizedwords,
56 const uint32_t *dwords, struct pipe_resource *prsc)
57 {
58 uint32_t i, sz, align_sz;
59 enum a6xx_state_src src;
60
61 debug_assert((regid % 4) == 0);
62
63 if (prsc) {
64 sz = 0;
65 src = SS6_INDIRECT;
66 } else {
67 sz = sizedwords;
68 src = SS6_DIRECT;
69 }
70
71 align_sz = align(sz, 4);
72
73 OUT_PKT7(ring, fd6_stage2opcode(type), 3 + align_sz);
74 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
75 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
76 CP_LOAD_STATE6_0_STATE_SRC(src) |
77 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
78 CP_LOAD_STATE6_0_NUM_UNIT(DIV_ROUND_UP(sizedwords, 4)));
79 if (prsc) {
80 struct fd_bo *bo = fd_resource(prsc)->bo;
81 OUT_RELOC(ring, bo, offset, 0, 0);
82 } else {
83 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
84 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
85 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
86 }
87
88 for (i = 0; i < sz; i++) {
89 OUT_RING(ring, dwords[i]);
90 }
91
92 /* Zero-pad to multiple of 4 dwords */
93 for (i = sz; i < align_sz; i++) {
94 OUT_RING(ring, 0);
95 }
96 }
97
98 static void
99 fd6_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
100 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
101 {
102 uint32_t anum = align(num, 2);
103 uint32_t i;
104
105 debug_assert((regid % 4) == 0);
106
107 OUT_PKT7(ring, fd6_stage2opcode(type), 3 + (2 * anum));
108 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
109 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS)|
110 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
111 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
112 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
113 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
114 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
115
116 for (i = 0; i < num; i++) {
117 if (prscs[i]) {
118 if (write) {
119 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
120 } else {
121 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
122 }
123 } else {
124 OUT_RING(ring, 0xbad00000 | (i << 16));
125 OUT_RING(ring, 0xbad00000 | (i << 16));
126 }
127 }
128
129 for (; i < anum; i++) {
130 OUT_RING(ring, 0xffffffff);
131 OUT_RING(ring, 0xffffffff);
132 }
133 }
134
135 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
136 * the same as a6xx then move this somewhere common ;-)
137 *
138 * Entry layout looks like (total size, 0x60 bytes):
139 */
140
141 struct PACKED bcolor_entry {
142 uint32_t fp32[4];
143 uint16_t ui16[4];
144 int16_t si16[4];
145 uint16_t fp16[4];
146 uint16_t rgb565;
147 uint16_t rgb5a1;
148 uint16_t rgba4;
149 uint8_t __pad0[2];
150 uint8_t ui8[4];
151 int8_t si8[4];
152 uint32_t rgb10a2;
153 uint32_t z24; /* also s8? */
154 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
155 uint8_t __pad1[56];
156 };
157
158 #define FD6_BORDER_COLOR_SIZE sizeof(struct bcolor_entry)
159 #define FD6_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD6_BORDER_COLOR_SIZE)
160
161 static void
162 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
163 {
164 unsigned i, j;
165 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
166
167 for (i = 0; i < tex->num_samplers; i++) {
168 struct bcolor_entry *e = &entries[i];
169 struct pipe_sampler_state *sampler = tex->samplers[i];
170 union pipe_color_union *bc;
171
172 if (!sampler)
173 continue;
174
175 bc = &sampler->border_color;
176
177 /*
178 * XXX HACK ALERT XXX
179 *
180 * The border colors need to be swizzled in a particular
181 * format-dependent order. Even though samplers don't know about
182 * formats, we can assume that with a GL state tracker, there's a
183 * 1:1 correspondence between sampler and texture. Take advantage
184 * of that knowledge.
185 */
186 if ((i >= tex->num_textures) || !tex->textures[i])
187 continue;
188
189 struct pipe_sampler_view *view = tex->textures[i];
190 enum pipe_format format = view->format;
191 const struct util_format_description *desc =
192 util_format_description(format);
193
194 e->rgb565 = 0;
195 e->rgb5a1 = 0;
196 e->rgba4 = 0;
197 e->rgb10a2 = 0;
198 e->z24 = 0;
199
200 unsigned char swiz[4];
201
202 fd6_tex_swiz(format, swiz,
203 view->swizzle_r, view->swizzle_g,
204 view->swizzle_b, view->swizzle_a);
205
206 for (j = 0; j < 4; j++) {
207 int c = swiz[j];
208 int cd = c;
209
210 /*
211 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the
212 * stencil border color value in bc->ui[0] but according
213 * to desc->swizzle and desc->channel, the .x/.w component
214 * is NONE and the stencil value is in the y component.
215 * Meanwhile the hardware wants this in the .w component
216 * for x24s8 and the .x component for x32_s8x24.
217 */
218 if ((format == PIPE_FORMAT_X24S8_UINT) ||
219 (format == PIPE_FORMAT_X32_S8X24_UINT)) {
220 if (j == 0) {
221 c = 1;
222 cd = (format == PIPE_FORMAT_X32_S8X24_UINT) ? 0 : 3;
223 } else {
224 continue;
225 }
226 }
227
228 if (c >= 4)
229 continue;
230
231 if (desc->channel[c].pure_integer) {
232 uint16_t clamped;
233 switch (desc->channel[c].size) {
234 case 2:
235 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
236 clamped = CLAMP(bc->ui[j], 0, 0x3);
237 break;
238 case 8:
239 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
240 clamped = CLAMP(bc->i[j], -128, 127);
241 else
242 clamped = CLAMP(bc->ui[j], 0, 255);
243 break;
244 case 10:
245 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
246 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
247 break;
248 case 16:
249 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
250 clamped = CLAMP(bc->i[j], -32768, 32767);
251 else
252 clamped = CLAMP(bc->ui[j], 0, 65535);
253 break;
254 default:
255 assert(!"Unexpected bit size");
256 case 32:
257 clamped = 0;
258 break;
259 }
260 e->fp32[cd] = bc->ui[j];
261 e->fp16[cd] = clamped;
262 } else {
263 float f = bc->f[j];
264 float f_u = CLAMP(f, 0, 1);
265 float f_s = CLAMP(f, -1, 1);
266
267 e->fp32[c] = fui(f);
268 e->fp16[c] = util_float_to_half(f);
269 e->srgb[c] = util_float_to_half(f_u);
270 e->ui16[c] = f_u * 0xffff;
271 e->si16[c] = f_s * 0x7fff;
272 e->ui8[c] = f_u * 0xff;
273 e->si8[c] = f_s * 0x7f;
274 if (c == 1)
275 e->rgb565 |= (int)(f_u * 0x3f) << 5;
276 else if (c < 3)
277 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
278 if (c == 3)
279 e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
280 else
281 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
282 if (c == 3)
283 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
284 else
285 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
286 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
287 if (c == 0)
288 e->z24 = f_u * 0xffffff;
289 }
290 }
291
292 #ifdef DEBUG
293 memset(&e->__pad0, 0, sizeof(e->__pad0));
294 memset(&e->__pad1, 0, sizeof(e->__pad1));
295 #endif
296 }
297 }
298
299 static void
300 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
301 {
302 struct fd6_context *fd6_ctx = fd6_context(ctx);
303 struct bcolor_entry *entries;
304 unsigned off;
305 void *ptr;
306
307 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
308
309 u_upload_alloc(fd6_ctx->border_color_uploader,
310 0, FD6_BORDER_COLOR_UPLOAD_SIZE,
311 FD6_BORDER_COLOR_UPLOAD_SIZE, &off,
312 &fd6_ctx->border_color_buf,
313 &ptr);
314
315 entries = ptr;
316
317 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
318 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
319 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
320
321 OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
322 OUT_RELOC(ring, fd_resource(fd6_ctx->border_color_buf)->bo, off, 0, 0);
323
324 u_upload_unmap(fd6_ctx->border_color_uploader);
325 }
326
327 static void
328 fd6_emit_fb_tex(struct fd_ringbuffer *state, struct fd_context *ctx)
329 {
330 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
331 struct pipe_surface *psurf = pfb->cbufs[0];
332 struct fd_resource *rsc = fd_resource(psurf->texture);
333
334 uint32_t texconst0 = fd6_tex_const_0(psurf->texture, psurf->u.tex.level,
335 psurf->format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
336 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W);
337
338 /* always TILE6_2 mode in GMEM.. which also means no swap: */
339 texconst0 &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
340 texconst0 |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
341
342 OUT_RING(state, texconst0);
343 OUT_RING(state, A6XX_TEX_CONST_1_WIDTH(pfb->width) |
344 A6XX_TEX_CONST_1_HEIGHT(pfb->height));
345 OUT_RINGP(state, A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
346 A6XX_TEX_CONST_2_FETCHSIZE(TFETCH6_2_BYTE),
347 &ctx->batch->fb_read_patches);
348 OUT_RING(state, A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size));
349
350 OUT_RING(state, A6XX_TEX_CONST_4_BASE_LO(ctx->screen->gmem_base));
351 OUT_RING(state, A6XX_TEX_CONST_5_BASE_HI(ctx->screen->gmem_base >> 32) |
352 A6XX_TEX_CONST_5_DEPTH(1));
353 OUT_RING(state, 0); /* texconst6 */
354 OUT_RING(state, 0); /* texconst7 */
355 OUT_RING(state, 0); /* texconst8 */
356 OUT_RING(state, 0); /* texconst9 */
357 OUT_RING(state, 0); /* texconst10 */
358 OUT_RING(state, 0); /* texconst11 */
359 OUT_RING(state, 0);
360 OUT_RING(state, 0);
361 OUT_RING(state, 0);
362 OUT_RING(state, 0);
363 }
364
365 bool
366 fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
367 enum pipe_shader_type type, struct fd_texture_stateobj *tex,
368 unsigned bcolor_offset,
369 /* can be NULL if no image/SSBO/fb state to merge in: */
370 const struct ir3_shader_variant *v, struct fd_context *ctx)
371 {
372 bool needs_border = false;
373 unsigned opcode, tex_samp_reg, tex_const_reg, tex_count_reg;
374 enum a6xx_state_block sb;
375
376 switch (type) {
377 case PIPE_SHADER_VERTEX:
378 sb = SB6_VS_TEX;
379 opcode = CP_LOAD_STATE6_GEOM;
380 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
381 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
382 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
383 break;
384 case PIPE_SHADER_TESS_CTRL:
385 sb = SB6_HS_TEX;
386 opcode = CP_LOAD_STATE6_GEOM;
387 tex_samp_reg = REG_A6XX_SP_HS_TEX_SAMP_LO;
388 tex_const_reg = REG_A6XX_SP_HS_TEX_CONST_LO;
389 tex_count_reg = REG_A6XX_SP_HS_TEX_COUNT;
390 break;
391 case PIPE_SHADER_TESS_EVAL:
392 sb = SB6_DS_TEX;
393 opcode = CP_LOAD_STATE6_GEOM;
394 tex_samp_reg = REG_A6XX_SP_DS_TEX_SAMP_LO;
395 tex_const_reg = REG_A6XX_SP_DS_TEX_CONST_LO;
396 tex_count_reg = REG_A6XX_SP_DS_TEX_COUNT;
397 break;
398 case PIPE_SHADER_GEOMETRY:
399 sb = SB6_GS_TEX;
400 opcode = CP_LOAD_STATE6_GEOM;
401 tex_samp_reg = REG_A6XX_SP_GS_TEX_SAMP_LO;
402 tex_const_reg = REG_A6XX_SP_GS_TEX_CONST_LO;
403 tex_count_reg = REG_A6XX_SP_GS_TEX_COUNT;
404 break;
405 case PIPE_SHADER_FRAGMENT:
406 sb = SB6_FS_TEX;
407 opcode = CP_LOAD_STATE6_FRAG;
408 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
409 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
410 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
411 break;
412 case PIPE_SHADER_COMPUTE:
413 sb = SB6_CS_TEX;
414 opcode = CP_LOAD_STATE6_FRAG;
415 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
416 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
417 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
418 break;
419 default:
420 unreachable("bad state block");
421 }
422
423 if (tex->num_samplers > 0) {
424 struct fd_ringbuffer *state =
425 fd_ringbuffer_new_object(pipe, tex->num_samplers * 4 * 4);
426 for (unsigned i = 0; i < tex->num_samplers; i++) {
427 static const struct fd6_sampler_stateobj dummy_sampler = {};
428 const struct fd6_sampler_stateobj *sampler = tex->samplers[i] ?
429 fd6_sampler_stateobj(tex->samplers[i]) : &dummy_sampler;
430 OUT_RING(state, sampler->texsamp0);
431 OUT_RING(state, sampler->texsamp1);
432 OUT_RING(state, sampler->texsamp2 |
433 A6XX_TEX_SAMP_2_BCOLOR_OFFSET((i + bcolor_offset) * sizeof(struct bcolor_entry)));
434 OUT_RING(state, sampler->texsamp3);
435 needs_border |= sampler->needs_border;
436 }
437
438 /* output sampler state: */
439 OUT_PKT7(ring, opcode, 3);
440 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
441 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
442 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
443 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
444 CP_LOAD_STATE6_0_NUM_UNIT(tex->num_samplers));
445 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
446
447 OUT_PKT4(ring, tex_samp_reg, 2);
448 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
449
450 fd_ringbuffer_del(state);
451 }
452
453 unsigned num_merged_textures = tex->num_textures;
454 unsigned num_textures = tex->num_textures;
455 if (v) {
456 num_merged_textures += v->image_mapping.num_tex;
457
458 if (v->fb_read)
459 num_merged_textures++;
460
461 /* There could be more bound textures than what the shader uses.
462 * Which isn't known at shader compile time. So in the case we
463 * are merging tex state, only emit the textures that the shader
464 * uses (since the image/SSBO related tex state comes immediately
465 * after)
466 */
467 num_textures = v->image_mapping.tex_base;
468 }
469
470 if (num_merged_textures > 0) {
471 struct fd_ringbuffer *state =
472 fd_ringbuffer_new_object(pipe, num_merged_textures * 16 * 4);
473 for (unsigned i = 0; i < num_textures; i++) {
474 static const struct fd6_pipe_sampler_view dummy_view = {};
475 const struct fd6_pipe_sampler_view *view = tex->textures[i] ?
476 fd6_pipe_sampler_view(tex->textures[i]) : &dummy_view;
477 struct fd_resource *rsc = NULL;
478
479 if (view->base.texture)
480 rsc = fd_resource(view->base.texture);
481
482 OUT_RING(state, view->texconst0);
483 OUT_RING(state, view->texconst1);
484 OUT_RING(state, view->texconst2);
485 OUT_RING(state, view->texconst3);
486
487 if (rsc) {
488 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
489 rsc = rsc->stencil;
490 OUT_RELOC(state, rsc->bo, view->offset,
491 (uint64_t)view->texconst5 << 32, 0);
492 } else {
493 OUT_RING(state, 0x00000000);
494 OUT_RING(state, view->texconst5);
495 }
496
497 OUT_RING(state, view->texconst6);
498
499 if (rsc && view->ubwc_enabled) {
500 OUT_RELOC(state, rsc->bo, view->ubwc_offset, 0, 0);
501 } else {
502 OUT_RING(state, 0);
503 OUT_RING(state, 0);
504 }
505
506 OUT_RING(state, view->texconst9);
507 OUT_RING(state, view->texconst10);
508 OUT_RING(state, view->texconst11);
509 OUT_RING(state, 0);
510 OUT_RING(state, 0);
511 OUT_RING(state, 0);
512 OUT_RING(state, 0);
513 }
514
515 if (v) {
516 const struct ir3_ibo_mapping *mapping = &v->image_mapping;
517 struct fd_shaderbuf_stateobj *buf = &ctx->shaderbuf[type];
518 struct fd_shaderimg_stateobj *img = &ctx->shaderimg[type];
519
520 for (unsigned i = 0; i < mapping->num_tex; i++) {
521 unsigned idx = mapping->tex_to_image[i];
522 if (idx & IBO_SSBO) {
523 fd6_emit_ssbo_tex(state, &buf->sb[idx & ~IBO_SSBO]);
524 } else {
525 fd6_emit_image_tex(state, &img->si[idx]);
526 }
527 }
528
529 if (v->fb_read) {
530 fd6_emit_fb_tex(state, ctx);
531 }
532 }
533
534 /* emit texture state: */
535 OUT_PKT7(ring, opcode, 3);
536 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
537 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
538 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
539 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
540 CP_LOAD_STATE6_0_NUM_UNIT(num_merged_textures));
541 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
542
543 OUT_PKT4(ring, tex_const_reg, 2);
544 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
545
546 fd_ringbuffer_del(state);
547 }
548
549 OUT_PKT4(ring, tex_count_reg, 1);
550 OUT_RING(ring, num_merged_textures);
551
552 return needs_border;
553 }
554
555 /* Emits combined texture state, which also includes any Image/SSBO
556 * related texture state merged in (because we must have all texture
557 * state for a given stage in a single buffer). In the fast-path, if
558 * we don't need to merge in any image/ssbo related texture state, we
559 * just use cached texture stateobj. Otherwise we generate a single-
560 * use stateobj.
561 *
562 * TODO Is there some sane way we can still use cached texture stateobj
563 * with image/ssbo in use?
564 *
565 * returns whether border_color is required:
566 */
567 static bool
568 fd6_emit_combined_textures(struct fd_ringbuffer *ring, struct fd6_emit *emit,
569 enum pipe_shader_type type, const struct ir3_shader_variant *v)
570 {
571 struct fd_context *ctx = emit->ctx;
572 bool needs_border = false;
573
574 static const struct {
575 enum fd6_state_id state_id;
576 unsigned enable_mask;
577 } s[PIPE_SHADER_TYPES] = {
578 [PIPE_SHADER_VERTEX] = { FD6_GROUP_VS_TEX, ENABLE_ALL },
579 [PIPE_SHADER_TESS_CTRL] = { FD6_GROUP_HS_TEX, ENABLE_ALL },
580 [PIPE_SHADER_TESS_EVAL] = { FD6_GROUP_DS_TEX, ENABLE_ALL },
581 [PIPE_SHADER_GEOMETRY] = { FD6_GROUP_GS_TEX, ENABLE_ALL },
582 [PIPE_SHADER_FRAGMENT] = { FD6_GROUP_FS_TEX, ENABLE_DRAW },
583 };
584
585 debug_assert(s[type].state_id);
586
587 if (!v->image_mapping.num_tex && !v->fb_read) {
588 /* in the fast-path, when we don't have to mix in any image/SSBO
589 * related texture state, we can just lookup the stateobj and
590 * re-emit that:
591 *
592 * Also, framebuffer-read is a slow-path because an extra
593 * texture needs to be inserted.
594 *
595 * TODO we can probably simmplify things if we also treated
596 * border_color as a slow-path.. this way the tex state key
597 * wouldn't depend on bcolor_offset.. but fb_read might rather
598 * be *somehow* a fast-path if we eventually used it for PLS.
599 * I suppose there would be no harm in just *always* inserting
600 * an fb_read texture?
601 */
602 if ((ctx->dirty_shader[type] & FD_DIRTY_SHADER_TEX) &&
603 ctx->tex[type].num_textures > 0) {
604 struct fd6_texture_state *tex = fd6_texture_state(ctx,
605 type, &ctx->tex[type]);
606
607 needs_border |= tex->needs_border;
608
609 fd6_emit_add_group(emit, tex->stateobj, s[type].state_id,
610 s[type].enable_mask);
611 }
612 } else {
613 /* In the slow-path, create a one-shot texture state object
614 * if either TEX|PROG|SSBO|IMAGE state is dirty:
615 */
616 if ((ctx->dirty_shader[type] &
617 (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
618 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) ||
619 v->fb_read) {
620 struct fd_texture_stateobj *tex = &ctx->tex[type];
621 struct fd_ringbuffer *stateobj =
622 fd_submit_new_ringbuffer(ctx->batch->submit,
623 0x1000, FD_RINGBUFFER_STREAMING);
624 unsigned bcolor_offset =
625 fd6_border_color_offset(ctx, type, tex);
626
627 needs_border |= fd6_emit_textures(ctx->pipe, stateobj, type, tex,
628 bcolor_offset, v, ctx);
629
630 fd6_emit_take_group(emit, stateobj, s[type].state_id,
631 s[type].enable_mask);
632 }
633 }
634
635 return needs_border;
636 }
637
638 static struct fd_ringbuffer *
639 build_vbo_state(struct fd6_emit *emit, const struct ir3_shader_variant *vp)
640 {
641 const struct fd_vertex_state *vtx = emit->vtx;
642 int32_t i, j;
643
644 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
645 4 * (10 * vp->inputs_count + 2), FD_RINGBUFFER_STREAMING);
646
647 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
648 if (vp->inputs[i].sysval)
649 continue;
650 if (vp->inputs[i].compmask) {
651 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
652 const struct pipe_vertex_buffer *vb =
653 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
654 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
655 enum pipe_format pfmt = elem->src_format;
656 enum a6xx_format fmt = fd6_pipe2vtx(pfmt);
657 bool isint = util_format_is_pure_integer(pfmt);
658 uint32_t off = vb->buffer_offset + elem->src_offset;
659 uint32_t size = fd_bo_size(rsc->bo) - off;
660 debug_assert(fmt != ~0);
661
662 #ifdef DEBUG
663 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
664 */
665 if (off > fd_bo_size(rsc->bo))
666 continue;
667 #endif
668
669 OUT_PKT4(ring, REG_A6XX_VFD_FETCH(j), 4);
670 OUT_RELOC(ring, rsc->bo, off, 0, 0);
671 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
672 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
673
674 OUT_PKT4(ring, REG_A6XX_VFD_DECODE(j), 2);
675 OUT_RING(ring, A6XX_VFD_DECODE_INSTR_IDX(j) |
676 A6XX_VFD_DECODE_INSTR_FORMAT(fmt) |
677 COND(elem->instance_divisor, A6XX_VFD_DECODE_INSTR_INSTANCED) |
678 A6XX_VFD_DECODE_INSTR_SWAP(fd6_pipe2swap(pfmt)) |
679 A6XX_VFD_DECODE_INSTR_UNK30 |
680 COND(!isint, A6XX_VFD_DECODE_INSTR_FLOAT));
681 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
682
683 OUT_PKT4(ring, REG_A6XX_VFD_DEST_CNTL(j), 1);
684 OUT_RING(ring, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
685 A6XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
686
687 j++;
688 }
689 }
690
691 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_0, 1);
692 OUT_RING(ring, A6XX_VFD_CONTROL_0_FETCH_CNT(j) |
693 A6XX_VFD_CONTROL_0_DECODE_CNT(j));
694
695 return ring;
696 }
697
698 static struct fd_ringbuffer *
699 build_lrz(struct fd6_emit *emit, bool binning_pass)
700 {
701 struct fd_context *ctx = emit->ctx;
702 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
703 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
704 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
705 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
706 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
707 uint32_t rb_lrz_cntl = zsa->rb_lrz_cntl;
708
709 if (zsa->invalidate_lrz) {
710 rsc->lrz_valid = false;
711 gras_lrz_cntl = 0;
712 rb_lrz_cntl = 0;
713 } else if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid) {
714 gras_lrz_cntl = 0;
715 rb_lrz_cntl = 0;
716 } else if (binning_pass && blend->lrz_write && zsa->lrz_write) {
717 gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_LRZ_WRITE;
718 }
719
720 struct fd6_context *fd6_ctx = fd6_context(ctx);
721 if ((fd6_ctx->last.lrz[binning_pass].gras_lrz_cntl == gras_lrz_cntl) &&
722 (fd6_ctx->last.lrz[binning_pass].rb_lrz_cntl == rb_lrz_cntl) &&
723 !ctx->last.dirty)
724 return NULL;
725
726 fd6_ctx->last.lrz[binning_pass].gras_lrz_cntl = gras_lrz_cntl;
727 fd6_ctx->last.lrz[binning_pass].rb_lrz_cntl = rb_lrz_cntl;
728
729 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(ctx->batch->submit,
730 16, FD_RINGBUFFER_STREAMING);
731
732 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
733 OUT_RING(ring, gras_lrz_cntl);
734
735 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
736 OUT_RING(ring, rb_lrz_cntl);
737
738 return ring;
739 }
740
741 static void
742 fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3_stream_output_info *info)
743 {
744 struct fd_context *ctx = emit->ctx;
745 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
746 struct fd_streamout_stateobj *so = &ctx->streamout;
747
748 emit->streamout_mask = 0;
749
750 for (unsigned i = 0; i < so->num_targets; i++) {
751 struct pipe_stream_output_target *target = so->targets[i];
752
753 if (!target)
754 continue;
755
756 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(i), 3);
757 /* VPC_SO[i].BUFFER_BASE_LO: */
758 OUT_RELOCW(ring, fd_resource(target->buffer)->bo, target->buffer_offset, 0, 0);
759 OUT_RING(ring, target->buffer_size - target->buffer_offset);
760
761 if (so->reset & (1 << i)) {
762 unsigned offset = (so->offsets[i] * info->stride[i] * 4);
763 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(i), 1);
764 OUT_RING(ring, offset);
765 } else {
766 OUT_PKT7(ring, CP_MEM_TO_REG, 3);
767 OUT_RING(ring, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i)) |
768 CP_MEM_TO_REG_0_SHIFT_BY_2 | CP_MEM_TO_REG_0_UNK31 |
769 CP_MEM_TO_REG_0_CNT(0));
770 OUT_RELOC(ring, control_ptr(fd6_context(ctx), flush_base[i].offset));
771 }
772
773 OUT_PKT4(ring, REG_A6XX_VPC_SO_FLUSH_BASE_LO(i), 2);
774 OUT_RELOCW(ring, control_ptr(fd6_context(ctx), flush_base[i]));
775
776 so->reset &= ~(1 << i);
777
778 emit->streamout_mask |= (1 << i);
779 }
780
781 if (emit->streamout_mask) {
782 const struct fd6_streamout_state *tf = &prog->tf;
783
784 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * tf->prog_count));
785 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
786 OUT_RING(ring, tf->vpc_so_buf_cntl);
787 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0));
788 OUT_RING(ring, tf->ncomp[0]);
789 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1));
790 OUT_RING(ring, tf->ncomp[1]);
791 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(2));
792 OUT_RING(ring, tf->ncomp[2]);
793 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3));
794 OUT_RING(ring, tf->ncomp[3]);
795 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
796 OUT_RING(ring, A6XX_VPC_SO_CNTL_ENABLE);
797 for (unsigned i = 0; i < tf->prog_count; i++) {
798 OUT_RING(ring, REG_A6XX_VPC_SO_PROG);
799 OUT_RING(ring, tf->prog[i]);
800 }
801 } else {
802 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 4);
803 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
804 OUT_RING(ring, 0);
805 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
806 OUT_RING(ring, 0);
807 }
808 }
809
810 static void
811 emit_tess_bos(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3_shader_variant *s)
812 {
813 struct fd_context *ctx = emit->ctx;
814 const unsigned regid = s->shader->const_state.offsets.primitive_param * 4 + 4;
815 uint32_t dwords = 16;
816
817 OUT_PKT7(ring, fd6_stage2opcode(s->type), 3);
818 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid / 4) |
819 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS)|
820 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
821 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(s->type)) |
822 CP_LOAD_STATE6_0_NUM_UNIT(dwords / 4));
823 OUT_RB(ring, ctx->batch->tess_addrs_constobj);
824 }
825
826 static void
827 emit_stage_tess_consts(struct fd_ringbuffer *ring, struct ir3_shader_variant *v,
828 uint32_t *params, int num_params)
829 {
830 const unsigned regid = v->shader->const_state.offsets.primitive_param;
831 int size = MIN2(1 + regid, v->constlen) - regid;
832 if (size > 0)
833 fd6_emit_const(ring, v->type, regid * 4, 0, num_params, params, NULL);
834 }
835
836 static void
837 fd6_emit_tess_const(struct fd6_emit *emit)
838 {
839 struct fd_context *ctx = emit->ctx;
840
841 struct fd_ringbuffer *constobj = fd_submit_new_ringbuffer(
842 ctx->batch->submit, 0x1000, FD_RINGBUFFER_STREAMING);
843
844 /* VS sizes are in bytes since that's what STLW/LDLW use, while the HS
845 * size is dwords, since that's what LDG/STG use.
846 */
847 unsigned num_vertices =
848 emit->hs ?
849 emit->info->vertices_per_patch :
850 emit->gs->shader->nir->info.gs.vertices_in;
851
852 uint32_t vs_params[4] = {
853 emit->vs->shader->output_size * num_vertices * 4, /* vs primitive stride */
854 emit->vs->shader->output_size * 4, /* vs vertex stride */
855 0,
856 0
857 };
858
859 emit_stage_tess_consts(constobj, emit->vs, vs_params, ARRAY_SIZE(vs_params));
860
861 if (emit->hs) {
862 uint32_t hs_params[4] = {
863 emit->vs->shader->output_size * num_vertices * 4, /* vs primitive stride */
864 emit->vs->shader->output_size * 4, /* vs vertex stride */
865 emit->hs->shader->output_size,
866 emit->info->vertices_per_patch
867 };
868
869 emit_stage_tess_consts(constobj, emit->hs, hs_params, ARRAY_SIZE(hs_params));
870 emit_tess_bos(constobj, emit, emit->hs);
871
872 if (emit->gs)
873 num_vertices = emit->gs->shader->nir->info.gs.vertices_in;
874
875 uint32_t ds_params[4] = {
876 emit->ds->shader->output_size * num_vertices * 4, /* ds primitive stride */
877 emit->ds->shader->output_size * 4, /* ds vertex stride */
878 emit->hs->shader->output_size, /* hs vertex stride (dwords) */
879 emit->hs->shader->nir->info.tess.tcs_vertices_out
880 };
881
882 emit_stage_tess_consts(constobj, emit->ds, ds_params, ARRAY_SIZE(ds_params));
883 emit_tess_bos(constobj, emit, emit->ds);
884 }
885
886 if (emit->gs) {
887 struct ir3_shader_variant *prev;
888 if (emit->ds)
889 prev = emit->ds;
890 else
891 prev = emit->vs;
892
893 uint32_t gs_params[4] = {
894 prev->shader->output_size * num_vertices * 4, /* ds primitive stride */
895 prev->shader->output_size * 4, /* ds vertex stride */
896 0,
897 0,
898 };
899
900 num_vertices = emit->gs->shader->nir->info.gs.vertices_in;
901 emit_stage_tess_consts(constobj, emit->gs, gs_params, ARRAY_SIZE(gs_params));
902 }
903
904 fd6_emit_take_group(emit, constobj, FD6_GROUP_PRIMITIVE_PARAMS, ENABLE_ALL);
905 }
906
907 static void
908 fd6_emit_consts(struct fd6_emit *emit)
909 {
910 static const enum pipe_shader_type types[] = {
911 PIPE_SHADER_VERTEX, PIPE_SHADER_TESS_CTRL, PIPE_SHADER_TESS_EVAL,
912 PIPE_SHADER_GEOMETRY, PIPE_SHADER_FRAGMENT,
913 };
914 const struct ir3_shader_variant *variants[] = {
915 emit->vs, emit->hs, emit->ds, emit->gs, emit->fs,
916 };
917 struct fd_context *ctx = emit->ctx;
918 unsigned sz = 0;
919
920 for (unsigned i = 0; i < ARRAY_SIZE(types); i++) {
921 if (!variants[i])
922 continue;
923 sz += variants[i]->shader->ubo_state.cmdstream_size;
924 }
925
926 struct fd_ringbuffer *constobj = fd_submit_new_ringbuffer(
927 ctx->batch->submit, sz, FD_RINGBUFFER_STREAMING);
928
929 for (unsigned i = 0; i < ARRAY_SIZE(types); i++) {
930 if (!variants[i])
931 continue;
932 ir3_emit_user_consts(ctx->screen, variants[i], constobj, &ctx->constbuf[types[i]]);
933 ir3_emit_ubos(ctx->screen, variants[i], constobj, &ctx->constbuf[types[i]]);
934 }
935
936 fd6_emit_take_group(emit, constobj, FD6_GROUP_CONST, ENABLE_ALL);
937 }
938
939 void
940 fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
941 {
942 struct fd_context *ctx = emit->ctx;
943 struct fd6_context *fd6_ctx = fd6_context(ctx);
944 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
945 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
946 const struct ir3_shader_variant *vs = emit->vs;
947 const struct ir3_shader_variant *hs = emit->hs;
948 const struct ir3_shader_variant *ds = emit->ds;
949 const struct ir3_shader_variant *gs = emit->gs;
950 const struct ir3_shader_variant *fs = emit->fs;
951 const enum fd_dirty_3d_state dirty = emit->dirty;
952 bool needs_border = false;
953
954 emit_marker6(ring, 5);
955
956 /* NOTE: we track fb_read differently than _BLEND_ENABLED since
957 * we might at some point decide to do sysmem in some cases when
958 * blend is enabled:
959 */
960 if (fs->fb_read)
961 ctx->batch->gmem_reason |= FD_GMEM_FB_READ;
962
963 if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE)) {
964 struct fd_ringbuffer *state;
965
966 state = build_vbo_state(emit, emit->vs);
967 fd6_emit_take_group(emit, state, FD6_GROUP_VBO, ENABLE_ALL);
968 }
969
970 if (dirty & FD_DIRTY_ZSA) {
971 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
972
973 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
974 fd6_emit_add_group(emit, zsa->stateobj_no_alpha, FD6_GROUP_ZSA, ENABLE_ALL);
975 else
976 fd6_emit_add_group(emit, zsa->stateobj, FD6_GROUP_ZSA, ENABLE_ALL);
977 }
978
979 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG)) && pfb->zsbuf) {
980 struct fd_ringbuffer *state;
981
982 state = build_lrz(emit, false);
983 if (state) {
984 fd6_emit_take_group(emit, state, FD6_GROUP_LRZ, ENABLE_DRAW);
985 }
986
987 state = build_lrz(emit, true);
988 if (state) {
989 fd6_emit_take_group(emit, state,
990 FD6_GROUP_LRZ_BINNING, CP_SET_DRAW_STATE__0_BINNING);
991 }
992 }
993
994 if (dirty & FD_DIRTY_STENCIL_REF) {
995 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
996
997 OUT_PKT4(ring, REG_A6XX_RB_STENCILREF, 1);
998 OUT_RING(ring, A6XX_RB_STENCILREF_REF(sr->ref_value[0]) |
999 A6XX_RB_STENCILREF_BFREF(sr->ref_value[1]));
1000 }
1001
1002 /* NOTE: scissor enabled bit is part of rasterizer state, but
1003 * fd_rasterizer_state_bind() will mark scissor dirty if needed:
1004 */
1005 if (dirty & FD_DIRTY_SCISSOR) {
1006 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
1007 emit->ctx->batch->submit, 3*4, FD_RINGBUFFER_STREAMING);
1008 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
1009
1010 OUT_PKT4(ring, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1011 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
1012 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
1013 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
1014 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
1015
1016 fd6_emit_take_group(emit, ring, FD6_GROUP_SCISSOR, ENABLE_ALL);
1017
1018 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
1019 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
1020 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
1021 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
1022 }
1023
1024 if (dirty & FD_DIRTY_VIEWPORT) {
1025 struct pipe_scissor_state *scissor = &ctx->viewport_scissor;
1026
1027 OUT_PKT4(ring, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1028 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
1029 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
1030 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
1031 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
1032 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
1033 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
1034
1035 OUT_PKT4(ring, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1036 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
1037 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
1038 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
1039 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
1040
1041 unsigned guardband_x = fd_calc_guardband(scissor->maxx - scissor->minx);
1042 unsigned guardband_y = fd_calc_guardband(scissor->maxy - scissor->miny);
1043
1044 OUT_PKT4(ring, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1045 OUT_RING(ring, A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_x) |
1046 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_y));
1047 }
1048
1049 if (dirty & FD_DIRTY_PROG) {
1050 fd6_emit_add_group(emit, prog->config_stateobj, FD6_GROUP_PROG_CONFIG, ENABLE_ALL);
1051 fd6_emit_add_group(emit, prog->stateobj, FD6_GROUP_PROG, ENABLE_DRAW);
1052 fd6_emit_add_group(emit, prog->binning_stateobj,
1053 FD6_GROUP_PROG_BINNING, CP_SET_DRAW_STATE__0_BINNING);
1054
1055 /* emit remaining streaming program state, ie. what depends on
1056 * other emit state, so cannot be pre-baked.
1057 */
1058 struct fd_ringbuffer *streaming = fd6_program_interp_state(emit);
1059
1060 fd6_emit_take_group(emit, streaming, FD6_GROUP_PROG_INTERP, ENABLE_DRAW);
1061 }
1062
1063 if (dirty & FD_DIRTY_RASTERIZER) {
1064 struct fd_ringbuffer *stateobj =
1065 fd6_rasterizer_state(ctx, emit->primitive_restart);
1066 fd6_emit_add_group(emit, stateobj,
1067 FD6_GROUP_RASTERIZER, ENABLE_ALL);
1068 }
1069
1070 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER_DISCARD | FD_DIRTY_PROG)) {
1071 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
1072 emit->ctx->batch->submit, 5 * 4, FD_RINGBUFFER_STREAMING);
1073
1074 unsigned nr = pfb->nr_cbufs;
1075
1076 if (ctx->rasterizer->rasterizer_discard)
1077 nr = 0;
1078
1079 OUT_PKT4(ring, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1080 OUT_RING(ring, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1081 COND(fs->writes_smask && pfb->samples > 1,
1082 A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
1083 OUT_RING(ring, A6XX_RB_FS_OUTPUT_CNTL1_MRT(nr));
1084
1085 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL1, 1);
1086 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL1_MRT(nr));
1087
1088 fd6_emit_take_group(emit, ring, FD6_GROUP_PROG_FB_RAST, ENABLE_DRAW);
1089 }
1090
1091 if (dirty & (FD_DIRTY_CONST | FD_DIRTY_PROG)) {
1092 fd6_emit_consts(emit);
1093 }
1094
1095 if (emit->key.key.has_gs || emit->key.key.tessellation)
1096 fd6_emit_tess_const(emit);
1097
1098 /* if driver-params are needed, emit each time: */
1099 if (ir3_needs_vs_driver_params(vs)) {
1100 struct fd_ringbuffer *dpconstobj = fd_submit_new_ringbuffer(
1101 ctx->batch->submit, IR3_DP_VS_COUNT * 4, FD_RINGBUFFER_STREAMING);
1102 ir3_emit_vs_driver_params(vs, dpconstobj, ctx, emit->info);
1103 fd6_emit_take_group(emit, dpconstobj, FD6_GROUP_VS_DRIVER_PARAMS, ENABLE_ALL);
1104 fd6_ctx->has_dp_state = true;
1105 } else if (fd6_ctx->has_dp_state) {
1106 fd6_emit_take_group(emit, NULL, FD6_GROUP_VS_DRIVER_PARAMS, ENABLE_ALL);
1107 fd6_ctx->has_dp_state = false;
1108 }
1109
1110 struct ir3_stream_output_info *info = &fd6_last_shader(prog)->shader->stream_output;
1111 if (info->num_outputs)
1112 fd6_emit_streamout(ring, emit, info);
1113
1114 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK)) {
1115 struct fd6_blend_variant *blend = fd6_blend_variant(ctx->blend,
1116 pfb->samples, ctx->sample_mask);
1117 fd6_emit_add_group(emit, blend->stateobj, FD6_GROUP_BLEND, ENABLE_DRAW);
1118 }
1119
1120 if (dirty & FD_DIRTY_BLEND_COLOR) {
1121 struct pipe_blend_color *bcolor = &ctx->blend_color;
1122 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
1123 emit->ctx->batch->submit, 5*4, FD_RINGBUFFER_STREAMING);
1124
1125 OUT_PKT4(ring, REG_A6XX_RB_BLEND_RED_F32, 4);
1126 OUT_RING(ring, A6XX_RB_BLEND_RED_F32(bcolor->color[0]));
1127 OUT_RING(ring, A6XX_RB_BLEND_GREEN_F32(bcolor->color[1]));
1128 OUT_RING(ring, A6XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
1129 OUT_RING(ring, A6XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
1130
1131 fd6_emit_take_group(emit, ring, FD6_GROUP_BLEND_COLOR, ENABLE_DRAW);
1132 }
1133
1134 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_VERTEX, vs);
1135 if (hs) {
1136 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_TESS_CTRL, hs);
1137 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_TESS_EVAL, ds);
1138 }
1139 if (gs) {
1140 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_GEOMETRY, gs);
1141 }
1142 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_FRAGMENT, fs);
1143
1144 if (needs_border)
1145 emit_border_color(ctx, ring);
1146
1147 if (hs) {
1148 debug_assert(ir3_shader_nibo(hs) == 0);
1149 debug_assert(ir3_shader_nibo(ds) == 0);
1150 }
1151 if (gs) {
1152 debug_assert(ir3_shader_nibo(gs) == 0);
1153 }
1154
1155 #define DIRTY_IBO (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE | \
1156 FD_DIRTY_SHADER_PROG)
1157 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & DIRTY_IBO) {
1158 struct fd_ringbuffer *state =
1159 fd6_build_ibo_state(ctx, fs, PIPE_SHADER_FRAGMENT);
1160 struct fd_ringbuffer *obj = fd_submit_new_ringbuffer(
1161 ctx->batch->submit, 0x100, FD_RINGBUFFER_STREAMING);
1162
1163 OUT_PKT7(obj, CP_LOAD_STATE6, 3);
1164 OUT_RING(obj, CP_LOAD_STATE6_0_DST_OFF(0) |
1165 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1166 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1167 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_IBO) |
1168 CP_LOAD_STATE6_0_NUM_UNIT(ir3_shader_nibo(fs)));
1169 OUT_RB(obj, state);
1170
1171 OUT_PKT4(obj, REG_A6XX_SP_IBO_LO, 2);
1172 OUT_RB(obj, state);
1173
1174 /* TODO if we used CP_SET_DRAW_STATE for compute shaders, we could
1175 * de-duplicate this from program->config_stateobj
1176 */
1177 OUT_PKT4(obj, REG_A6XX_SP_IBO_COUNT, 1);
1178 OUT_RING(obj, ir3_shader_nibo(fs));
1179
1180 ir3_emit_ssbo_sizes(ctx->screen, fs, obj,
1181 &ctx->shaderbuf[PIPE_SHADER_FRAGMENT]);
1182 ir3_emit_image_dims(ctx->screen, fs, obj,
1183 &ctx->shaderimg[PIPE_SHADER_FRAGMENT]);
1184
1185 fd6_emit_take_group(emit, obj, FD6_GROUP_IBO, ENABLE_DRAW);
1186 fd_ringbuffer_del(state);
1187 }
1188
1189 if (emit->num_groups > 0) {
1190 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3 * emit->num_groups);
1191 for (unsigned i = 0; i < emit->num_groups; i++) {
1192 struct fd6_state_group *g = &emit->groups[i];
1193 unsigned n = g->stateobj ?
1194 fd_ringbuffer_size(g->stateobj) / 4 : 0;
1195
1196 debug_assert((g->enable_mask & ~ENABLE_ALL) == 0);
1197
1198 if (n == 0) {
1199 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1200 CP_SET_DRAW_STATE__0_DISABLE |
1201 g->enable_mask |
1202 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
1203 OUT_RING(ring, 0x00000000);
1204 OUT_RING(ring, 0x00000000);
1205 } else {
1206 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(n) |
1207 g->enable_mask |
1208 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
1209 OUT_RB(ring, g->stateobj);
1210 }
1211
1212 if (g->stateobj)
1213 fd_ringbuffer_del(g->stateobj);
1214 }
1215 emit->num_groups = 0;
1216 }
1217 }
1218
1219 void
1220 fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
1221 struct ir3_shader_variant *cp)
1222 {
1223 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
1224
1225 if (dirty & (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
1226 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) {
1227 struct fd_texture_stateobj *tex = &ctx->tex[PIPE_SHADER_COMPUTE];
1228 unsigned bcolor_offset = fd6_border_color_offset(ctx, PIPE_SHADER_COMPUTE, tex);
1229
1230 bool needs_border = fd6_emit_textures(ctx->pipe, ring, PIPE_SHADER_COMPUTE, tex,
1231 bcolor_offset, cp, ctx);
1232
1233 if (needs_border)
1234 emit_border_color(ctx, ring);
1235
1236 OUT_PKT4(ring, REG_A6XX_SP_VS_TEX_COUNT, 1);
1237 OUT_RING(ring, 0);
1238
1239 OUT_PKT4(ring, REG_A6XX_SP_HS_TEX_COUNT, 1);
1240 OUT_RING(ring, 0);
1241
1242 OUT_PKT4(ring, REG_A6XX_SP_DS_TEX_COUNT, 1);
1243 OUT_RING(ring, 0);
1244
1245 OUT_PKT4(ring, REG_A6XX_SP_GS_TEX_COUNT, 1);
1246 OUT_RING(ring, 0);
1247
1248 OUT_PKT4(ring, REG_A6XX_SP_FS_TEX_COUNT, 1);
1249 OUT_RING(ring, 0);
1250 }
1251
1252 if (dirty & (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)) {
1253 struct fd_ringbuffer *state =
1254 fd6_build_ibo_state(ctx, cp, PIPE_SHADER_COMPUTE);
1255
1256 OUT_PKT7(ring, CP_LOAD_STATE6_FRAG, 3);
1257 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
1258 CP_LOAD_STATE6_0_STATE_TYPE(ST6_IBO) |
1259 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1260 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_CS_SHADER) |
1261 CP_LOAD_STATE6_0_NUM_UNIT(ir3_shader_nibo(cp)));
1262 OUT_RB(ring, state);
1263
1264 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_LO, 2);
1265 OUT_RB(ring, state);
1266
1267 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_COUNT, 1);
1268 OUT_RING(ring, ir3_shader_nibo(cp));
1269
1270 fd_ringbuffer_del(state);
1271 }
1272 }
1273
1274
1275 /* emit setup at begin of new cmdstream buffer (don't rely on previous
1276 * state, there could have been a context switch between ioctls):
1277 */
1278 void
1279 fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
1280 {
1281 //struct fd_context *ctx = batch->ctx;
1282
1283 fd_log(batch, "START RESTORE");
1284
1285 fd6_cache_inv(batch, ring);
1286
1287 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1288 OUT_RING(ring, 0xfffff);
1289
1290 OUT_WFI5(ring);
1291
1292 WRITE(REG_A6XX_RB_UNKNOWN_8E04, 0x0);
1293 WRITE(REG_A6XX_SP_UNKNOWN_AE04, 0x8);
1294 WRITE(REG_A6XX_SP_UNKNOWN_AE00, 0);
1295 WRITE(REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
1296 WRITE(REG_A6XX_SP_UNKNOWN_B605, 0x44);
1297 WRITE(REG_A6XX_SP_UNKNOWN_B600, 0x100000);
1298 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
1299 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
1300
1301 WRITE(REG_A6XX_VPC_UNKNOWN_9600, 0);
1302 WRITE(REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
1303 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE04, 0x80000);
1304 WRITE(REG_A6XX_SP_UNKNOWN_AE03, 0x1430);
1305 WRITE(REG_A6XX_SP_IBO_COUNT, 0);
1306 WRITE(REG_A6XX_SP_UNKNOWN_B182, 0);
1307 WRITE(REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
1308 WRITE(REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
1309 WRITE(REG_A6XX_UCHE_CLIENT_PF, 4);
1310 WRITE(REG_A6XX_RB_UNKNOWN_8E01, 0x1);
1311 WRITE(REG_A6XX_SP_UNKNOWN_AB00, 0x5);
1312 WRITE(REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
1313 WRITE(REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
1314 WRITE(REG_A6XX_PC_MODE_CNTL, 0x1f);
1315
1316 OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
1317 OUT_RING(ring, 0);
1318
1319 WRITE(REG_A6XX_GRAS_UNKNOWN_8101, 0);
1320 WRITE(REG_A6XX_GRAS_SAMPLE_CNTL, 0);
1321 WRITE(REG_A6XX_GRAS_UNKNOWN_8110, 0x2);
1322
1323 WRITE(REG_A6XX_RB_UNKNOWN_8818, 0);
1324 WRITE(REG_A6XX_RB_UNKNOWN_8819, 0);
1325 WRITE(REG_A6XX_RB_UNKNOWN_881A, 0);
1326 WRITE(REG_A6XX_RB_UNKNOWN_881B, 0);
1327 WRITE(REG_A6XX_RB_UNKNOWN_881C, 0);
1328 WRITE(REG_A6XX_RB_UNKNOWN_881D, 0);
1329 WRITE(REG_A6XX_RB_UNKNOWN_881E, 0);
1330 WRITE(REG_A6XX_RB_UNKNOWN_88F0, 0);
1331
1332 WRITE(REG_A6XX_VPC_UNKNOWN_9236,
1333 A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(0));
1334 WRITE(REG_A6XX_VPC_UNKNOWN_9300, 0);
1335
1336 WRITE(REG_A6XX_VPC_SO_OVERRIDE, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
1337
1338 WRITE(REG_A6XX_PC_UNKNOWN_9990, 0);
1339 WRITE(REG_A6XX_PC_UNKNOWN_9980, 0);
1340
1341 WRITE(REG_A6XX_PC_UNKNOWN_9B07, 0);
1342
1343 WRITE(REG_A6XX_SP_UNKNOWN_A81B, 0);
1344
1345 WRITE(REG_A6XX_SP_UNKNOWN_B183, 0);
1346
1347 WRITE(REG_A6XX_GRAS_UNKNOWN_8099, 0);
1348 WRITE(REG_A6XX_GRAS_UNKNOWN_809B, 0);
1349 WRITE(REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1350 WRITE(REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1351 WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
1352 WRITE(REG_A6XX_VPC_UNKNOWN_9211, 0);
1353 WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
1354 WRITE(REG_A6XX_PC_UNKNOWN_9981, 0x3);
1355 WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
1356 WRITE(REG_A6XX_VPC_UNKNOWN_9108, 0x3);
1357 WRITE(REG_A6XX_SP_TP_SAMPLE_CONFIG, 0);
1358 /* NOTE blob seems to (mostly?) use 0xb2 for SP_TP_UNKNOWN_B309
1359 * but this seems to kill texture gather offsets.
1360 */
1361 WRITE(REG_A6XX_SP_TP_UNKNOWN_B309, 0xa2);
1362 WRITE(REG_A6XX_RB_SAMPLE_CONFIG, 0);
1363 WRITE(REG_A6XX_GRAS_SAMPLE_CONFIG, 0);
1364 WRITE(REG_A6XX_RB_UNKNOWN_8878, 0);
1365 WRITE(REG_A6XX_RB_UNKNOWN_8879, 0);
1366 WRITE(REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1367
1368 emit_marker6(ring, 7);
1369
1370 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
1371 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
1372
1373 WRITE(REG_A6XX_VFD_UNKNOWN_A008, 0);
1374
1375 OUT_PKT4(ring, REG_A6XX_PC_MODE_CNTL, 1);
1376 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
1377
1378 /* we don't use this yet.. probably best to disable.. */
1379 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1380 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1381 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1382 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1383 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1384 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1385
1386 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1387 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
1388
1389 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1390 OUT_RING(ring, 0x00000000);
1391
1392 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
1393 OUT_RING(ring, 0x00000000);
1394
1395 fd_log(batch, "END RESTORE");
1396 }
1397
1398 static void
1399 fd6_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
1400 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
1401 unsigned sizedwords)
1402 {
1403 struct fd_bo *src_bo = fd_resource(src)->bo;
1404 struct fd_bo *dst_bo = fd_resource(dst)->bo;
1405 unsigned i;
1406
1407 for (i = 0; i < sizedwords; i++) {
1408 OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
1409 OUT_RING(ring, 0x00000000);
1410 OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
1411 OUT_RELOC (ring, src_bo, src_off, 0, 0);
1412
1413 dst_off += 4;
1414 src_off += 4;
1415 }
1416 }
1417
1418 /* this is *almost* the same as fd6_cache_flush().. which I guess
1419 * could be re-worked to be something a bit more generic w/ param
1420 * indicating what needs to be flushed.. although that would mean
1421 * figuring out which events trigger what state to flush..
1422 */
1423 static void
1424 fd6_framebuffer_barrier(struct fd_context *ctx)
1425 {
1426 struct fd6_context *fd6_ctx = fd6_context(ctx);
1427 struct fd_batch *batch = ctx->batch;
1428 struct fd_ringbuffer *ring = batch->draw;
1429 unsigned seqno;
1430
1431 seqno = fd6_event_write(batch, ring, RB_DONE_TS, true);
1432
1433 OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);
1434 OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
1435 CP_WAIT_REG_MEM_0_POLL_MEMORY);
1436 OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
1437 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(seqno));
1438 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(~0));
1439 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
1440
1441 fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
1442 fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
1443
1444 seqno = fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
1445
1446 fd6_event_write(batch, ring, 0x31, false);
1447
1448 OUT_PKT7(ring, CP_WAIT_MEM_GTE, 4);
1449 OUT_RING(ring, CP_WAIT_MEM_GTE_0_RESERVED(0));
1450 OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
1451 OUT_RING(ring, CP_WAIT_MEM_GTE_3_REF(seqno));
1452 }
1453
1454 void
1455 fd6_emit_init_screen(struct pipe_screen *pscreen)
1456 {
1457 struct fd_screen *screen = fd_screen(pscreen);
1458 screen->emit_const = fd6_emit_const;
1459 screen->emit_const_bo = fd6_emit_const_bo;
1460 screen->emit_ib = fd6_emit_ib;
1461 screen->mem_to_mem = fd6_mem_to_mem;
1462 }
1463
1464 void
1465 fd6_emit_init(struct pipe_context *pctx)
1466 {
1467 struct fd_context *ctx = fd_context(pctx);
1468 ctx->framebuffer_barrier = fd6_framebuffer_barrier;
1469 }