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c17bd49be4d3264b2334d43103b3c06cc61e509d
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_helpers.h"
32 #include "util/u_format.h"
33 #include "util/u_viewport.h"
34
35 #include "freedreno_resource.h"
36 #include "freedreno_query_hw.h"
37
38 #include "fd6_emit.h"
39 #include "fd6_blend.h"
40 #include "fd6_context.h"
41 #include "fd6_image.h"
42 #include "fd6_program.h"
43 #include "fd6_rasterizer.h"
44 #include "fd6_texture.h"
45 #include "fd6_format.h"
46 #include "fd6_zsa.h"
47
48 static uint32_t
49 shader_t_to_opcode(gl_shader_stage type)
50 {
51 switch (type) {
52 case MESA_SHADER_VERTEX:
53 case MESA_SHADER_TESS_CTRL:
54 case MESA_SHADER_TESS_EVAL:
55 case MESA_SHADER_GEOMETRY:
56 return CP_LOAD_STATE6_GEOM;
57 case MESA_SHADER_FRAGMENT:
58 case MESA_SHADER_COMPUTE:
59 case MESA_SHADER_KERNEL:
60 return CP_LOAD_STATE6_FRAG;
61 default:
62 unreachable("bad shader type");
63 }
64 }
65
66 /* regid: base const register
67 * prsc or dwords: buffer containing constant values
68 * sizedwords: size of const value buffer
69 */
70 static void
71 fd6_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
72 uint32_t regid, uint32_t offset, uint32_t sizedwords,
73 const uint32_t *dwords, struct pipe_resource *prsc)
74 {
75 uint32_t i, sz, align_sz;
76 enum a6xx_state_src src;
77
78 debug_assert((regid % 4) == 0);
79
80 if (prsc) {
81 sz = 0;
82 src = SS6_INDIRECT;
83 } else {
84 sz = sizedwords;
85 src = SS6_DIRECT;
86 }
87
88 align_sz = align(sz, 4);
89
90 OUT_PKT7(ring, shader_t_to_opcode(type), 3 + align_sz);
91 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
92 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
93 CP_LOAD_STATE6_0_STATE_SRC(src) |
94 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
95 CP_LOAD_STATE6_0_NUM_UNIT(DIV_ROUND_UP(sizedwords, 4)));
96 if (prsc) {
97 struct fd_bo *bo = fd_resource(prsc)->bo;
98 OUT_RELOC(ring, bo, offset, 0, 0);
99 } else {
100 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
101 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
102 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
103 }
104
105 for (i = 0; i < sz; i++) {
106 OUT_RING(ring, dwords[i]);
107 }
108
109 /* Zero-pad to multiple of 4 dwords */
110 for (i = sz; i < align_sz; i++) {
111 OUT_RING(ring, 0);
112 }
113 }
114
115 static void
116 fd6_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
117 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
118 {
119 uint32_t anum = align(num, 2);
120 uint32_t i;
121
122 debug_assert((regid % 4) == 0);
123
124 OUT_PKT7(ring, shader_t_to_opcode(type), 3 + (2 * anum));
125 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
126 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS)|
127 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
128 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
129 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
130 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
131 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
132
133 for (i = 0; i < num; i++) {
134 if (prscs[i]) {
135 if (write) {
136 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
137 } else {
138 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
139 }
140 } else {
141 OUT_RING(ring, 0xbad00000 | (i << 16));
142 OUT_RING(ring, 0xbad00000 | (i << 16));
143 }
144 }
145
146 for (; i < anum; i++) {
147 OUT_RING(ring, 0xffffffff);
148 OUT_RING(ring, 0xffffffff);
149 }
150 }
151
152 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
153 * the same as a6xx then move this somewhere common ;-)
154 *
155 * Entry layout looks like (total size, 0x60 bytes):
156 */
157
158 struct PACKED bcolor_entry {
159 uint32_t fp32[4];
160 uint16_t ui16[4];
161 int16_t si16[4];
162 uint16_t fp16[4];
163 uint16_t rgb565;
164 uint16_t rgb5a1;
165 uint16_t rgba4;
166 uint8_t __pad0[2];
167 uint8_t ui8[4];
168 int8_t si8[4];
169 uint32_t rgb10a2;
170 uint32_t z24; /* also s8? */
171 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
172 uint8_t __pad1[56];
173 };
174
175 #define FD6_BORDER_COLOR_SIZE sizeof(struct bcolor_entry)
176 #define FD6_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD6_BORDER_COLOR_SIZE)
177
178 static void
179 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
180 {
181 unsigned i, j;
182 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
183
184 for (i = 0; i < tex->num_samplers; i++) {
185 struct bcolor_entry *e = &entries[i];
186 struct pipe_sampler_state *sampler = tex->samplers[i];
187 union pipe_color_union *bc;
188
189 if (!sampler)
190 continue;
191
192 bc = &sampler->border_color;
193
194 /*
195 * XXX HACK ALERT XXX
196 *
197 * The border colors need to be swizzled in a particular
198 * format-dependent order. Even though samplers don't know about
199 * formats, we can assume that with a GL state tracker, there's a
200 * 1:1 correspondence between sampler and texture. Take advantage
201 * of that knowledge.
202 */
203 if ((i >= tex->num_textures) || !tex->textures[i])
204 continue;
205
206 struct pipe_sampler_view *view = tex->textures[i];
207 enum pipe_format format = view->format;
208 const struct util_format_description *desc =
209 util_format_description(format);
210
211 e->rgb565 = 0;
212 e->rgb5a1 = 0;
213 e->rgba4 = 0;
214 e->rgb10a2 = 0;
215 e->z24 = 0;
216
217 unsigned char swiz[4];
218
219 fd6_tex_swiz(format, swiz,
220 view->swizzle_r, view->swizzle_g,
221 view->swizzle_b, view->swizzle_a);
222
223 for (j = 0; j < 4; j++) {
224 int c = swiz[j];
225 int cd = c;
226
227 /*
228 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the
229 * stencil border color value in bc->ui[0] but according
230 * to desc->swizzle and desc->channel, the .x component
231 * is NONE and the stencil value is in the y component.
232 * Meanwhile the hardware wants this in the .x componetn.
233 */
234 if ((format == PIPE_FORMAT_X24S8_UINT) ||
235 (format == PIPE_FORMAT_X32_S8X24_UINT)) {
236 if (j == 0) {
237 c = 1;
238 cd = 0;
239 } else {
240 continue;
241 }
242 }
243
244 if (c >= 4)
245 continue;
246
247 if (desc->channel[c].pure_integer) {
248 uint16_t clamped;
249 switch (desc->channel[c].size) {
250 case 2:
251 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
252 clamped = CLAMP(bc->ui[j], 0, 0x3);
253 break;
254 case 8:
255 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
256 clamped = CLAMP(bc->i[j], -128, 127);
257 else
258 clamped = CLAMP(bc->ui[j], 0, 255);
259 break;
260 case 10:
261 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
262 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
263 break;
264 case 16:
265 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
266 clamped = CLAMP(bc->i[j], -32768, 32767);
267 else
268 clamped = CLAMP(bc->ui[j], 0, 65535);
269 break;
270 default:
271 assert(!"Unexpected bit size");
272 case 32:
273 clamped = 0;
274 break;
275 }
276 e->fp32[cd] = bc->ui[j];
277 e->fp16[cd] = clamped;
278 } else {
279 float f = bc->f[j];
280 float f_u = CLAMP(f, 0, 1);
281 float f_s = CLAMP(f, -1, 1);
282
283 e->fp32[c] = fui(f);
284 e->fp16[c] = util_float_to_half(f);
285 e->srgb[c] = util_float_to_half(f_u);
286 e->ui16[c] = f_u * 0xffff;
287 e->si16[c] = f_s * 0x7fff;
288 e->ui8[c] = f_u * 0xff;
289 e->si8[c] = f_s * 0x7f;
290 if (c == 1)
291 e->rgb565 |= (int)(f_u * 0x3f) << 5;
292 else if (c < 3)
293 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
294 if (c == 3)
295 e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
296 else
297 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
298 if (c == 3)
299 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
300 else
301 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
302 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
303 if (c == 0)
304 e->z24 = f_u * 0xffffff;
305 }
306 }
307
308 #ifdef DEBUG
309 memset(&e->__pad0, 0, sizeof(e->__pad0));
310 memset(&e->__pad1, 0, sizeof(e->__pad1));
311 #endif
312 }
313 }
314
315 static void
316 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
317 {
318 struct fd6_context *fd6_ctx = fd6_context(ctx);
319 struct bcolor_entry *entries;
320 unsigned off;
321 void *ptr;
322
323 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
324
325 u_upload_alloc(fd6_ctx->border_color_uploader,
326 0, FD6_BORDER_COLOR_UPLOAD_SIZE,
327 FD6_BORDER_COLOR_UPLOAD_SIZE, &off,
328 &fd6_ctx->border_color_buf,
329 &ptr);
330
331 entries = ptr;
332
333 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
334 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
335 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
336
337 OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
338 OUT_RELOC(ring, fd_resource(fd6_ctx->border_color_buf)->bo, off, 0, 0);
339
340 u_upload_unmap(fd6_ctx->border_color_uploader);
341 }
342
343 static void
344 fd6_emit_fb_tex(struct fd_ringbuffer *state, struct fd_context *ctx)
345 {
346 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
347 struct pipe_surface *psurf = pfb->cbufs[0];
348 struct fd_resource *rsc = fd_resource(psurf->texture);
349
350 uint32_t texconst0 = fd6_tex_const_0(psurf->texture, psurf->u.tex.level,
351 psurf->format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
352 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W);
353
354 /* always TILE6_2 mode in GMEM.. which also means no swap: */
355 texconst0 &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
356 texconst0 |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
357
358 OUT_RING(state, texconst0);
359 OUT_RING(state, A6XX_TEX_CONST_1_WIDTH(pfb->width) |
360 A6XX_TEX_CONST_1_HEIGHT(pfb->height));
361 OUT_RINGP(state, A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
362 A6XX_TEX_CONST_2_FETCHSIZE(TFETCH6_2_BYTE),
363 &ctx->batch->fb_read_patches);
364 OUT_RING(state, A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layer_size));
365
366 OUT_RING(state, A6XX_TEX_CONST_4_BASE_LO(ctx->screen->gmem_base));
367 OUT_RING(state, A6XX_TEX_CONST_5_BASE_HI(ctx->screen->gmem_base >> 32) |
368 A6XX_TEX_CONST_5_DEPTH(1));
369 OUT_RING(state, 0); /* texconst6 */
370 OUT_RING(state, 0); /* texconst7 */
371 OUT_RING(state, 0); /* texconst8 */
372 OUT_RING(state, 0); /* texconst9 */
373 OUT_RING(state, 0); /* texconst10 */
374 OUT_RING(state, 0); /* texconst11 */
375 OUT_RING(state, 0);
376 OUT_RING(state, 0);
377 OUT_RING(state, 0);
378 OUT_RING(state, 0);
379 }
380
381 bool
382 fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
383 enum pipe_shader_type type, struct fd_texture_stateobj *tex,
384 unsigned bcolor_offset,
385 /* can be NULL if no image/SSBO/fb state to merge in: */
386 const struct ir3_shader_variant *v, struct fd_context *ctx)
387 {
388 bool needs_border = false;
389 unsigned opcode, tex_samp_reg, tex_const_reg, tex_count_reg;
390 enum a6xx_state_block sb;
391
392 switch (type) {
393 case PIPE_SHADER_VERTEX:
394 sb = SB6_VS_TEX;
395 opcode = CP_LOAD_STATE6_GEOM;
396 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
397 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
398 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
399 break;
400 case PIPE_SHADER_FRAGMENT:
401 sb = SB6_FS_TEX;
402 opcode = CP_LOAD_STATE6_FRAG;
403 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
404 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
405 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
406 break;
407 case PIPE_SHADER_COMPUTE:
408 sb = SB6_CS_TEX;
409 opcode = CP_LOAD_STATE6_FRAG;
410 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
411 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
412 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
413 break;
414 default:
415 unreachable("bad state block");
416 }
417
418 if (tex->num_samplers > 0) {
419 struct fd_ringbuffer *state =
420 fd_ringbuffer_new_object(pipe, tex->num_samplers * 4 * 4);
421 for (unsigned i = 0; i < tex->num_samplers; i++) {
422 static const struct fd6_sampler_stateobj dummy_sampler = {};
423 const struct fd6_sampler_stateobj *sampler = tex->samplers[i] ?
424 fd6_sampler_stateobj(tex->samplers[i]) : &dummy_sampler;
425 OUT_RING(state, sampler->texsamp0);
426 OUT_RING(state, sampler->texsamp1);
427 OUT_RING(state, sampler->texsamp2 |
428 A6XX_TEX_SAMP_2_BCOLOR_OFFSET((i + bcolor_offset) * sizeof(struct bcolor_entry)));
429 OUT_RING(state, sampler->texsamp3);
430 needs_border |= sampler->needs_border;
431 }
432
433 /* output sampler state: */
434 OUT_PKT7(ring, opcode, 3);
435 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
436 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
437 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
438 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
439 CP_LOAD_STATE6_0_NUM_UNIT(tex->num_samplers));
440 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
441
442 OUT_PKT4(ring, tex_samp_reg, 2);
443 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
444
445 fd_ringbuffer_del(state);
446 }
447
448 unsigned num_merged_textures = tex->num_textures;
449 unsigned num_textures = tex->num_textures;
450 if (v) {
451 num_merged_textures += v->image_mapping.num_tex;
452
453 if (v->fb_read)
454 num_merged_textures++;
455
456 /* There could be more bound textures than what the shader uses.
457 * Which isn't known at shader compile time. So in the case we
458 * are merging tex state, only emit the textures that the shader
459 * uses (since the image/SSBO related tex state comes immediately
460 * after)
461 */
462 num_textures = v->image_mapping.tex_base;
463 }
464
465 if (num_merged_textures > 0) {
466 struct fd_ringbuffer *state =
467 fd_ringbuffer_new_object(pipe, num_merged_textures * 16 * 4);
468 for (unsigned i = 0; i < num_textures; i++) {
469 static const struct fd6_pipe_sampler_view dummy_view = {};
470 const struct fd6_pipe_sampler_view *view = tex->textures[i] ?
471 fd6_pipe_sampler_view(tex->textures[i]) : &dummy_view;
472 struct fd_resource *rsc = NULL;
473
474 if (view->base.texture)
475 rsc = fd_resource(view->base.texture);
476
477 OUT_RING(state, view->texconst0);
478 OUT_RING(state, view->texconst1);
479 OUT_RING(state, view->texconst2);
480 OUT_RING(state, view->texconst3);
481
482 if (rsc) {
483 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
484 rsc = rsc->stencil;
485 OUT_RELOC(state, rsc->bo, view->offset + rsc->offset,
486 (uint64_t)view->texconst5 << 32, 0);
487 } else {
488 OUT_RING(state, 0x00000000);
489 OUT_RING(state, view->texconst5);
490 }
491
492 OUT_RING(state, view->texconst6);
493
494 if (rsc && view->ubwc_enabled) {
495 OUT_RELOC(state, rsc->bo, view->offset + rsc->ubwc_offset, 0, 0);
496 } else {
497 OUT_RING(state, 0);
498 OUT_RING(state, 0);
499 }
500
501 OUT_RING(state, view->texconst9);
502 OUT_RING(state, view->texconst10);
503 OUT_RING(state, view->texconst11);
504 OUT_RING(state, 0);
505 OUT_RING(state, 0);
506 OUT_RING(state, 0);
507 OUT_RING(state, 0);
508 }
509
510 if (v) {
511 const struct ir3_ibo_mapping *mapping = &v->image_mapping;
512 struct fd_shaderbuf_stateobj *buf = &ctx->shaderbuf[type];
513 struct fd_shaderimg_stateobj *img = &ctx->shaderimg[type];
514
515 for (unsigned i = 0; i < mapping->num_tex; i++) {
516 unsigned idx = mapping->tex_to_image[i];
517 if (idx & IBO_SSBO) {
518 fd6_emit_ssbo_tex(state, &buf->sb[idx & ~IBO_SSBO]);
519 } else {
520 fd6_emit_image_tex(state, &img->si[idx]);
521 }
522 }
523
524 if (v->fb_read) {
525 fd6_emit_fb_tex(state, ctx);
526 }
527 }
528
529 /* emit texture state: */
530 OUT_PKT7(ring, opcode, 3);
531 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
532 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
533 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
534 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
535 CP_LOAD_STATE6_0_NUM_UNIT(num_merged_textures));
536 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
537
538 OUT_PKT4(ring, tex_const_reg, 2);
539 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
540
541 fd_ringbuffer_del(state);
542 }
543
544 OUT_PKT4(ring, tex_count_reg, 1);
545 OUT_RING(ring, num_merged_textures);
546
547 return needs_border;
548 }
549
550 /* Emits combined texture state, which also includes any Image/SSBO
551 * related texture state merged in (because we must have all texture
552 * state for a given stage in a single buffer). In the fast-path, if
553 * we don't need to merge in any image/ssbo related texture state, we
554 * just use cached texture stateobj. Otherwise we generate a single-
555 * use stateobj.
556 *
557 * TODO Is there some sane way we can still use cached texture stateobj
558 * with image/ssbo in use?
559 *
560 * returns whether border_color is required:
561 */
562 static bool
563 fd6_emit_combined_textures(struct fd_ringbuffer *ring, struct fd6_emit *emit,
564 enum pipe_shader_type type, const struct ir3_shader_variant *v)
565 {
566 struct fd_context *ctx = emit->ctx;
567 bool needs_border = false;
568
569 static const enum fd6_state_id state_id[PIPE_SHADER_TYPES] = {
570 [PIPE_SHADER_VERTEX] = FD6_GROUP_VS_TEX,
571 [PIPE_SHADER_FRAGMENT] = FD6_GROUP_FS_TEX,
572 };
573
574 debug_assert(state_id[type]);
575
576 if (!v->image_mapping.num_tex && !v->fb_read) {
577 /* in the fast-path, when we don't have to mix in any image/SSBO
578 * related texture state, we can just lookup the stateobj and
579 * re-emit that:
580 *
581 * Also, framebuffer-read is a slow-path because an extra
582 * texture needs to be inserted.
583 *
584 * TODO we can probably simmplify things if we also treated
585 * border_color as a slow-path.. this way the tex state key
586 * wouldn't depend on bcolor_offset.. but fb_read might rather
587 * be *somehow* a fast-path if we eventually used it for PLS.
588 * I suppose there would be no harm in just *always* inserting
589 * an fb_read texture?
590 */
591 if ((ctx->dirty_shader[type] & FD_DIRTY_SHADER_TEX) &&
592 ctx->tex[type].num_textures > 0) {
593 struct fd6_texture_state *tex = fd6_texture_state(ctx,
594 type, &ctx->tex[type]);
595
596 needs_border |= tex->needs_border;
597
598 fd6_emit_add_group(emit, tex->stateobj, state_id[type], 0x7);
599 }
600 } else {
601 /* In the slow-path, create a one-shot texture state object
602 * if either TEX|PROG|SSBO|IMAGE state is dirty:
603 */
604 if ((ctx->dirty_shader[type] &
605 (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
606 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) ||
607 v->fb_read) {
608 struct fd_texture_stateobj *tex = &ctx->tex[type];
609 struct fd_ringbuffer *stateobj =
610 fd_submit_new_ringbuffer(ctx->batch->submit,
611 0x1000, FD_RINGBUFFER_STREAMING);
612 unsigned bcolor_offset =
613 fd6_border_color_offset(ctx, type, tex);
614
615 needs_border |= fd6_emit_textures(ctx->pipe, stateobj, type, tex,
616 bcolor_offset, v, ctx);
617
618 fd6_emit_add_group(emit, stateobj, state_id[type], 0x7);
619
620 fd_ringbuffer_del(stateobj);
621 }
622 }
623
624 return needs_border;
625 }
626
627 static struct fd_ringbuffer *
628 build_vbo_state(struct fd6_emit *emit, const struct ir3_shader_variant *vp)
629 {
630 const struct fd_vertex_state *vtx = emit->vtx;
631 int32_t i, j;
632
633 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
634 4 * (10 * vp->inputs_count + 2), FD_RINGBUFFER_STREAMING);
635
636 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
637 if (vp->inputs[i].sysval)
638 continue;
639 if (vp->inputs[i].compmask) {
640 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
641 const struct pipe_vertex_buffer *vb =
642 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
643 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
644 enum pipe_format pfmt = elem->src_format;
645 enum a6xx_vtx_fmt fmt = fd6_pipe2vtx(pfmt);
646 bool isint = util_format_is_pure_integer(pfmt);
647 uint32_t off = vb->buffer_offset + elem->src_offset;
648 uint32_t size = fd_bo_size(rsc->bo) - off;
649 debug_assert(fmt != ~0);
650
651 #ifdef DEBUG
652 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
653 */
654 if (off > fd_bo_size(rsc->bo))
655 continue;
656 #endif
657
658 OUT_PKT4(ring, REG_A6XX_VFD_FETCH(j), 4);
659 OUT_RELOC(ring, rsc->bo, off, 0, 0);
660 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
661 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
662
663 OUT_PKT4(ring, REG_A6XX_VFD_DECODE(j), 2);
664 OUT_RING(ring, A6XX_VFD_DECODE_INSTR_IDX(j) |
665 A6XX_VFD_DECODE_INSTR_FORMAT(fmt) |
666 COND(elem->instance_divisor, A6XX_VFD_DECODE_INSTR_INSTANCED) |
667 A6XX_VFD_DECODE_INSTR_SWAP(fd6_pipe2swap(pfmt)) |
668 A6XX_VFD_DECODE_INSTR_UNK30 |
669 COND(!isint, A6XX_VFD_DECODE_INSTR_FLOAT));
670 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
671
672 OUT_PKT4(ring, REG_A6XX_VFD_DEST_CNTL(j), 1);
673 OUT_RING(ring, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
674 A6XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
675
676 j++;
677 }
678 }
679
680 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_0, 1);
681 OUT_RING(ring, A6XX_VFD_CONTROL_0_VTXCNT(j) | (j << 8));
682
683 return ring;
684 }
685
686 static struct fd_ringbuffer *
687 build_lrz(struct fd6_emit *emit, bool binning_pass)
688 {
689 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(emit->ctx->zsa);
690 struct pipe_framebuffer_state *pfb = &emit->ctx->batch->framebuffer;
691 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
692 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
693 uint32_t rb_lrz_cntl = zsa->rb_lrz_cntl;
694
695 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
696 16, FD_RINGBUFFER_STREAMING);
697
698 if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid) {
699 gras_lrz_cntl = 0;
700 rb_lrz_cntl = 0;
701 } else if (binning_pass && zsa->lrz_write) {
702 gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_LRZ_WRITE;
703 }
704
705 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
706 OUT_RING(ring, gras_lrz_cntl);
707
708 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
709 OUT_RING(ring, rb_lrz_cntl);
710
711 return ring;
712 }
713
714 static void
715 fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3_stream_output_info *info)
716 {
717 struct fd_context *ctx = emit->ctx;
718 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
719 struct fd_streamout_stateobj *so = &ctx->streamout;
720
721 emit->streamout_mask = 0;
722
723 for (unsigned i = 0; i < so->num_targets; i++) {
724 struct pipe_stream_output_target *target = so->targets[i];
725
726 if (!target)
727 continue;
728
729 unsigned offset = (so->offsets[i] * info->stride[i] * 4) +
730 target->buffer_offset;
731
732 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(i), 3);
733 /* VPC_SO[i].BUFFER_BASE_LO: */
734 OUT_RELOCW(ring, fd_resource(target->buffer)->bo, 0, 0, 0);
735 OUT_RING(ring, target->buffer_size + offset);
736
737 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(i), 3);
738 OUT_RING(ring, offset);
739 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
740 // TODO just give hw a dummy addr for now.. we should
741 // be using this an then CP_MEM_TO_REG to set the
742 // VPC_SO[i].BUFFER_OFFSET for the next draw..
743 OUT_RELOCW(ring, fd6_context(ctx)->blit_mem, 0x100, 0, 0);
744
745 emit->streamout_mask |= (1 << i);
746 }
747
748 if (emit->streamout_mask) {
749 const struct fd6_streamout_state *tf = &prog->tf;
750
751 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * tf->prog_count));
752 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
753 OUT_RING(ring, tf->vpc_so_buf_cntl);
754 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0));
755 OUT_RING(ring, tf->ncomp[0]);
756 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1));
757 OUT_RING(ring, tf->ncomp[1]);
758 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(2));
759 OUT_RING(ring, tf->ncomp[2]);
760 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3));
761 OUT_RING(ring, tf->ncomp[3]);
762 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
763 OUT_RING(ring, A6XX_VPC_SO_CNTL_ENABLE);
764 for (unsigned i = 0; i < tf->prog_count; i++) {
765 OUT_RING(ring, REG_A6XX_VPC_SO_PROG);
766 OUT_RING(ring, tf->prog[i]);
767 }
768
769 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
770 OUT_RING(ring, 0x0);
771 } else {
772 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 4);
773 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
774 OUT_RING(ring, 0);
775 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
776 OUT_RING(ring, 0);
777
778 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
779 OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
780 }
781
782 }
783
784 void
785 fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
786 {
787 struct fd_context *ctx = emit->ctx;
788 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
789 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
790 const struct ir3_shader_variant *vp = emit->vs;
791 const struct ir3_shader_variant *fp = emit->fs;
792 const enum fd_dirty_3d_state dirty = emit->dirty;
793 bool needs_border = false;
794
795 emit_marker6(ring, 5);
796
797 /* NOTE: we track fb_read differently than _BLEND_ENABLED since
798 * we might at some point decide to do sysmem in some cases when
799 * blend is enabled:
800 */
801 if (fp->fb_read)
802 ctx->batch->gmem_reason |= FD_GMEM_FB_READ;
803
804 if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE)) {
805 struct fd_ringbuffer *state;
806
807 state = build_vbo_state(emit, emit->vs);
808 fd6_emit_add_group(emit, state, FD6_GROUP_VBO, 0x6);
809 fd_ringbuffer_del(state);
810
811 state = build_vbo_state(emit, emit->bs);
812 fd6_emit_add_group(emit, state, FD6_GROUP_VBO_BINNING, 0x1);
813 fd_ringbuffer_del(state);
814 }
815
816 if (dirty & FD_DIRTY_ZSA) {
817 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
818
819 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
820 fd6_emit_add_group(emit, zsa->stateobj_no_alpha, FD6_GROUP_ZSA, 0x7);
821 else
822 fd6_emit_add_group(emit, zsa->stateobj, FD6_GROUP_ZSA, 0x7);
823 }
824
825 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && pfb->zsbuf) {
826 struct fd_ringbuffer *state;
827
828 state = build_lrz(emit, false);
829 fd6_emit_add_group(emit, state, FD6_GROUP_LRZ, 0x6);
830 fd_ringbuffer_del(state);
831
832 state = build_lrz(emit, true);
833 fd6_emit_add_group(emit, state, FD6_GROUP_LRZ_BINNING, 0x1);
834 fd_ringbuffer_del(state);
835 }
836
837 if (dirty & FD_DIRTY_STENCIL_REF) {
838 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
839
840 OUT_PKT4(ring, REG_A6XX_RB_STENCILREF, 1);
841 OUT_RING(ring, A6XX_RB_STENCILREF_REF(sr->ref_value[0]) |
842 A6XX_RB_STENCILREF_BFREF(sr->ref_value[1]));
843 }
844
845 /* NOTE: scissor enabled bit is part of rasterizer state: */
846 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
847 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
848
849 OUT_PKT4(ring, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
850 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
851 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
852 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
853 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
854
855 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
856 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
857 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
858 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
859 }
860
861 if (dirty & FD_DIRTY_VIEWPORT) {
862 struct pipe_scissor_state *scissor = &ctx->viewport_scissor;
863
864 OUT_PKT4(ring, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
865 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
866 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
867 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
868 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
869 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
870 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
871
872 OUT_PKT4(ring, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
873 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
874 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
875 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
876 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
877
878 unsigned guardband_x = fd_calc_guardband(scissor->maxx - scissor->minx);
879 unsigned guardband_y = fd_calc_guardband(scissor->maxy - scissor->miny);
880
881 OUT_PKT4(ring, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
882 OUT_RING(ring, A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_x) |
883 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_y));
884 }
885
886 if (dirty & FD_DIRTY_PROG) {
887 fd6_emit_add_group(emit, prog->stateobj, FD6_GROUP_PROG, 0x6);
888 fd6_emit_add_group(emit, prog->binning_stateobj,
889 FD6_GROUP_PROG_BINNING, 0x1);
890
891 /* emit remaining non-stateobj program state, ie. what depends
892 * on other emit state, so cannot be pre-baked. This could
893 * be moved to a separate stateobj which is dynamically
894 * created.
895 */
896 fd6_program_emit(ring, emit);
897 }
898
899 if (dirty & FD_DIRTY_RASTERIZER) {
900 struct fd6_rasterizer_stateobj *rasterizer =
901 fd6_rasterizer_stateobj(ctx->rasterizer);
902 fd6_emit_add_group(emit, rasterizer->stateobj,
903 FD6_GROUP_RASTERIZER, 0x7);
904 }
905
906 /* Since the primitive restart state is not part of a tracked object, we
907 * re-emit this register every time.
908 */
909 if (emit->info && ctx->rasterizer) {
910 struct fd6_rasterizer_stateobj *rasterizer =
911 fd6_rasterizer_stateobj(ctx->rasterizer);
912 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9806, 1);
913 OUT_RING(ring, 0);
914 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9990, 1);
915 OUT_RING(ring, 0);
916 OUT_PKT4(ring, REG_A6XX_VFD_UNKNOWN_A008, 1);
917 OUT_RING(ring, 0);
918
919 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
920 OUT_RING(ring, rasterizer->pc_primitive_cntl |
921 COND(emit->info->primitive_restart && emit->info->index_size,
922 A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART));
923 }
924
925 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
926 unsigned nr = pfb->nr_cbufs;
927
928 if (ctx->rasterizer->rasterizer_discard)
929 nr = 0;
930
931 OUT_PKT4(ring, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
932 OUT_RING(ring, COND(fp->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
933 COND(fp->writes_smask && pfb->samples > 1,
934 A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
935 OUT_RING(ring, A6XX_RB_FS_OUTPUT_CNTL1_MRT(nr));
936
937 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL1, 1);
938 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL1_MRT(nr));
939 }
940
941 #define DIRTY_CONST (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST | \
942 FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)
943
944 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & DIRTY_CONST) {
945 struct fd_ringbuffer *vsconstobj = fd_submit_new_ringbuffer(
946 ctx->batch->submit, 0x1000, FD_RINGBUFFER_STREAMING);
947
948 OUT_WFI5(vsconstobj);
949 ir3_emit_vs_consts(vp, vsconstobj, ctx, emit->info);
950 fd6_emit_add_group(emit, vsconstobj, FD6_GROUP_VS_CONST, 0x7);
951 fd_ringbuffer_del(vsconstobj);
952 }
953
954 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & DIRTY_CONST) {
955 struct fd_ringbuffer *fsconstobj = fd_submit_new_ringbuffer(
956 ctx->batch->submit, 0x1000, FD_RINGBUFFER_STREAMING);
957
958 OUT_WFI5(fsconstobj);
959 ir3_emit_fs_consts(fp, fsconstobj, ctx);
960 fd6_emit_add_group(emit, fsconstobj, FD6_GROUP_FS_CONST, 0x6);
961 fd_ringbuffer_del(fsconstobj);
962 }
963
964 struct ir3_stream_output_info *info = &vp->shader->stream_output;
965 if (info->num_outputs)
966 fd6_emit_streamout(ring, emit, info);
967
968 if (dirty & FD_DIRTY_BLEND) {
969 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
970 uint32_t i;
971
972 for (i = 0; i < pfb->nr_cbufs; i++) {
973 enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
974 bool is_int = util_format_is_pure_integer(format);
975 bool has_alpha = util_format_has_alpha(format);
976 uint32_t control = blend->rb_mrt[i].control;
977 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
978
979 if (is_int) {
980 control &= A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
981 control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
982 }
983
984 if (has_alpha) {
985 blend_control |= blend->rb_mrt[i].blend_control_rgb;
986 } else {
987 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
988 control &= ~A6XX_RB_MRT_CONTROL_BLEND2;
989 }
990
991 OUT_PKT4(ring, REG_A6XX_RB_MRT_CONTROL(i), 1);
992 OUT_RING(ring, control);
993
994 OUT_PKT4(ring, REG_A6XX_RB_MRT_BLEND_CONTROL(i), 1);
995 OUT_RING(ring, blend_control);
996 }
997
998 OUT_PKT4(ring, REG_A6XX_SP_BLEND_CNTL, 1);
999 OUT_RING(ring, blend->sp_blend_cntl);
1000 }
1001
1002 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK)) {
1003 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
1004
1005 OUT_PKT4(ring, REG_A6XX_RB_BLEND_CNTL, 1);
1006 OUT_RING(ring, blend->rb_blend_cntl |
1007 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(ctx->sample_mask));
1008 }
1009
1010 if (dirty & FD_DIRTY_BLEND_COLOR) {
1011 struct pipe_blend_color *bcolor = &ctx->blend_color;
1012
1013 OUT_PKT4(ring, REG_A6XX_RB_BLEND_RED_F32, 4);
1014 OUT_RING(ring, A6XX_RB_BLEND_RED_F32(bcolor->color[0]));
1015 OUT_RING(ring, A6XX_RB_BLEND_GREEN_F32(bcolor->color[1]));
1016 OUT_RING(ring, A6XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
1017 OUT_RING(ring, A6XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
1018 }
1019
1020 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_VERTEX, vp);
1021 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_FRAGMENT, fp);
1022
1023 if (needs_border)
1024 emit_border_color(ctx, ring);
1025
1026 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] &
1027 (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)) {
1028 struct fd_ringbuffer *state =
1029 fd6_build_ibo_state(ctx, fp, PIPE_SHADER_FRAGMENT);
1030 struct fd_ringbuffer *obj = fd_submit_new_ringbuffer(
1031 ctx->batch->submit, 9 * 4, FD_RINGBUFFER_STREAMING);
1032 const struct ir3_ibo_mapping *mapping = &fp->image_mapping;
1033
1034 OUT_PKT7(obj, CP_LOAD_STATE6, 3);
1035 OUT_RING(obj, CP_LOAD_STATE6_0_DST_OFF(0) |
1036 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1037 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1038 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_IBO) |
1039 CP_LOAD_STATE6_0_NUM_UNIT(mapping->num_ibo));
1040 OUT_RB(obj, state);
1041
1042 OUT_PKT4(obj, REG_A6XX_SP_IBO_LO, 2);
1043 OUT_RB(obj, state);
1044
1045 OUT_PKT4(obj, REG_A6XX_SP_IBO_COUNT, 1);
1046 OUT_RING(obj, mapping->num_ibo);
1047
1048 fd6_emit_add_group(emit, obj, FD6_GROUP_IBO, 0x7);
1049 fd_ringbuffer_del(obj);
1050 fd_ringbuffer_del(state);
1051 }
1052
1053 if (emit->num_groups > 0) {
1054 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3 * emit->num_groups);
1055 for (unsigned i = 0; i < emit->num_groups; i++) {
1056 struct fd6_state_group *g = &emit->groups[i];
1057 unsigned n = fd_ringbuffer_size(g->stateobj) / 4;
1058
1059 if (n == 0) {
1060 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1061 CP_SET_DRAW_STATE__0_DISABLE |
1062 CP_SET_DRAW_STATE__0_ENABLE_MASK(g->enable_mask) |
1063 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
1064 OUT_RING(ring, 0x00000000);
1065 OUT_RING(ring, 0x00000000);
1066 } else {
1067 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(n) |
1068 CP_SET_DRAW_STATE__0_ENABLE_MASK(g->enable_mask) |
1069 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
1070 OUT_RB(ring, g->stateobj);
1071 }
1072
1073 fd_ringbuffer_del(g->stateobj);
1074 }
1075 emit->num_groups = 0;
1076 }
1077 }
1078
1079 void
1080 fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
1081 struct ir3_shader_variant *cp)
1082 {
1083 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
1084
1085 if (dirty & (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
1086 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) {
1087 struct fd_texture_stateobj *tex = &ctx->tex[PIPE_SHADER_COMPUTE];
1088 unsigned bcolor_offset = fd6_border_color_offset(ctx, PIPE_SHADER_COMPUTE, tex);
1089
1090 bool needs_border = fd6_emit_textures(ctx->pipe, ring, PIPE_SHADER_COMPUTE, tex,
1091 bcolor_offset, cp, ctx);
1092
1093 if (needs_border)
1094 emit_border_color(ctx, ring);
1095
1096 OUT_PKT4(ring, REG_A6XX_SP_VS_TEX_COUNT, 1);
1097 OUT_RING(ring, 0);
1098
1099 OUT_PKT4(ring, REG_A6XX_SP_HS_TEX_COUNT, 1);
1100 OUT_RING(ring, 0);
1101
1102 OUT_PKT4(ring, REG_A6XX_SP_DS_TEX_COUNT, 1);
1103 OUT_RING(ring, 0);
1104
1105 OUT_PKT4(ring, REG_A6XX_SP_GS_TEX_COUNT, 1);
1106 OUT_RING(ring, 0);
1107
1108 OUT_PKT4(ring, REG_A6XX_SP_FS_TEX_COUNT, 1);
1109 OUT_RING(ring, 0);
1110 }
1111
1112 if (dirty & (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)) {
1113 struct fd_ringbuffer *state =
1114 fd6_build_ibo_state(ctx, cp, PIPE_SHADER_COMPUTE);
1115 const struct ir3_ibo_mapping *mapping = &cp->image_mapping;
1116
1117 OUT_PKT7(ring, CP_LOAD_STATE6_FRAG, 3);
1118 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
1119 CP_LOAD_STATE6_0_STATE_TYPE(ST6_IBO) |
1120 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1121 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_CS_SHADER) |
1122 CP_LOAD_STATE6_0_NUM_UNIT(mapping->num_ibo));
1123 OUT_RB(ring, state);
1124
1125 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_LO, 2);
1126 OUT_RB(ring, state);
1127
1128 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_COUNT, 1);
1129 OUT_RING(ring, mapping->num_ibo);
1130
1131 fd_ringbuffer_del(state);
1132 }
1133 }
1134
1135
1136 /* emit setup at begin of new cmdstream buffer (don't rely on previous
1137 * state, there could have been a context switch between ioctls):
1138 */
1139 void
1140 fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
1141 {
1142 //struct fd_context *ctx = batch->ctx;
1143
1144 fd6_cache_inv(batch, ring);
1145
1146 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1147 OUT_RING(ring, 0xfffff);
1148
1149 /*
1150 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
1151 0000000500024048: 70d08003 00000000 001c5000 00000005
1152 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
1153 0000000500024058: 70d08003 00000010 001c7000 00000005
1154
1155 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
1156 0000000500024068: 70268000
1157 */
1158
1159 WRITE(REG_A6XX_RB_CCU_CNTL, 0x7c400004);
1160 WRITE(REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
1161 WRITE(REG_A6XX_SP_UNKNOWN_AE04, 0x8);
1162 WRITE(REG_A6XX_SP_UNKNOWN_AE00, 0);
1163 WRITE(REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
1164 WRITE(REG_A6XX_SP_UNKNOWN_B605, 0x44);
1165 WRITE(REG_A6XX_SP_UNKNOWN_B600, 0x100000);
1166 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
1167 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
1168
1169 WRITE(REG_A6XX_VPC_UNKNOWN_9600, 0);
1170 WRITE(REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
1171 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
1172 WRITE(REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
1173 WRITE(REG_A6XX_SP_IBO_COUNT, 0);
1174 WRITE(REG_A6XX_SP_UNKNOWN_B182, 0);
1175 WRITE(REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
1176 WRITE(REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
1177 WRITE(REG_A6XX_UCHE_CLIENT_PF, 4);
1178 WRITE(REG_A6XX_RB_UNKNOWN_8E01, 0x0);
1179 WRITE(REG_A6XX_SP_UNKNOWN_AB00, 0x5);
1180 WRITE(REG_A6XX_VFD_UNKNOWN_A009, 0x00000001);
1181 WRITE(REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
1182 WRITE(REG_A6XX_PC_MODE_CNTL, 0x1f);
1183
1184 OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
1185 OUT_RING(ring, 0);
1186
1187 WRITE(REG_A6XX_GRAS_UNKNOWN_8101, 0);
1188 WRITE(REG_A6XX_GRAS_SAMPLE_CNTL, 0);
1189 WRITE(REG_A6XX_GRAS_UNKNOWN_8110, 0);
1190
1191 WRITE(REG_A6XX_RB_RENDER_CONTROL0, 0x401);
1192 WRITE(REG_A6XX_RB_RENDER_CONTROL1, 0);
1193 WRITE(REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
1194 WRITE(REG_A6XX_RB_SAMPLE_CNTL, 0);
1195 WRITE(REG_A6XX_RB_UNKNOWN_8818, 0);
1196 WRITE(REG_A6XX_RB_UNKNOWN_8819, 0);
1197 WRITE(REG_A6XX_RB_UNKNOWN_881A, 0);
1198 WRITE(REG_A6XX_RB_UNKNOWN_881B, 0);
1199 WRITE(REG_A6XX_RB_UNKNOWN_881C, 0);
1200 WRITE(REG_A6XX_RB_UNKNOWN_881D, 0);
1201 WRITE(REG_A6XX_RB_UNKNOWN_881E, 0);
1202 WRITE(REG_A6XX_RB_UNKNOWN_88F0, 0);
1203
1204 WRITE(REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
1205 WRITE(REG_A6XX_VPC_UNKNOWN_9107, 0);
1206
1207 WRITE(REG_A6XX_VPC_UNKNOWN_9236,
1208 A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(0));
1209 WRITE(REG_A6XX_VPC_UNKNOWN_9300, 0);
1210
1211 WRITE(REG_A6XX_VPC_SO_OVERRIDE, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
1212
1213 WRITE(REG_A6XX_PC_UNKNOWN_9801, 0);
1214 WRITE(REG_A6XX_PC_UNKNOWN_9806, 0);
1215 WRITE(REG_A6XX_PC_UNKNOWN_9980, 0);
1216
1217 WRITE(REG_A6XX_PC_UNKNOWN_9B06, 0);
1218 WRITE(REG_A6XX_PC_UNKNOWN_9B06, 0);
1219
1220 WRITE(REG_A6XX_SP_UNKNOWN_A81B, 0);
1221
1222 WRITE(REG_A6XX_SP_UNKNOWN_B183, 0);
1223
1224 WRITE(REG_A6XX_GRAS_UNKNOWN_8099, 0);
1225 WRITE(REG_A6XX_GRAS_UNKNOWN_809B, 0);
1226 WRITE(REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1227 WRITE(REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1228 WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
1229 WRITE(REG_A6XX_VPC_UNKNOWN_9211, 0);
1230 WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
1231 WRITE(REG_A6XX_PC_UNKNOWN_9981, 0x3);
1232 WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
1233 WRITE(REG_A6XX_VPC_UNKNOWN_9108, 0x3);
1234 WRITE(REG_A6XX_SP_TP_UNKNOWN_B304, 0);
1235 WRITE(REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
1236 WRITE(REG_A6XX_RB_UNKNOWN_8804, 0);
1237 WRITE(REG_A6XX_GRAS_UNKNOWN_80A4, 0);
1238 WRITE(REG_A6XX_GRAS_UNKNOWN_80A5, 0);
1239 WRITE(REG_A6XX_GRAS_UNKNOWN_80A6, 0);
1240 WRITE(REG_A6XX_RB_UNKNOWN_8805, 0);
1241 WRITE(REG_A6XX_RB_UNKNOWN_8806, 0);
1242 WRITE(REG_A6XX_RB_UNKNOWN_8878, 0);
1243 WRITE(REG_A6XX_RB_UNKNOWN_8879, 0);
1244 WRITE(REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1245
1246 emit_marker6(ring, 7);
1247
1248 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
1249 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
1250
1251 WRITE(REG_A6XX_VFD_UNKNOWN_A008, 0);
1252
1253 OUT_PKT4(ring, REG_A6XX_PC_MODE_CNTL, 1);
1254 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
1255
1256 /* we don't use this yet.. probably best to disable.. */
1257 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1258 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1259 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1260 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1261 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1262 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1263
1264 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1265 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
1266
1267 OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1);
1268 OUT_RING(ring, 0x00000000);
1269
1270 OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
1271 OUT_RING(ring, 0x00000000);
1272
1273 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1274 OUT_RING(ring, 0x00000000);
1275
1276 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
1277 OUT_RING(ring, 0x00000000);
1278 }
1279
1280 static void
1281 fd6_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
1282 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
1283 unsigned sizedwords)
1284 {
1285 struct fd_bo *src_bo = fd_resource(src)->bo;
1286 struct fd_bo *dst_bo = fd_resource(dst)->bo;
1287 unsigned i;
1288
1289 for (i = 0; i < sizedwords; i++) {
1290 OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
1291 OUT_RING(ring, 0x00000000);
1292 OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
1293 OUT_RELOC (ring, src_bo, src_off, 0, 0);
1294
1295 dst_off += 4;
1296 src_off += 4;
1297 }
1298 }
1299
1300 void
1301 fd6_emit_init(struct pipe_context *pctx)
1302 {
1303 struct fd_context *ctx = fd_context(pctx);
1304 ctx->emit_const = fd6_emit_const;
1305 ctx->emit_const_bo = fd6_emit_const_bo;
1306 ctx->emit_ib = fd6_emit_ib;
1307 ctx->mem_to_mem = fd6_mem_to_mem;
1308 }