2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_helpers.h"
32 #include "util/u_format.h"
33 #include "util/u_viewport.h"
35 #include "freedreno_resource.h"
36 #include "freedreno_query_hw.h"
39 #include "fd6_blend.h"
40 #include "fd6_context.h"
41 #include "fd6_image.h"
42 #include "fd6_program.h"
43 #include "fd6_rasterizer.h"
44 #include "fd6_texture.h"
45 #include "fd6_format.h"
49 shader_t_to_opcode(enum shader_t type
)
56 return CP_LOAD_STATE6_GEOM
;
59 return CP_LOAD_STATE6_FRAG
;
61 unreachable("bad shader type");
65 /* regid: base const register
66 * prsc or dwords: buffer containing constant values
67 * sizedwords: size of const value buffer
70 fd6_emit_const(struct fd_ringbuffer
*ring
, enum shader_t type
,
71 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
72 const uint32_t *dwords
, struct pipe_resource
*prsc
)
75 enum a6xx_state_src src
;
77 debug_assert((regid
% 4) == 0);
78 debug_assert((sizedwords
% 4) == 0);
88 OUT_PKT7(ring
, shader_t_to_opcode(type
), 3 + sz
);
89 OUT_RING(ring
, CP_LOAD_STATE6_0_DST_OFF(regid
/4) |
90 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
91 CP_LOAD_STATE6_0_STATE_SRC(src
) |
92 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type
)) |
93 CP_LOAD_STATE6_0_NUM_UNIT(sizedwords
/4));
95 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
96 OUT_RELOC(ring
, bo
, offset
, 0, 0);
98 OUT_RING(ring
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
99 OUT_RING(ring
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
100 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
102 for (i
= 0; i
< sz
; i
++) {
103 OUT_RING(ring
, dwords
[i
]);
108 fd6_emit_const_bo(struct fd_ringbuffer
*ring
, enum shader_t type
, boolean write
,
109 uint32_t regid
, uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
)
111 uint32_t anum
= align(num
, 2);
114 debug_assert((regid
% 4) == 0);
116 OUT_PKT7(ring
, shader_t_to_opcode(type
), 3 + (2 * anum
));
117 OUT_RING(ring
, CP_LOAD_STATE6_0_DST_OFF(regid
/4) |
118 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
)|
119 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
120 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type
)) |
121 CP_LOAD_STATE6_0_NUM_UNIT(anum
/2));
122 OUT_RING(ring
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
123 OUT_RING(ring
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
125 for (i
= 0; i
< num
; i
++) {
128 OUT_RELOCW(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
130 OUT_RELOC(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
133 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
134 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
138 for (; i
< anum
; i
++) {
139 OUT_RING(ring
, 0xffffffff);
140 OUT_RING(ring
, 0xffffffff);
144 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
145 * the same as a6xx then move this somewhere common ;-)
147 * Entry layout looks like (total size, 0x60 bytes):
150 struct PACKED bcolor_entry
{
162 uint32_t z24
; /* also s8? */
163 uint16_t srgb
[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
167 #define FD6_BORDER_COLOR_SIZE 0x60
168 #define FD6_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD6_BORDER_COLOR_SIZE)
171 setup_border_colors(struct fd_texture_stateobj
*tex
, struct bcolor_entry
*entries
)
174 STATIC_ASSERT(sizeof(struct bcolor_entry
) == FD6_BORDER_COLOR_SIZE
);
176 for (i
= 0; i
< tex
->num_samplers
; i
++) {
177 struct bcolor_entry
*e
= &entries
[i
];
178 struct pipe_sampler_state
*sampler
= tex
->samplers
[i
];
179 union pipe_color_union
*bc
;
184 bc
= &sampler
->border_color
;
189 * The border colors need to be swizzled in a particular
190 * format-dependent order. Even though samplers don't know about
191 * formats, we can assume that with a GL state tracker, there's a
192 * 1:1 correspondence between sampler and texture. Take advantage
195 if ((i
>= tex
->num_textures
) || !tex
->textures
[i
])
198 enum pipe_format format
= tex
->textures
[i
]->format
;
199 const struct util_format_description
*desc
=
200 util_format_description(format
);
208 for (j
= 0; j
< 4; j
++) {
209 int c
= desc
->swizzle
[j
];
213 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the
214 * stencil border color value in bc->ui[0] but according
215 * to desc->swizzle and desc->channel, the .x component
216 * is NONE and the stencil value is in the y component.
217 * Meanwhile the hardware wants this in the .x componetn.
219 if ((format
== PIPE_FORMAT_X24S8_UINT
) ||
220 (format
== PIPE_FORMAT_X32_S8X24_UINT
)) {
232 if (desc
->channel
[c
].pure_integer
) {
234 switch (desc
->channel
[c
].size
) {
236 assert(desc
->channel
[c
].type
== UTIL_FORMAT_TYPE_UNSIGNED
);
237 clamped
= CLAMP(bc
->ui
[j
], 0, 0x3);
240 if (desc
->channel
[c
].type
== UTIL_FORMAT_TYPE_SIGNED
)
241 clamped
= CLAMP(bc
->i
[j
], -128, 127);
243 clamped
= CLAMP(bc
->ui
[j
], 0, 255);
246 assert(desc
->channel
[c
].type
== UTIL_FORMAT_TYPE_UNSIGNED
);
247 clamped
= CLAMP(bc
->ui
[j
], 0, 0x3ff);
250 if (desc
->channel
[c
].type
== UTIL_FORMAT_TYPE_SIGNED
)
251 clamped
= CLAMP(bc
->i
[j
], -32768, 32767);
253 clamped
= CLAMP(bc
->ui
[j
], 0, 65535);
256 assert(!"Unexpected bit size");
261 e
->fp32
[cd
] = bc
->ui
[j
];
262 e
->fp16
[cd
] = clamped
;
265 float f_u
= CLAMP(f
, 0, 1);
266 float f_s
= CLAMP(f
, -1, 1);
269 e
->fp16
[c
] = util_float_to_half(f
);
270 e
->srgb
[c
] = util_float_to_half(f_u
);
271 e
->ui16
[c
] = f_u
* 0xffff;
272 e
->si16
[c
] = f_s
* 0x7fff;
273 e
->ui8
[c
] = f_u
* 0xff;
274 e
->si8
[c
] = f_s
* 0x7f;
276 e
->rgb565
|= (int)(f_u
* 0x3f) << 5;
278 e
->rgb565
|= (int)(f_u
* 0x1f) << (c
? 11 : 0);
280 e
->rgb5a1
|= (f_u
> 0.5) ? 0x8000 : 0;
282 e
->rgb5a1
|= (int)(f_u
* 0x1f) << (c
* 5);
284 e
->rgb10a2
|= (int)(f_u
* 0x3) << 30;
286 e
->rgb10a2
|= (int)(f_u
* 0x3ff) << (c
* 10);
287 e
->rgba4
|= (int)(f_u
* 0xf) << (c
* 4);
289 e
->z24
= f_u
* 0xffffff;
294 memset(&e
->__pad0
, 0, sizeof(e
->__pad0
));
295 memset(&e
->__pad1
, 0, sizeof(e
->__pad1
));
301 emit_border_color(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
)
303 struct fd6_context
*fd6_ctx
= fd6_context(ctx
);
304 struct bcolor_entry
*entries
;
308 STATIC_ASSERT(sizeof(struct bcolor_entry
) == FD6_BORDER_COLOR_SIZE
);
310 u_upload_alloc(fd6_ctx
->border_color_uploader
,
311 0, FD6_BORDER_COLOR_UPLOAD_SIZE
,
312 FD6_BORDER_COLOR_UPLOAD_SIZE
, &off
,
313 &fd6_ctx
->border_color_buf
,
318 setup_border_colors(&ctx
->tex
[PIPE_SHADER_VERTEX
], &entries
[0]);
319 setup_border_colors(&ctx
->tex
[PIPE_SHADER_FRAGMENT
],
320 &entries
[ctx
->tex
[PIPE_SHADER_VERTEX
].num_samplers
]);
322 OUT_PKT4(ring
, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO
, 2);
323 OUT_RELOC(ring
, fd_resource(fd6_ctx
->border_color_buf
)->bo
, off
, 0, 0);
325 u_upload_unmap(fd6_ctx
->border_color_uploader
);
329 fd6_emit_textures(struct fd_pipe
*pipe
, struct fd_ringbuffer
*ring
,
330 enum a6xx_state_block sb
, struct fd_texture_stateobj
*tex
,
331 unsigned bcolor_offset
)
333 bool needs_border
= false;
334 unsigned opcode
, tex_samp_reg
, tex_const_reg
, tex_count_reg
;
338 opcode
= CP_LOAD_STATE6_GEOM
;
339 tex_samp_reg
= REG_A6XX_SP_VS_TEX_SAMP_LO
;
340 tex_const_reg
= REG_A6XX_SP_VS_TEX_CONST_LO
;
341 tex_count_reg
= REG_A6XX_SP_VS_TEX_COUNT
;
344 opcode
= CP_LOAD_STATE6_FRAG
;
345 tex_samp_reg
= REG_A6XX_SP_FS_TEX_SAMP_LO
;
346 tex_const_reg
= REG_A6XX_SP_FS_TEX_CONST_LO
;
347 tex_count_reg
= REG_A6XX_SP_FS_TEX_COUNT
;
350 opcode
= CP_LOAD_STATE6_FRAG
;
351 tex_samp_reg
= REG_A6XX_SP_CS_TEX_SAMP_LO
;
352 tex_const_reg
= REG_A6XX_SP_CS_TEX_CONST_LO
;
353 tex_count_reg
= 0; //REG_A6XX_SP_CS_TEX_COUNT;
356 unreachable("bad state block");
360 if (tex
->num_samplers
> 0) {
361 struct fd_ringbuffer
*state
=
362 fd_ringbuffer_new_object(pipe
, tex
->num_samplers
* 4 * 4);
363 for (unsigned i
= 0; i
< tex
->num_samplers
; i
++) {
364 static const struct fd6_sampler_stateobj dummy_sampler
= {};
365 const struct fd6_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
366 fd6_sampler_stateobj(tex
->samplers
[i
]) : &dummy_sampler
;
367 OUT_RING(state
, sampler
->texsamp0
);
368 OUT_RING(state
, sampler
->texsamp1
);
369 OUT_RING(state
, sampler
->texsamp2
|
370 A6XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset
));
371 OUT_RING(state
, sampler
->texsamp3
);
372 needs_border
|= sampler
->needs_border
;
375 /* output sampler state: */
376 OUT_PKT7(ring
, opcode
, 3);
377 OUT_RING(ring
, CP_LOAD_STATE6_0_DST_OFF(0) |
378 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
379 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
380 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
381 CP_LOAD_STATE6_0_NUM_UNIT(tex
->num_samplers
));
382 OUT_RB(ring
, state
); /* SRC_ADDR_LO/HI */
384 OUT_PKT4(ring
, tex_samp_reg
, 2);
385 OUT_RB(ring
, state
); /* SRC_ADDR_LO/HI */
387 fd_ringbuffer_del(state
);
390 if (tex
->num_textures
> 0) {
391 struct fd_ringbuffer
*state
=
392 fd_ringbuffer_new_object(pipe
, tex
->num_textures
* 16 * 4);
393 for (unsigned i
= 0; i
< tex
->num_textures
; i
++) {
394 static const struct fd6_pipe_sampler_view dummy_view
= {};
395 const struct fd6_pipe_sampler_view
*view
= tex
->textures
[i
] ?
396 fd6_pipe_sampler_view(tex
->textures
[i
]) : &dummy_view
;
397 enum a6xx_tile_mode tile_mode
= TILE6_LINEAR
;
399 if (view
->base
.texture
)
400 tile_mode
= fd_resource(view
->base
.texture
)->tile_mode
;
402 OUT_RING(state
, view
->texconst0
|
403 A6XX_TEX_CONST_0_TILE_MODE(tile_mode
));
404 OUT_RING(state
, view
->texconst1
);
405 OUT_RING(state
, view
->texconst2
);
406 OUT_RING(state
, view
->texconst3
);
408 if (view
->base
.texture
) {
409 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
410 if (view
->base
.format
== PIPE_FORMAT_X32_S8X24_UINT
)
412 OUT_RELOC(state
, rsc
->bo
, view
->offset
,
413 (uint64_t)view
->texconst5
<< 32, 0);
415 OUT_RING(state
, 0x00000000);
416 OUT_RING(state
, view
->texconst5
);
419 OUT_RING(state
, view
->texconst6
);
420 OUT_RING(state
, view
->texconst7
);
421 OUT_RING(state
, view
->texconst8
);
422 OUT_RING(state
, view
->texconst9
);
423 OUT_RING(state
, view
->texconst10
);
424 OUT_RING(state
, view
->texconst11
);
431 /* emit texture state: */
432 OUT_PKT7(ring
, opcode
, 3);
433 OUT_RING(ring
, CP_LOAD_STATE6_0_DST_OFF(0) |
434 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
435 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
436 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
437 CP_LOAD_STATE6_0_NUM_UNIT(tex
->num_textures
));
438 OUT_RB(ring
, state
); /* SRC_ADDR_LO/HI */
440 OUT_PKT4(ring
, tex_const_reg
, 2);
441 OUT_RB(ring
, state
); /* SRC_ADDR_LO/HI */
443 fd_ringbuffer_del(state
);
447 OUT_PKT4(ring
, tex_count_reg
, 1);
448 OUT_RING(ring
, tex
->num_textures
);
455 emit_ssbos(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
456 enum a6xx_state_block sb
, struct fd_shaderbuf_stateobj
*so
)
458 unsigned count
= util_last_bit(so
->enabled_mask
);
467 opcode
= CP_LOAD_STATE6_GEOM
;
470 unreachable("bad state block");
473 OUT_PKT7(ring
, opcode
, 3 + (4 * count
));
474 OUT_RING(ring
, CP_LOAD_STATE6_0_DST_OFF(0) |
475 CP_LOAD_STATE6_0_STATE_TYPE(0) |
476 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
477 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
478 CP_LOAD_STATE6_0_NUM_UNIT(count
));
479 OUT_RING(ring
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
480 OUT_RING(ring
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
481 for (unsigned i
= 0; i
< count
; i
++) {
482 OUT_RING(ring
, 0x00000000);
483 OUT_RING(ring
, 0x00000000);
484 OUT_RING(ring
, 0x00000000);
485 OUT_RING(ring
, 0x00000000);
489 OUT_PKT7(ring
, opcode
, 3 + (2 * count
));
490 OUT_RING(ring
, CP_LOAD_STATE6_0_DST_OFF(0) |
491 CP_LOAD_STATE6_0_STATE_TYPE(1) |
492 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
493 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
494 CP_LOAD_STATE6_0_NUM_UNIT(count
));
495 OUT_RING(ring
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
496 OUT_RING(ring
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
497 for (unsigned i
= 0; i
< count
; i
++) {
498 struct pipe_shader_buffer
*buf
= &so
->sb
[i
];
499 unsigned sz
= buf
->buffer_size
;
501 /* width is in dwords, overflows into height: */
504 OUT_RING(ring
, A6XX_SSBO_1_0_WIDTH(sz
));
505 OUT_RING(ring
, A6XX_SSBO_1_1_HEIGHT(sz
>> 16));
509 OUT_PKT7(ring
, opcode
, 3 + (2 * count
));
510 OUT_RING(ring
, CP_LOAD_STATE6_0_DST_OFF(0) |
511 CP_LOAD_STATE6_0_STATE_TYPE(2) |
512 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
513 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
514 CP_LOAD_STATE6_0_NUM_UNIT(count
));
515 OUT_RING(ring
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
516 OUT_RING(ring
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
517 for (unsigned i
= 0; i
< count
; i
++) {
518 struct pipe_shader_buffer
*buf
= &so
->sb
[i
];
520 struct fd_resource
*rsc
= fd_resource(buf
->buffer
);
521 OUT_RELOCW(ring
, rsc
->bo
, buf
->buffer_offset
, 0, 0);
523 OUT_RING(ring
, 0x00000000);
524 OUT_RING(ring
, 0x00000000);
529 struct fd_ringbuffer
*
530 fd6_build_vbo_state(struct fd6_emit
*emit
, const struct ir3_shader_variant
*vp
)
532 const struct fd_vertex_state
*vtx
= emit
->vtx
;
535 struct fd_ringbuffer
*ring
= fd_submit_new_ringbuffer(emit
->ctx
->batch
->submit
,
536 4 * (10 * vp
->inputs_count
+ 2), FD_RINGBUFFER_STREAMING
);
538 for (i
= 0, j
= 0; i
<= vp
->inputs_count
; i
++) {
539 if (vp
->inputs
[i
].sysval
)
541 if (vp
->inputs
[i
].compmask
) {
542 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
543 const struct pipe_vertex_buffer
*vb
=
544 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
545 struct fd_resource
*rsc
= fd_resource(vb
->buffer
.resource
);
546 enum pipe_format pfmt
= elem
->src_format
;
547 enum a6xx_vtx_fmt fmt
= fd6_pipe2vtx(pfmt
);
548 bool isint
= util_format_is_pure_integer(pfmt
);
549 uint32_t off
= vb
->buffer_offset
+ elem
->src_offset
;
550 uint32_t size
= fd_bo_size(rsc
->bo
) - off
;
551 debug_assert(fmt
!= ~0);
554 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
556 if (off
> fd_bo_size(rsc
->bo
))
560 OUT_PKT4(ring
, REG_A6XX_VFD_FETCH(j
), 4);
561 OUT_RELOC(ring
, rsc
->bo
, off
, 0, 0);
562 OUT_RING(ring
, size
); /* VFD_FETCH[j].SIZE */
563 OUT_RING(ring
, vb
->stride
); /* VFD_FETCH[j].STRIDE */
565 OUT_PKT4(ring
, REG_A6XX_VFD_DECODE(j
), 2);
566 OUT_RING(ring
, A6XX_VFD_DECODE_INSTR_IDX(j
) |
567 A6XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
568 COND(elem
->instance_divisor
, A6XX_VFD_DECODE_INSTR_INSTANCED
) |
569 A6XX_VFD_DECODE_INSTR_SWAP(fd6_pipe2swap(pfmt
)) |
570 A6XX_VFD_DECODE_INSTR_UNK30
|
571 COND(!isint
, A6XX_VFD_DECODE_INSTR_FLOAT
));
572 OUT_RING(ring
, MAX2(1, elem
->instance_divisor
)); /* VFD_DECODE[j].STEP_RATE */
574 OUT_PKT4(ring
, REG_A6XX_VFD_DEST_CNTL(j
), 1);
575 OUT_RING(ring
, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
576 A6XX_VFD_DEST_CNTL_INSTR_REGID(vp
->inputs
[i
].regid
));
582 OUT_PKT4(ring
, REG_A6XX_VFD_CONTROL_0
, 1);
583 OUT_RING(ring
, A6XX_VFD_CONTROL_0_VTXCNT(j
) | (j
<< 8));
588 static struct fd_ringbuffer
*
589 build_lrz(struct fd6_emit
*emit
, bool binning_pass
)
591 struct fd6_zsa_stateobj
*zsa
= fd6_zsa_stateobj(emit
->ctx
->zsa
);
592 struct pipe_framebuffer_state
*pfb
= &emit
->ctx
->batch
->framebuffer
;
593 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
594 uint32_t gras_lrz_cntl
= zsa
->gras_lrz_cntl
;
595 uint32_t rb_lrz_cntl
= zsa
->rb_lrz_cntl
;
597 struct fd_ringbuffer
*ring
= fd_submit_new_ringbuffer(emit
->ctx
->batch
->submit
,
598 16, FD_RINGBUFFER_STREAMING
);
600 if (emit
->no_lrz_write
|| !rsc
->lrz
|| !rsc
->lrz_valid
) {
603 } else if (binning_pass
&& zsa
->lrz_write
) {
604 gras_lrz_cntl
|= A6XX_GRAS_LRZ_CNTL_LRZ_WRITE
;
607 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_CNTL
, 1);
608 OUT_RING(ring
, gras_lrz_cntl
);
610 OUT_PKT4(ring
, REG_A6XX_RB_LRZ_CNTL
, 1);
611 OUT_RING(ring
, rb_lrz_cntl
);
617 fd6_emit_state(struct fd_ringbuffer
*ring
, struct fd6_emit
*emit
)
619 struct fd_context
*ctx
= emit
->ctx
;
620 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
621 const struct fd6_program_state
*prog
= fd6_emit_get_prog(emit
);
622 const struct ir3_shader_variant
*vp
= emit
->vs
;
623 const struct ir3_shader_variant
*fp
= emit
->fs
;
624 const enum fd_dirty_3d_state dirty
= emit
->dirty
;
625 bool needs_border
= false;
627 emit_marker6(ring
, 5);
629 if (dirty
& FD_DIRTY_ZSA
) {
630 struct fd6_zsa_stateobj
*zsa
= fd6_zsa_stateobj(ctx
->zsa
);
632 if (util_format_is_pure_integer(pipe_surface_format(pfb
->cbufs
[0])))
633 fd6_emit_add_group(emit
, zsa
->stateobj_no_alpha
, FD6_GROUP_ZSA
, 0x7);
635 fd6_emit_add_group(emit
, zsa
->stateobj
, FD6_GROUP_ZSA
, 0x7);
638 if ((dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_PROG
)) && pfb
->zsbuf
) {
639 struct fd_ringbuffer
*state
;
641 state
= build_lrz(emit
, false);
642 fd6_emit_add_group(emit
, state
, FD6_GROUP_LRZ
, 0x6);
643 fd_ringbuffer_del(state
);
645 state
= build_lrz(emit
, true);
646 fd6_emit_add_group(emit
, state
, FD6_GROUP_LRZ_BINNING
, 0x1);
647 fd_ringbuffer_del(state
);
650 if (dirty
& FD_DIRTY_STENCIL_REF
) {
651 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
653 OUT_PKT4(ring
, REG_A6XX_RB_STENCILREF
, 1);
654 OUT_RING(ring
, A6XX_RB_STENCILREF_REF(sr
->ref_value
[0]) |
655 A6XX_RB_STENCILREF_BFREF(sr
->ref_value
[1]));
658 /* NOTE: scissor enabled bit is part of rasterizer state: */
659 if (dirty
& (FD_DIRTY_SCISSOR
| FD_DIRTY_RASTERIZER
)) {
660 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
662 OUT_PKT4(ring
, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0
, 2);
663 OUT_RING(ring
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor
->minx
) |
664 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor
->miny
));
665 OUT_RING(ring
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor
->maxx
- 1) |
666 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor
->maxy
- 1));
668 OUT_PKT4(ring
, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0
, 2);
669 OUT_RING(ring
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor
->minx
) |
670 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor
->miny
));
671 OUT_RING(ring
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor
->maxx
- 1) |
672 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor
->maxy
- 1));
674 ctx
->batch
->max_scissor
.minx
= MIN2(ctx
->batch
->max_scissor
.minx
, scissor
->minx
);
675 ctx
->batch
->max_scissor
.miny
= MIN2(ctx
->batch
->max_scissor
.miny
, scissor
->miny
);
676 ctx
->batch
->max_scissor
.maxx
= MAX2(ctx
->batch
->max_scissor
.maxx
, scissor
->maxx
);
677 ctx
->batch
->max_scissor
.maxy
= MAX2(ctx
->batch
->max_scissor
.maxy
, scissor
->maxy
);
680 if (dirty
& FD_DIRTY_VIEWPORT
) {
681 fd_wfi(ctx
->batch
, ring
);
682 OUT_PKT4(ring
, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
683 OUT_RING(ring
, A6XX_GRAS_CL_VPORT_XOFFSET_0(ctx
->viewport
.translate
[0]));
684 OUT_RING(ring
, A6XX_GRAS_CL_VPORT_XSCALE_0(ctx
->viewport
.scale
[0]));
685 OUT_RING(ring
, A6XX_GRAS_CL_VPORT_YOFFSET_0(ctx
->viewport
.translate
[1]));
686 OUT_RING(ring
, A6XX_GRAS_CL_VPORT_YSCALE_0(ctx
->viewport
.scale
[1]));
687 OUT_RING(ring
, A6XX_GRAS_CL_VPORT_ZOFFSET_0(ctx
->viewport
.translate
[2]));
688 OUT_RING(ring
, A6XX_GRAS_CL_VPORT_ZSCALE_0(ctx
->viewport
.scale
[2]));
691 if (dirty
& FD_DIRTY_PROG
) {
692 fd6_emit_add_group(emit
, prog
->stateobj
, FD6_GROUP_PROG
, 0x6);
693 fd6_emit_add_group(emit
, prog
->binning_stateobj
,
694 FD6_GROUP_PROG_BINNING
, 0x1);
696 /* emit remaining non-stateobj program state, ie. what depends
697 * on other emit state, so cannot be pre-baked. This could
698 * be moved to a separate stateobj which is dynamically
701 fd6_program_emit(ring
, emit
);
704 if (dirty
& FD_DIRTY_RASTERIZER
) {
705 struct fd6_rasterizer_stateobj
*rasterizer
=
706 fd6_rasterizer_stateobj(ctx
->rasterizer
);
707 fd6_emit_add_group(emit
, rasterizer
->stateobj
,
708 FD6_GROUP_RASTERIZER
, 0x7);
711 /* Since the primitive restart state is not part of a tracked object, we
712 * re-emit this register every time.
714 if (emit
->info
&& ctx
->rasterizer
) {
715 struct fd6_rasterizer_stateobj
*rasterizer
=
716 fd6_rasterizer_stateobj(ctx
->rasterizer
);
717 OUT_PKT4(ring
, REG_A6XX_PC_UNKNOWN_9806
, 1);
719 OUT_PKT4(ring
, REG_A6XX_PC_UNKNOWN_9990
, 1);
721 OUT_PKT4(ring
, REG_A6XX_VFD_UNKNOWN_A008
, 1);
725 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_0
, 1);
726 OUT_RING(ring
, rasterizer
->pc_primitive_cntl
|
727 COND(emit
->info
->primitive_restart
&& emit
->info
->index_size
,
728 A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART
));
731 if (dirty
& (FD_DIRTY_FRAMEBUFFER
| FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
732 unsigned nr
= pfb
->nr_cbufs
;
734 if (ctx
->rasterizer
->rasterizer_discard
)
737 OUT_PKT4(ring
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 2);
738 OUT_RING(ring
, COND(fp
->writes_pos
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z
));
739 OUT_RING(ring
, A6XX_RB_FS_OUTPUT_CNTL1_MRT(nr
));
741 OUT_PKT4(ring
, REG_A6XX_SP_FS_OUTPUT_CNTL1
, 1);
742 OUT_RING(ring
, A6XX_SP_FS_OUTPUT_CNTL1_MRT(nr
));
745 #define DIRTY_CONST (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST | \
746 FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)
748 if (ctx
->dirty_shader
[PIPE_SHADER_VERTEX
] & DIRTY_CONST
) {
749 struct fd_ringbuffer
*vsconstobj
= fd_submit_new_ringbuffer(
750 ctx
->batch
->submit
, 0x1000, FD_RINGBUFFER_STREAMING
);
752 ir3_emit_vs_consts(vp
, vsconstobj
, ctx
, emit
->info
);
753 fd6_emit_add_group(emit
, vsconstobj
, FD6_GROUP_VS_CONST
, 0x7);
754 fd_ringbuffer_del(vsconstobj
);
757 if (ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] & DIRTY_CONST
) {
758 struct fd_ringbuffer
*fsconstobj
= fd_submit_new_ringbuffer(
759 ctx
->batch
->submit
, 0x1000, FD_RINGBUFFER_STREAMING
);
761 ir3_emit_fs_consts(fp
, fsconstobj
, ctx
);
762 fd6_emit_add_group(emit
, fsconstobj
, FD6_GROUP_FS_CONST
, 0x6);
763 fd_ringbuffer_del(fsconstobj
);
766 struct pipe_stream_output_info
*info
= &vp
->shader
->stream_output
;
767 if (info
->num_outputs
) {
768 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
770 emit
->streamout_mask
= 0;
772 for (unsigned i
= 0; i
< so
->num_targets
; i
++) {
773 struct pipe_stream_output_target
*target
= so
->targets
[i
];
778 unsigned offset
= (so
->offsets
[i
] * info
->stride
[i
] * 4) +
779 target
->buffer_offset
;
781 OUT_PKT4(ring
, REG_A6XX_VPC_SO_BUFFER_BASE_LO(i
), 3);
782 /* VPC_SO[i].BUFFER_BASE_LO: */
783 OUT_RELOCW(ring
, fd_resource(target
->buffer
)->bo
, 0, 0, 0);
784 OUT_RING(ring
, target
->buffer_size
+ offset
);
786 OUT_PKT4(ring
, REG_A6XX_VPC_SO_BUFFER_OFFSET(i
), 3);
787 OUT_RING(ring
, offset
);
788 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
789 // TODO just give hw a dummy addr for now.. we should
790 // be using this an then CP_MEM_TO_REG to set the
791 // VPC_SO[i].BUFFER_OFFSET for the next draw..
792 OUT_RELOCW(ring
, fd6_context(ctx
)->blit_mem
, 0x100, 0, 0);
794 emit
->streamout_mask
|= (1 << i
);
797 if (emit
->streamout_mask
) {
798 const struct fd6_streamout_state
*tf
= &prog
->tf
;
800 OUT_PKT7(ring
, CP_CONTEXT_REG_BUNCH
, 12 + (2 * tf
->prog_count
));
801 OUT_RING(ring
, REG_A6XX_VPC_SO_BUF_CNTL
);
802 OUT_RING(ring
, tf
->vpc_so_buf_cntl
);
803 OUT_RING(ring
, REG_A6XX_VPC_SO_NCOMP(0));
804 OUT_RING(ring
, tf
->ncomp
[0]);
805 OUT_RING(ring
, REG_A6XX_VPC_SO_NCOMP(1));
806 OUT_RING(ring
, tf
->ncomp
[1]);
807 OUT_RING(ring
, REG_A6XX_VPC_SO_NCOMP(2));
808 OUT_RING(ring
, tf
->ncomp
[2]);
809 OUT_RING(ring
, REG_A6XX_VPC_SO_NCOMP(3));
810 OUT_RING(ring
, tf
->ncomp
[3]);
811 OUT_RING(ring
, REG_A6XX_VPC_SO_CNTL
);
812 OUT_RING(ring
, A6XX_VPC_SO_CNTL_ENABLE
);
813 for (unsigned i
= 0; i
< tf
->prog_count
; i
++) {
814 OUT_RING(ring
, REG_A6XX_VPC_SO_PROG
);
815 OUT_RING(ring
, tf
->prog
[i
]);
818 OUT_PKT4(ring
, REG_A6XX_VPC_SO_OVERRIDE
, 1);
821 OUT_PKT7(ring
, CP_CONTEXT_REG_BUNCH
, 4);
822 OUT_RING(ring
, REG_A6XX_VPC_SO_CNTL
);
824 OUT_RING(ring
, REG_A6XX_VPC_SO_BUF_CNTL
);
827 OUT_PKT4(ring
, REG_A6XX_VPC_SO_OVERRIDE
, 1);
828 OUT_RING(ring
, A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
832 if ((dirty
& FD_DIRTY_BLEND
)) {
833 struct fd6_blend_stateobj
*blend
= fd6_blend_stateobj(ctx
->blend
);
836 for (i
= 0; i
< A6XX_MAX_RENDER_TARGETS
; i
++) {
837 enum pipe_format format
= pipe_surface_format(pfb
->cbufs
[i
]);
838 bool is_int
= util_format_is_pure_integer(format
);
839 bool has_alpha
= util_format_has_alpha(format
);
840 uint32_t control
= blend
->rb_mrt
[i
].control
;
841 uint32_t blend_control
= blend
->rb_mrt
[i
].blend_control_alpha
;
844 control
&= A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
845 control
|= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
849 blend_control
|= blend
->rb_mrt
[i
].blend_control_rgb
;
851 blend_control
|= blend
->rb_mrt
[i
].blend_control_no_alpha_rgb
;
852 control
&= ~A6XX_RB_MRT_CONTROL_BLEND2
;
855 OUT_PKT4(ring
, REG_A6XX_RB_MRT_CONTROL(i
), 1);
856 OUT_RING(ring
, control
);
858 OUT_PKT4(ring
, REG_A6XX_RB_MRT_BLEND_CONTROL(i
), 1);
859 OUT_RING(ring
, blend_control
);
862 OUT_PKT4(ring
, REG_A6XX_RB_BLEND_CNTL
, 1);
863 OUT_RING(ring
, blend
->rb_blend_cntl
|
864 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(0xffff));
866 OUT_PKT4(ring
, REG_A6XX_SP_BLEND_CNTL
, 1);
867 OUT_RING(ring
, blend
->sp_blend_cntl
);
870 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
871 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
873 OUT_PKT4(ring
, REG_A6XX_RB_BLEND_RED_F32
, 4);
874 OUT_RING(ring
, A6XX_RB_BLEND_RED_F32(bcolor
->color
[0]));
875 OUT_RING(ring
, A6XX_RB_BLEND_GREEN_F32(bcolor
->color
[1]));
876 OUT_RING(ring
, A6XX_RB_BLEND_BLUE_F32(bcolor
->color
[2]));
877 OUT_RING(ring
, A6XX_RB_BLEND_ALPHA_F32(bcolor
->color
[3]));
880 if ((ctx
->dirty_shader
[PIPE_SHADER_VERTEX
] & FD_DIRTY_SHADER_TEX
) &&
881 ctx
->tex
[PIPE_SHADER_VERTEX
].num_textures
> 0) {
882 struct fd6_texture_state
*tex
= fd6_texture_state(ctx
,
883 SB6_VS_TEX
, &ctx
->tex
[PIPE_SHADER_VERTEX
]);
885 needs_border
|= tex
->needs_border
;
887 fd6_emit_add_group(emit
, tex
->stateobj
, FD6_GROUP_VS_TEX
, 0x7);
890 if ((ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] & FD_DIRTY_SHADER_TEX
) &&
891 ctx
->tex
[PIPE_SHADER_FRAGMENT
].num_textures
> 0) {
892 struct fd6_texture_state
*tex
= fd6_texture_state(ctx
,
893 SB6_FS_TEX
, &ctx
->tex
[PIPE_SHADER_FRAGMENT
]);
895 needs_border
|= tex
->needs_border
;
897 fd6_emit_add_group(emit
, tex
->stateobj
, FD6_GROUP_FS_TEX
, 0x7);
901 emit_border_color(ctx
, ring
);
903 if (ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] & FD_DIRTY_SHADER_SSBO
)
904 emit_ssbos(ctx
, ring
, SB6_SSBO
, &ctx
->shaderbuf
[PIPE_SHADER_FRAGMENT
]);
906 if (ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] & FD_DIRTY_SHADER_IMAGE
)
907 fd6_emit_images(ctx
, ring
, PIPE_SHADER_FRAGMENT
);
909 if (emit
->num_groups
> 0) {
910 OUT_PKT7(ring
, CP_SET_DRAW_STATE
, 3 * emit
->num_groups
);
911 for (unsigned i
= 0; i
< emit
->num_groups
; i
++) {
912 struct fd6_state_group
*g
= &emit
->groups
[i
];
913 unsigned n
= fd_ringbuffer_size(g
->stateobj
) / 4;
916 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
917 CP_SET_DRAW_STATE__0_DISABLE
|
918 CP_SET_DRAW_STATE__0_ENABLE_MASK(g
->enable_mask
) |
919 CP_SET_DRAW_STATE__0_GROUP_ID(g
->group_id
));
920 OUT_RING(ring
, 0x00000000);
921 OUT_RING(ring
, 0x00000000);
923 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(n
) |
924 CP_SET_DRAW_STATE__0_ENABLE_MASK(g
->enable_mask
) |
925 CP_SET_DRAW_STATE__0_GROUP_ID(g
->group_id
));
926 OUT_RB(ring
, g
->stateobj
);
929 fd_ringbuffer_del(g
->stateobj
);
931 emit
->num_groups
= 0;
936 fd6_emit_cs_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
937 struct ir3_shader_variant
*cp
)
939 enum fd_dirty_shader_state dirty
= ctx
->dirty_shader
[PIPE_SHADER_COMPUTE
];
941 if (dirty
& FD_DIRTY_SHADER_TEX
) {
942 bool needs_border
= false;
943 needs_border
|= fd6_emit_textures(ctx
->pipe
, ring
, SB6_CS_TEX
,
944 &ctx
->tex
[PIPE_SHADER_COMPUTE
], 0);
947 emit_border_color(ctx
, ring
);
950 OUT_PKT4(ring
, REG_A6XX_TPL1_VS_TEX_COUNT
, 1);
953 OUT_PKT4(ring
, REG_A6XX_TPL1_HS_TEX_COUNT
, 1);
956 OUT_PKT4(ring
, REG_A6XX_TPL1_DS_TEX_COUNT
, 1);
959 OUT_PKT4(ring
, REG_A6XX_TPL1_GS_TEX_COUNT
, 1);
962 OUT_PKT4(ring
, REG_A6XX_TPL1_FS_TEX_COUNT
, 1);
968 OUT_PKT4(ring
, REG_A6XX_TPL1_CS_TEX_COUNT
, 1);
969 OUT_RING(ring
, ctx
->shaderimg
[PIPE_SHADER_COMPUTE
].enabled_mask
?
970 ~0 : ctx
->tex
[PIPE_SHADER_COMPUTE
].num_textures
);
973 if (dirty
& FD_DIRTY_SHADER_SSBO
)
974 emit_ssbos(ctx
, ring
, SB6_CS_SSBO
, &ctx
->shaderbuf
[PIPE_SHADER_COMPUTE
]);
976 if (dirty
& FD_DIRTY_SHADER_IMAGE
)
977 fd6_emit_images(ctx
, ring
, PIPE_SHADER_COMPUTE
);
981 /* emit setup at begin of new cmdstream buffer (don't rely on previous
982 * state, there could have been a context switch between ioctls):
985 fd6_emit_restore(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
987 //struct fd_context *ctx = batch->ctx;
989 fd6_cache_flush(batch
, ring
);
991 OUT_PKT4(ring
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
992 OUT_RING(ring
, 0xfffff);
995 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
996 0000000500024048: 70d08003 00000000 001c5000 00000005
997 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
998 0000000500024058: 70d08003 00000010 001c7000 00000005
1000 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
1001 0000000500024068: 70268000
1004 WRITE(REG_A6XX_RB_CCU_CNTL
, 0x7c400004);
1005 WRITE(REG_A6XX_RB_UNKNOWN_8E04
, 0x00100000);
1006 WRITE(REG_A6XX_SP_UNKNOWN_AE04
, 0x8);
1007 WRITE(REG_A6XX_SP_UNKNOWN_AE00
, 0);
1008 WRITE(REG_A6XX_SP_UNKNOWN_AE0F
, 0x3f);
1009 WRITE(REG_A6XX_SP_UNKNOWN_B605
, 0x44);
1010 WRITE(REG_A6XX_SP_UNKNOWN_B600
, 0x100000);
1011 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE00
, 0x80);
1012 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE01
, 0);
1014 WRITE(REG_A6XX_VPC_UNKNOWN_9600
, 0);
1015 WRITE(REG_A6XX_GRAS_UNKNOWN_8600
, 0x880);
1016 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE04
, 0);
1017 WRITE(REG_A6XX_SP_UNKNOWN_AE03
, 0x00000410);
1018 WRITE(REG_A6XX_SP_UNKNOWN_AB20
, 0);
1019 WRITE(REG_A6XX_SP_UNKNOWN_B182
, 0);
1020 WRITE(REG_A6XX_HLSQ_UNKNOWN_BB11
, 0);
1021 WRITE(REG_A6XX_UCHE_UNKNOWN_0E12
, 0x3200000);
1022 WRITE(REG_A6XX_UCHE_CLIENT_PF
, 4);
1023 WRITE(REG_A6XX_RB_UNKNOWN_8E01
, 0x0);
1024 WRITE(REG_A6XX_SP_UNKNOWN_AB00
, 0x5);
1025 WRITE(REG_A6XX_VFD_UNKNOWN_A009
, 0x00000001);
1026 WRITE(REG_A6XX_RB_UNKNOWN_8811
, 0x00000010);
1027 WRITE(REG_A6XX_PC_MODE_CNTL
, 0x1f);
1029 OUT_PKT4(ring
, REG_A6XX_RB_SRGB_CNTL
, 1);
1032 WRITE(REG_A6XX_GRAS_UNKNOWN_8101
, 0);
1033 WRITE(REG_A6XX_GRAS_UNKNOWN_8109
, 0);
1034 WRITE(REG_A6XX_GRAS_UNKNOWN_8110
, 0);
1036 WRITE(REG_A6XX_RB_RENDER_CONTROL0
, 0x401);
1037 WRITE(REG_A6XX_RB_RENDER_CONTROL1
, 0);
1038 WRITE(REG_A6XX_RB_FS_OUTPUT_CNTL0
, 0);
1039 WRITE(REG_A6XX_RB_UNKNOWN_8810
, 0);
1040 WRITE(REG_A6XX_RB_UNKNOWN_8818
, 0);
1041 WRITE(REG_A6XX_RB_UNKNOWN_8819
, 0);
1042 WRITE(REG_A6XX_RB_UNKNOWN_881A
, 0);
1043 WRITE(REG_A6XX_RB_UNKNOWN_881B
, 0);
1044 WRITE(REG_A6XX_RB_UNKNOWN_881C
, 0);
1045 WRITE(REG_A6XX_RB_UNKNOWN_881D
, 0);
1046 WRITE(REG_A6XX_RB_UNKNOWN_881E
, 0);
1047 WRITE(REG_A6XX_RB_UNKNOWN_88F0
, 0);
1049 WRITE(REG_A6XX_VPC_UNKNOWN_9101
, 0xffff00);
1050 WRITE(REG_A6XX_VPC_UNKNOWN_9107
, 0);
1052 WRITE(REG_A6XX_VPC_UNKNOWN_9236
, 1);
1053 WRITE(REG_A6XX_VPC_UNKNOWN_9300
, 0);
1055 WRITE(REG_A6XX_VPC_SO_OVERRIDE
, A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
1057 WRITE(REG_A6XX_PC_UNKNOWN_9801
, 0);
1058 WRITE(REG_A6XX_PC_UNKNOWN_9806
, 0);
1059 WRITE(REG_A6XX_PC_UNKNOWN_9980
, 0);
1061 WRITE(REG_A6XX_PC_UNKNOWN_9B06
, 0);
1062 WRITE(REG_A6XX_PC_UNKNOWN_9B06
, 0);
1064 WRITE(REG_A6XX_SP_UNKNOWN_A81B
, 0);
1066 WRITE(REG_A6XX_SP_UNKNOWN_B183
, 0);
1068 WRITE(REG_A6XX_GRAS_UNKNOWN_8099
, 0);
1069 WRITE(REG_A6XX_GRAS_UNKNOWN_809B
, 0);
1070 WRITE(REG_A6XX_GRAS_UNKNOWN_80A0
, 2);
1071 WRITE(REG_A6XX_GRAS_UNKNOWN_80AF
, 0);
1072 WRITE(REG_A6XX_VPC_UNKNOWN_9210
, 0);
1073 WRITE(REG_A6XX_VPC_UNKNOWN_9211
, 0);
1074 WRITE(REG_A6XX_VPC_UNKNOWN_9602
, 0);
1075 WRITE(REG_A6XX_PC_UNKNOWN_9981
, 0x3);
1076 WRITE(REG_A6XX_PC_UNKNOWN_9E72
, 0);
1077 WRITE(REG_A6XX_VPC_UNKNOWN_9108
, 0x3);
1078 WRITE(REG_A6XX_SP_TP_UNKNOWN_B304
, 0);
1079 WRITE(REG_A6XX_SP_TP_UNKNOWN_B309
, 0x000000a2);
1080 WRITE(REG_A6XX_RB_UNKNOWN_8804
, 0);
1081 WRITE(REG_A6XX_GRAS_UNKNOWN_80A4
, 0);
1082 WRITE(REG_A6XX_GRAS_UNKNOWN_80A5
, 0);
1083 WRITE(REG_A6XX_GRAS_UNKNOWN_80A6
, 0);
1084 WRITE(REG_A6XX_RB_UNKNOWN_8805
, 0);
1085 WRITE(REG_A6XX_RB_UNKNOWN_8806
, 0);
1086 WRITE(REG_A6XX_RB_UNKNOWN_8878
, 0);
1087 WRITE(REG_A6XX_RB_UNKNOWN_8879
, 0);
1088 WRITE(REG_A6XX_HLSQ_CONTROL_5_REG
, 0xfc);
1090 emit_marker6(ring
, 7);
1092 OUT_PKT4(ring
, REG_A6XX_VFD_MODE_CNTL
, 1);
1093 OUT_RING(ring
, 0x00000000); /* VFD_MODE_CNTL */
1095 WRITE(REG_A6XX_VFD_UNKNOWN_A008
, 0);
1097 OUT_PKT4(ring
, REG_A6XX_PC_MODE_CNTL
, 1);
1098 OUT_RING(ring
, 0x0000001f); /* PC_MODE_CNTL */
1100 /* we don't use this yet.. probably best to disable.. */
1101 OUT_PKT7(ring
, CP_SET_DRAW_STATE
, 3);
1102 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
1103 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1104 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1105 OUT_RING(ring
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1106 OUT_RING(ring
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1108 OUT_PKT4(ring
, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
1109 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
1110 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
1111 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
1113 OUT_PKT4(ring
, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
1114 OUT_RING(ring
, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
1115 OUT_RING(ring
, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1117 OUT_PKT4(ring
, REG_A6XX_VPC_SO_BUF_CNTL
, 1);
1118 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUF_CNTL */
1120 OUT_PKT4(ring
, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
1121 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E2AB */
1123 OUT_PKT4(ring
, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1124 OUT_RING(ring
, 0x00000000);
1125 OUT_RING(ring
, 0x00000000);
1126 OUT_RING(ring
, 0x00000000);
1128 OUT_PKT4(ring
, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
1129 OUT_RING(ring
, 0x00000000);
1130 OUT_RING(ring
, 0x00000000);
1131 OUT_RING(ring
, 0x00000000);
1132 OUT_RING(ring
, 0x00000000);
1133 OUT_RING(ring
, 0x00000000);
1134 OUT_RING(ring
, 0x00000000);
1136 OUT_PKT4(ring
, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
1137 OUT_RING(ring
, 0x00000000);
1138 OUT_RING(ring
, 0x00000000);
1139 OUT_RING(ring
, 0x00000000);
1140 OUT_RING(ring
, 0x00000000);
1141 OUT_RING(ring
, 0x00000000);
1142 OUT_RING(ring
, 0x00000000);
1144 OUT_PKT4(ring
, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
1145 OUT_RING(ring
, 0x00000000);
1146 OUT_RING(ring
, 0x00000000);
1147 OUT_RING(ring
, 0x00000000);
1149 OUT_PKT4(ring
, REG_A6XX_SP_HS_CTRL_REG0
, 1);
1150 OUT_RING(ring
, 0x00000000);
1152 OUT_PKT4(ring
, REG_A6XX_SP_GS_CTRL_REG0
, 1);
1153 OUT_RING(ring
, 0x00000000);
1155 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_CNTL
, 1);
1156 OUT_RING(ring
, 0x00000000);
1158 OUT_PKT4(ring
, REG_A6XX_RB_LRZ_CNTL
, 1);
1159 OUT_RING(ring
, 0x00000000);
1163 fd6_mem_to_mem(struct fd_ringbuffer
*ring
, struct pipe_resource
*dst
,
1164 unsigned dst_off
, struct pipe_resource
*src
, unsigned src_off
,
1165 unsigned sizedwords
)
1167 struct fd_bo
*src_bo
= fd_resource(src
)->bo
;
1168 struct fd_bo
*dst_bo
= fd_resource(dst
)->bo
;
1171 for (i
= 0; i
< sizedwords
; i
++) {
1172 OUT_PKT7(ring
, CP_MEM_TO_MEM
, 5);
1173 OUT_RING(ring
, 0x00000000);
1174 OUT_RELOCW(ring
, dst_bo
, dst_off
, 0, 0);
1175 OUT_RELOC (ring
, src_bo
, src_off
, 0, 0);
1183 fd6_emit_init(struct pipe_context
*pctx
)
1185 struct fd_context
*ctx
= fd_context(pctx
);
1186 ctx
->emit_const
= fd6_emit_const
;
1187 ctx
->emit_const_bo
= fd6_emit_const_bo
;
1188 ctx
->emit_ib
= fd6_emit_ib
;
1189 ctx
->mem_to_mem
= fd6_mem_to_mem
;