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freedreno/a6xx: Fix point coord
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_helpers.h"
32 #include "util/u_format.h"
33 #include "util/u_viewport.h"
34
35 #include "freedreno_resource.h"
36 #include "freedreno_query_hw.h"
37
38 #include "fd6_emit.h"
39 #include "fd6_blend.h"
40 #include "fd6_context.h"
41 #include "fd6_image.h"
42 #include "fd6_program.h"
43 #include "fd6_rasterizer.h"
44 #include "fd6_texture.h"
45 #include "fd6_format.h"
46 #include "fd6_zsa.h"
47
48 static uint32_t
49 shader_t_to_opcode(gl_shader_stage type)
50 {
51 switch (type) {
52 case MESA_SHADER_VERTEX:
53 case MESA_SHADER_TESS_CTRL:
54 case MESA_SHADER_TESS_EVAL:
55 case MESA_SHADER_GEOMETRY:
56 return CP_LOAD_STATE6_GEOM;
57 case MESA_SHADER_FRAGMENT:
58 case MESA_SHADER_COMPUTE:
59 case MESA_SHADER_KERNEL:
60 return CP_LOAD_STATE6_FRAG;
61 default:
62 unreachable("bad shader type");
63 }
64 }
65
66 /* regid: base const register
67 * prsc or dwords: buffer containing constant values
68 * sizedwords: size of const value buffer
69 */
70 static void
71 fd6_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
72 uint32_t regid, uint32_t offset, uint32_t sizedwords,
73 const uint32_t *dwords, struct pipe_resource *prsc)
74 {
75 uint32_t i, sz;
76 enum a6xx_state_src src;
77
78 debug_assert((regid % 4) == 0);
79 debug_assert((sizedwords % 4) == 0);
80
81 if (prsc) {
82 sz = 0;
83 src = SS6_INDIRECT;
84 } else {
85 sz = sizedwords;
86 src = SS6_DIRECT;
87 }
88
89 OUT_PKT7(ring, shader_t_to_opcode(type), 3 + sz);
90 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
91 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
92 CP_LOAD_STATE6_0_STATE_SRC(src) |
93 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
94 CP_LOAD_STATE6_0_NUM_UNIT(sizedwords/4));
95 if (prsc) {
96 struct fd_bo *bo = fd_resource(prsc)->bo;
97 OUT_RELOC(ring, bo, offset, 0, 0);
98 } else {
99 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
100 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
101 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
102 }
103 for (i = 0; i < sz; i++) {
104 OUT_RING(ring, dwords[i]);
105 }
106 }
107
108 static void
109 fd6_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
110 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
111 {
112 uint32_t anum = align(num, 2);
113 uint32_t i;
114
115 debug_assert((regid % 4) == 0);
116
117 OUT_PKT7(ring, shader_t_to_opcode(type), 3 + (2 * anum));
118 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
119 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS)|
120 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
121 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
122 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
123 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
124 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
125
126 for (i = 0; i < num; i++) {
127 if (prscs[i]) {
128 if (write) {
129 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
130 } else {
131 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
132 }
133 } else {
134 OUT_RING(ring, 0xbad00000 | (i << 16));
135 OUT_RING(ring, 0xbad00000 | (i << 16));
136 }
137 }
138
139 for (; i < anum; i++) {
140 OUT_RING(ring, 0xffffffff);
141 OUT_RING(ring, 0xffffffff);
142 }
143 }
144
145 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
146 * the same as a6xx then move this somewhere common ;-)
147 *
148 * Entry layout looks like (total size, 0x60 bytes):
149 */
150
151 struct PACKED bcolor_entry {
152 uint32_t fp32[4];
153 uint16_t ui16[4];
154 int16_t si16[4];
155 uint16_t fp16[4];
156 uint16_t rgb565;
157 uint16_t rgb5a1;
158 uint16_t rgba4;
159 uint8_t __pad0[2];
160 uint8_t ui8[4];
161 int8_t si8[4];
162 uint32_t rgb10a2;
163 uint32_t z24; /* also s8? */
164 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
165 uint8_t __pad1[24];
166 };
167
168 #define FD6_BORDER_COLOR_SIZE 0x60
169 #define FD6_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD6_BORDER_COLOR_SIZE)
170
171 static void
172 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
173 {
174 unsigned i, j;
175 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
176
177 for (i = 0; i < tex->num_samplers; i++) {
178 struct bcolor_entry *e = &entries[i];
179 struct pipe_sampler_state *sampler = tex->samplers[i];
180 union pipe_color_union *bc;
181
182 if (!sampler)
183 continue;
184
185 bc = &sampler->border_color;
186
187 /*
188 * XXX HACK ALERT XXX
189 *
190 * The border colors need to be swizzled in a particular
191 * format-dependent order. Even though samplers don't know about
192 * formats, we can assume that with a GL state tracker, there's a
193 * 1:1 correspondence between sampler and texture. Take advantage
194 * of that knowledge.
195 */
196 if ((i >= tex->num_textures) || !tex->textures[i])
197 continue;
198
199 enum pipe_format format = tex->textures[i]->format;
200 const struct util_format_description *desc =
201 util_format_description(format);
202
203 e->rgb565 = 0;
204 e->rgb5a1 = 0;
205 e->rgba4 = 0;
206 e->rgb10a2 = 0;
207 e->z24 = 0;
208
209 for (j = 0; j < 4; j++) {
210 int c = desc->swizzle[j];
211 int cd = c;
212
213 /*
214 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the
215 * stencil border color value in bc->ui[0] but according
216 * to desc->swizzle and desc->channel, the .x component
217 * is NONE and the stencil value is in the y component.
218 * Meanwhile the hardware wants this in the .x componetn.
219 */
220 if ((format == PIPE_FORMAT_X24S8_UINT) ||
221 (format == PIPE_FORMAT_X32_S8X24_UINT)) {
222 if (j == 0) {
223 c = 1;
224 cd = 0;
225 } else {
226 continue;
227 }
228 }
229
230 if (c >= 4)
231 continue;
232
233 if (desc->channel[c].pure_integer) {
234 uint16_t clamped;
235 switch (desc->channel[c].size) {
236 case 2:
237 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
238 clamped = CLAMP(bc->ui[j], 0, 0x3);
239 break;
240 case 8:
241 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
242 clamped = CLAMP(bc->i[j], -128, 127);
243 else
244 clamped = CLAMP(bc->ui[j], 0, 255);
245 break;
246 case 10:
247 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
248 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
249 break;
250 case 16:
251 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
252 clamped = CLAMP(bc->i[j], -32768, 32767);
253 else
254 clamped = CLAMP(bc->ui[j], 0, 65535);
255 break;
256 default:
257 assert(!"Unexpected bit size");
258 case 32:
259 clamped = 0;
260 break;
261 }
262 e->fp32[cd] = bc->ui[j];
263 e->fp16[cd] = clamped;
264 } else {
265 float f = bc->f[j];
266 float f_u = CLAMP(f, 0, 1);
267 float f_s = CLAMP(f, -1, 1);
268
269 e->fp32[c] = fui(f);
270 e->fp16[c] = util_float_to_half(f);
271 e->srgb[c] = util_float_to_half(f_u);
272 e->ui16[c] = f_u * 0xffff;
273 e->si16[c] = f_s * 0x7fff;
274 e->ui8[c] = f_u * 0xff;
275 e->si8[c] = f_s * 0x7f;
276 if (c == 1)
277 e->rgb565 |= (int)(f_u * 0x3f) << 5;
278 else if (c < 3)
279 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
280 if (c == 3)
281 e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
282 else
283 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
284 if (c == 3)
285 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
286 else
287 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
288 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
289 if (c == 0)
290 e->z24 = f_u * 0xffffff;
291 }
292 }
293
294 #ifdef DEBUG
295 memset(&e->__pad0, 0, sizeof(e->__pad0));
296 memset(&e->__pad1, 0, sizeof(e->__pad1));
297 #endif
298 }
299 }
300
301 static void
302 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
303 {
304 struct fd6_context *fd6_ctx = fd6_context(ctx);
305 struct bcolor_entry *entries;
306 unsigned off;
307 void *ptr;
308
309 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
310
311 u_upload_alloc(fd6_ctx->border_color_uploader,
312 0, FD6_BORDER_COLOR_UPLOAD_SIZE,
313 FD6_BORDER_COLOR_UPLOAD_SIZE, &off,
314 &fd6_ctx->border_color_buf,
315 &ptr);
316
317 entries = ptr;
318
319 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
320 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
321 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
322
323 OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
324 OUT_RELOC(ring, fd_resource(fd6_ctx->border_color_buf)->bo, off, 0, 0);
325
326 u_upload_unmap(fd6_ctx->border_color_uploader);
327 }
328
329 bool
330 fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
331 enum a6xx_state_block sb, struct fd_texture_stateobj *tex,
332 unsigned bcolor_offset)
333 {
334 bool needs_border = false;
335 unsigned opcode, tex_samp_reg, tex_const_reg, tex_count_reg;
336
337 switch (sb) {
338 case SB6_VS_TEX:
339 opcode = CP_LOAD_STATE6_GEOM;
340 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
341 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
342 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
343 break;
344 case SB6_FS_TEX:
345 opcode = CP_LOAD_STATE6_FRAG;
346 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
347 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
348 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
349 break;
350 case SB6_CS_TEX:
351 opcode = CP_LOAD_STATE6_FRAG;
352 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
353 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
354 tex_count_reg = 0; //REG_A6XX_SP_CS_TEX_COUNT;
355 break;
356 default:
357 unreachable("bad state block");
358 }
359
360
361 if (tex->num_samplers > 0) {
362 struct fd_ringbuffer *state =
363 fd_ringbuffer_new_object(pipe, tex->num_samplers * 4 * 4);
364 for (unsigned i = 0; i < tex->num_samplers; i++) {
365 static const struct fd6_sampler_stateobj dummy_sampler = {};
366 const struct fd6_sampler_stateobj *sampler = tex->samplers[i] ?
367 fd6_sampler_stateobj(tex->samplers[i]) : &dummy_sampler;
368 OUT_RING(state, sampler->texsamp0);
369 OUT_RING(state, sampler->texsamp1);
370 OUT_RING(state, sampler->texsamp2 |
371 A6XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset));
372 OUT_RING(state, sampler->texsamp3);
373 needs_border |= sampler->needs_border;
374 }
375
376 /* output sampler state: */
377 OUT_PKT7(ring, opcode, 3);
378 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
379 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
380 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
381 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
382 CP_LOAD_STATE6_0_NUM_UNIT(tex->num_samplers));
383 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
384
385 OUT_PKT4(ring, tex_samp_reg, 2);
386 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
387
388 fd_ringbuffer_del(state);
389 }
390
391 if (tex->num_textures > 0) {
392 struct fd_ringbuffer *state =
393 fd_ringbuffer_new_object(pipe, tex->num_textures * 16 * 4);
394 for (unsigned i = 0; i < tex->num_textures; i++) {
395 static const struct fd6_pipe_sampler_view dummy_view = {};
396 const struct fd6_pipe_sampler_view *view = tex->textures[i] ?
397 fd6_pipe_sampler_view(tex->textures[i]) : &dummy_view;
398
399 OUT_RING(state, view->texconst0);
400 OUT_RING(state, view->texconst1);
401 OUT_RING(state, view->texconst2);
402 OUT_RING(state, view->texconst3);
403
404 if (view->base.texture) {
405 struct fd_resource *rsc = fd_resource(view->base.texture);
406 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
407 rsc = rsc->stencil;
408 OUT_RELOC(state, rsc->bo, view->offset,
409 (uint64_t)view->texconst5 << 32, 0);
410 } else {
411 OUT_RING(state, 0x00000000);
412 OUT_RING(state, view->texconst5);
413 }
414
415 OUT_RING(state, view->texconst6);
416 OUT_RING(state, view->texconst7);
417 OUT_RING(state, view->texconst8);
418 OUT_RING(state, view->texconst9);
419 OUT_RING(state, view->texconst10);
420 OUT_RING(state, view->texconst11);
421 OUT_RING(state, 0);
422 OUT_RING(state, 0);
423 OUT_RING(state, 0);
424 OUT_RING(state, 0);
425 }
426
427 /* emit texture state: */
428 OUT_PKT7(ring, opcode, 3);
429 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
430 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
431 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
432 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
433 CP_LOAD_STATE6_0_NUM_UNIT(tex->num_textures));
434 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
435
436 OUT_PKT4(ring, tex_const_reg, 2);
437 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
438
439 fd_ringbuffer_del(state);
440 }
441
442 if (tex_count_reg) {
443 OUT_PKT4(ring, tex_count_reg, 1);
444 OUT_RING(ring, tex->num_textures);
445 }
446
447 return needs_border;
448 }
449
450 static void
451 emit_ssbos(struct fd_context *ctx, struct fd_ringbuffer *ring,
452 enum a6xx_state_block sb, struct fd_shaderbuf_stateobj *so)
453 {
454 unsigned count = util_last_bit(so->enabled_mask);
455 unsigned opcode;
456
457 if (count == 0)
458 return;
459
460 switch (sb) {
461 case SB6_IBO:
462 case SB6_CS_IBO:
463 opcode = CP_LOAD_STATE6_GEOM;
464 break;
465 default:
466 unreachable("bad state block");
467 }
468
469 OUT_PKT7(ring, opcode, 3 + (4 * count));
470 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
471 CP_LOAD_STATE6_0_STATE_TYPE(0) |
472 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
473 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
474 CP_LOAD_STATE6_0_NUM_UNIT(count));
475 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
476 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
477 for (unsigned i = 0; i < count; i++) {
478 OUT_RING(ring, 0x00000000);
479 OUT_RING(ring, 0x00000000);
480 OUT_RING(ring, 0x00000000);
481 OUT_RING(ring, 0x00000000);
482 }
483
484 #if 0
485 OUT_PKT7(ring, opcode, 3 + (2 * count));
486 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
487 CP_LOAD_STATE6_0_STATE_TYPE(1) |
488 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
489 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
490 CP_LOAD_STATE6_0_NUM_UNIT(count));
491 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
492 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
493 for (unsigned i = 0; i < count; i++) {
494 struct pipe_shader_buffer *buf = &so->sb[i];
495 unsigned sz = buf->buffer_size;
496
497 /* width is in dwords, overflows into height: */
498 sz /= 4;
499
500 OUT_RING(ring, A6XX_SSBO_1_0_WIDTH(sz));
501 OUT_RING(ring, A6XX_SSBO_1_1_HEIGHT(sz >> 16));
502 }
503 #endif
504
505 OUT_PKT7(ring, opcode, 3 + (2 * count));
506 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
507 CP_LOAD_STATE6_0_STATE_TYPE(2) |
508 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
509 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
510 CP_LOAD_STATE6_0_NUM_UNIT(count));
511 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
512 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
513 for (unsigned i = 0; i < count; i++) {
514 struct pipe_shader_buffer *buf = &so->sb[i];
515 if (buf->buffer) {
516 struct fd_resource *rsc = fd_resource(buf->buffer);
517 OUT_RELOCW(ring, rsc->bo, buf->buffer_offset, 0, 0);
518 } else {
519 OUT_RING(ring, 0x00000000);
520 OUT_RING(ring, 0x00000000);
521 }
522 }
523 }
524
525 static struct fd_ringbuffer *
526 build_vbo_state(struct fd6_emit *emit, const struct ir3_shader_variant *vp)
527 {
528 const struct fd_vertex_state *vtx = emit->vtx;
529 int32_t i, j;
530
531 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
532 4 * (10 * vp->inputs_count + 2), FD_RINGBUFFER_STREAMING);
533
534 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
535 if (vp->inputs[i].sysval)
536 continue;
537 if (vp->inputs[i].compmask) {
538 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
539 const struct pipe_vertex_buffer *vb =
540 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
541 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
542 enum pipe_format pfmt = elem->src_format;
543 enum a6xx_vtx_fmt fmt = fd6_pipe2vtx(pfmt);
544 bool isint = util_format_is_pure_integer(pfmt);
545 uint32_t off = vb->buffer_offset + elem->src_offset;
546 uint32_t size = fd_bo_size(rsc->bo) - off;
547 debug_assert(fmt != ~0);
548
549 #ifdef DEBUG
550 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
551 */
552 if (off > fd_bo_size(rsc->bo))
553 continue;
554 #endif
555
556 OUT_PKT4(ring, REG_A6XX_VFD_FETCH(j), 4);
557 OUT_RELOC(ring, rsc->bo, off, 0, 0);
558 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
559 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
560
561 OUT_PKT4(ring, REG_A6XX_VFD_DECODE(j), 2);
562 OUT_RING(ring, A6XX_VFD_DECODE_INSTR_IDX(j) |
563 A6XX_VFD_DECODE_INSTR_FORMAT(fmt) |
564 COND(elem->instance_divisor, A6XX_VFD_DECODE_INSTR_INSTANCED) |
565 A6XX_VFD_DECODE_INSTR_SWAP(fd6_pipe2swap(pfmt)) |
566 A6XX_VFD_DECODE_INSTR_UNK30 |
567 COND(!isint, A6XX_VFD_DECODE_INSTR_FLOAT));
568 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
569
570 OUT_PKT4(ring, REG_A6XX_VFD_DEST_CNTL(j), 1);
571 OUT_RING(ring, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
572 A6XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
573
574 j++;
575 }
576 }
577
578 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_0, 1);
579 OUT_RING(ring, A6XX_VFD_CONTROL_0_VTXCNT(j) | (j << 8));
580
581 return ring;
582 }
583
584 static struct fd_ringbuffer *
585 build_lrz(struct fd6_emit *emit, bool binning_pass)
586 {
587 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(emit->ctx->zsa);
588 struct pipe_framebuffer_state *pfb = &emit->ctx->batch->framebuffer;
589 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
590 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
591 uint32_t rb_lrz_cntl = zsa->rb_lrz_cntl;
592
593 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
594 16, FD_RINGBUFFER_STREAMING);
595
596 if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid) {
597 gras_lrz_cntl = 0;
598 rb_lrz_cntl = 0;
599 } else if (binning_pass && zsa->lrz_write) {
600 gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_LRZ_WRITE;
601 }
602
603 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
604 OUT_RING(ring, gras_lrz_cntl);
605
606 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
607 OUT_RING(ring, rb_lrz_cntl);
608
609 return ring;
610 }
611
612 void
613 fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
614 {
615 struct fd_context *ctx = emit->ctx;
616 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
617 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
618 const struct ir3_shader_variant *vp = emit->vs;
619 const struct ir3_shader_variant *fp = emit->fs;
620 const enum fd_dirty_3d_state dirty = emit->dirty;
621 bool needs_border = false;
622
623 emit_marker6(ring, 5);
624
625 if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE)) {
626 struct fd_ringbuffer *state;
627
628 state = build_vbo_state(emit, emit->vs);
629 fd6_emit_add_group(emit, state, FD6_GROUP_VBO, 0x6);
630 fd_ringbuffer_del(state);
631
632 state = build_vbo_state(emit, emit->bs);
633 fd6_emit_add_group(emit, state, FD6_GROUP_VBO_BINNING, 0x1);
634 fd_ringbuffer_del(state);
635 }
636
637 if (dirty & FD_DIRTY_ZSA) {
638 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
639
640 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
641 fd6_emit_add_group(emit, zsa->stateobj_no_alpha, FD6_GROUP_ZSA, 0x7);
642 else
643 fd6_emit_add_group(emit, zsa->stateobj, FD6_GROUP_ZSA, 0x7);
644 }
645
646 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && pfb->zsbuf) {
647 struct fd_ringbuffer *state;
648
649 state = build_lrz(emit, false);
650 fd6_emit_add_group(emit, state, FD6_GROUP_LRZ, 0x6);
651 fd_ringbuffer_del(state);
652
653 state = build_lrz(emit, true);
654 fd6_emit_add_group(emit, state, FD6_GROUP_LRZ_BINNING, 0x1);
655 fd_ringbuffer_del(state);
656 }
657
658 if (dirty & FD_DIRTY_STENCIL_REF) {
659 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
660
661 OUT_PKT4(ring, REG_A6XX_RB_STENCILREF, 1);
662 OUT_RING(ring, A6XX_RB_STENCILREF_REF(sr->ref_value[0]) |
663 A6XX_RB_STENCILREF_BFREF(sr->ref_value[1]));
664 }
665
666 /* NOTE: scissor enabled bit is part of rasterizer state: */
667 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
668 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
669
670 OUT_PKT4(ring, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
671 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
672 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
673 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
674 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
675
676 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
677 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
678 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
679 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
680 }
681
682 if (dirty & FD_DIRTY_VIEWPORT) {
683 struct pipe_scissor_state *scissor = &ctx->viewport_scissor;
684
685 OUT_PKT4(ring, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
686 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
687 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
688 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
689 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
690 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
691 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
692
693 OUT_PKT4(ring, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
694 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
695 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
696 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
697 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
698
699 unsigned guardband_x = fd_calc_guardband(scissor->maxx - scissor->minx);
700 unsigned guardband_y = fd_calc_guardband(scissor->maxy - scissor->miny);
701
702 OUT_PKT4(ring, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
703 OUT_RING(ring, A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_x) |
704 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_y));
705 }
706
707 if (dirty & FD_DIRTY_PROG) {
708 fd6_emit_add_group(emit, prog->stateobj, FD6_GROUP_PROG, 0x6);
709 fd6_emit_add_group(emit, prog->binning_stateobj,
710 FD6_GROUP_PROG_BINNING, 0x1);
711
712 /* emit remaining non-stateobj program state, ie. what depends
713 * on other emit state, so cannot be pre-baked. This could
714 * be moved to a separate stateobj which is dynamically
715 * created.
716 */
717 fd6_program_emit(ring, emit);
718 }
719
720 if (dirty & FD_DIRTY_RASTERIZER) {
721 struct fd6_rasterizer_stateobj *rasterizer =
722 fd6_rasterizer_stateobj(ctx->rasterizer);
723 fd6_emit_add_group(emit, rasterizer->stateobj,
724 FD6_GROUP_RASTERIZER, 0x7);
725 }
726
727 /* Since the primitive restart state is not part of a tracked object, we
728 * re-emit this register every time.
729 */
730 if (emit->info && ctx->rasterizer) {
731 struct fd6_rasterizer_stateobj *rasterizer =
732 fd6_rasterizer_stateobj(ctx->rasterizer);
733 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9806, 1);
734 OUT_RING(ring, 0);
735 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9990, 1);
736 OUT_RING(ring, 0);
737 OUT_PKT4(ring, REG_A6XX_VFD_UNKNOWN_A008, 1);
738 OUT_RING(ring, 0);
739
740 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
741 OUT_RING(ring, rasterizer->pc_primitive_cntl |
742 COND(emit->info->primitive_restart && emit->info->index_size,
743 A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART));
744 }
745
746 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
747 unsigned nr = pfb->nr_cbufs;
748
749 if (ctx->rasterizer->rasterizer_discard)
750 nr = 0;
751
752 OUT_PKT4(ring, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
753 OUT_RING(ring, COND(fp->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z));
754 OUT_RING(ring, A6XX_RB_FS_OUTPUT_CNTL1_MRT(nr));
755
756 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL1, 1);
757 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL1_MRT(nr));
758 }
759
760 #define DIRTY_CONST (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST | \
761 FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)
762
763 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & DIRTY_CONST) {
764 struct fd_ringbuffer *vsconstobj = fd_submit_new_ringbuffer(
765 ctx->batch->submit, 0x1000, FD_RINGBUFFER_STREAMING);
766
767 OUT_WFI5(vsconstobj);
768 ir3_emit_vs_consts(vp, vsconstobj, ctx, emit->info);
769 fd6_emit_add_group(emit, vsconstobj, FD6_GROUP_VS_CONST, 0x7);
770 fd_ringbuffer_del(vsconstobj);
771 }
772
773 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & DIRTY_CONST) {
774 struct fd_ringbuffer *fsconstobj = fd_submit_new_ringbuffer(
775 ctx->batch->submit, 0x1000, FD_RINGBUFFER_STREAMING);
776
777 OUT_WFI5(fsconstobj);
778 ir3_emit_fs_consts(fp, fsconstobj, ctx);
779 fd6_emit_add_group(emit, fsconstobj, FD6_GROUP_FS_CONST, 0x6);
780 fd_ringbuffer_del(fsconstobj);
781 }
782
783 struct ir3_stream_output_info *info = &vp->shader->stream_output;
784 if (info->num_outputs) {
785 struct fd_streamout_stateobj *so = &ctx->streamout;
786
787 emit->streamout_mask = 0;
788
789 for (unsigned i = 0; i < so->num_targets; i++) {
790 struct pipe_stream_output_target *target = so->targets[i];
791
792 if (!target)
793 continue;
794
795 unsigned offset = (so->offsets[i] * info->stride[i] * 4) +
796 target->buffer_offset;
797
798 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(i), 3);
799 /* VPC_SO[i].BUFFER_BASE_LO: */
800 OUT_RELOCW(ring, fd_resource(target->buffer)->bo, 0, 0, 0);
801 OUT_RING(ring, target->buffer_size + offset);
802
803 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(i), 3);
804 OUT_RING(ring, offset);
805 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
806 // TODO just give hw a dummy addr for now.. we should
807 // be using this an then CP_MEM_TO_REG to set the
808 // VPC_SO[i].BUFFER_OFFSET for the next draw..
809 OUT_RELOCW(ring, fd6_context(ctx)->blit_mem, 0x100, 0, 0);
810
811 emit->streamout_mask |= (1 << i);
812 }
813
814 if (emit->streamout_mask) {
815 const struct fd6_streamout_state *tf = &prog->tf;
816
817 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * tf->prog_count));
818 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
819 OUT_RING(ring, tf->vpc_so_buf_cntl);
820 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0));
821 OUT_RING(ring, tf->ncomp[0]);
822 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1));
823 OUT_RING(ring, tf->ncomp[1]);
824 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(2));
825 OUT_RING(ring, tf->ncomp[2]);
826 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3));
827 OUT_RING(ring, tf->ncomp[3]);
828 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
829 OUT_RING(ring, A6XX_VPC_SO_CNTL_ENABLE);
830 for (unsigned i = 0; i < tf->prog_count; i++) {
831 OUT_RING(ring, REG_A6XX_VPC_SO_PROG);
832 OUT_RING(ring, tf->prog[i]);
833 }
834
835 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
836 OUT_RING(ring, 0x0);
837 } else {
838 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 4);
839 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
840 OUT_RING(ring, 0);
841 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
842 OUT_RING(ring, 0);
843
844 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
845 OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
846 }
847 }
848
849 if (dirty & FD_DIRTY_BLEND) {
850 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
851 uint32_t i;
852
853 for (i = 0; i < A6XX_MAX_RENDER_TARGETS; i++) {
854 enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
855 bool is_int = util_format_is_pure_integer(format);
856 bool has_alpha = util_format_has_alpha(format);
857 uint32_t control = blend->rb_mrt[i].control;
858 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
859
860 if (is_int) {
861 control &= A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
862 control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
863 }
864
865 if (has_alpha) {
866 blend_control |= blend->rb_mrt[i].blend_control_rgb;
867 } else {
868 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
869 control &= ~A6XX_RB_MRT_CONTROL_BLEND2;
870 }
871
872 OUT_PKT4(ring, REG_A6XX_RB_MRT_CONTROL(i), 1);
873 OUT_RING(ring, control);
874
875 OUT_PKT4(ring, REG_A6XX_RB_MRT_BLEND_CONTROL(i), 1);
876 OUT_RING(ring, blend_control);
877 }
878
879 OUT_PKT4(ring, REG_A6XX_SP_BLEND_CNTL, 1);
880 OUT_RING(ring, blend->sp_blend_cntl);
881 }
882
883 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK)) {
884 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
885
886 OUT_PKT4(ring, REG_A6XX_RB_BLEND_CNTL, 1);
887 OUT_RING(ring, blend->rb_blend_cntl |
888 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(ctx->sample_mask));
889 }
890
891 if (dirty & FD_DIRTY_BLEND_COLOR) {
892 struct pipe_blend_color *bcolor = &ctx->blend_color;
893
894 OUT_PKT4(ring, REG_A6XX_RB_BLEND_RED_F32, 4);
895 OUT_RING(ring, A6XX_RB_BLEND_RED_F32(bcolor->color[0]));
896 OUT_RING(ring, A6XX_RB_BLEND_GREEN_F32(bcolor->color[1]));
897 OUT_RING(ring, A6XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
898 OUT_RING(ring, A6XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
899 }
900
901 if ((ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX) &&
902 ctx->tex[PIPE_SHADER_VERTEX].num_textures > 0) {
903 struct fd6_texture_state *tex = fd6_texture_state(ctx,
904 SB6_VS_TEX, &ctx->tex[PIPE_SHADER_VERTEX]);
905
906 needs_border |= tex->needs_border;
907
908 fd6_emit_add_group(emit, tex->stateobj, FD6_GROUP_VS_TEX, 0x7);
909 }
910
911 if ((ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX) &&
912 ctx->tex[PIPE_SHADER_FRAGMENT].num_textures > 0) {
913 struct fd6_texture_state *tex = fd6_texture_state(ctx,
914 SB6_FS_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT]);
915
916 needs_border |= tex->needs_border;
917
918 fd6_emit_add_group(emit, tex->stateobj, FD6_GROUP_FS_TEX, 0x7);
919 }
920
921 if (needs_border)
922 emit_border_color(ctx, ring);
923
924 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_SSBO)
925 emit_ssbos(ctx, ring, SB6_IBO, &ctx->shaderbuf[PIPE_SHADER_FRAGMENT]);
926
927 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_IMAGE)
928 fd6_emit_images(ctx, ring, PIPE_SHADER_FRAGMENT);
929
930 if (emit->num_groups > 0) {
931 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3 * emit->num_groups);
932 for (unsigned i = 0; i < emit->num_groups; i++) {
933 struct fd6_state_group *g = &emit->groups[i];
934 unsigned n = fd_ringbuffer_size(g->stateobj) / 4;
935
936 if (n == 0) {
937 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
938 CP_SET_DRAW_STATE__0_DISABLE |
939 CP_SET_DRAW_STATE__0_ENABLE_MASK(g->enable_mask) |
940 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
941 OUT_RING(ring, 0x00000000);
942 OUT_RING(ring, 0x00000000);
943 } else {
944 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(n) |
945 CP_SET_DRAW_STATE__0_ENABLE_MASK(g->enable_mask) |
946 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
947 OUT_RB(ring, g->stateobj);
948 }
949
950 fd_ringbuffer_del(g->stateobj);
951 }
952 emit->num_groups = 0;
953 }
954 }
955
956 void
957 fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
958 struct ir3_shader_variant *cp)
959 {
960 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
961
962 if (dirty & FD_DIRTY_SHADER_TEX) {
963 bool needs_border = false;
964 needs_border |= fd6_emit_textures(ctx->pipe, ring, SB6_CS_TEX,
965 &ctx->tex[PIPE_SHADER_COMPUTE], 0);
966
967 if (needs_border)
968 emit_border_color(ctx, ring);
969
970 #if 0
971 OUT_PKT4(ring, REG_A6XX_TPL1_VS_TEX_COUNT, 1);
972 OUT_RING(ring, 0);
973
974 OUT_PKT4(ring, REG_A6XX_TPL1_HS_TEX_COUNT, 1);
975 OUT_RING(ring, 0);
976
977 OUT_PKT4(ring, REG_A6XX_TPL1_DS_TEX_COUNT, 1);
978 OUT_RING(ring, 0);
979
980 OUT_PKT4(ring, REG_A6XX_TPL1_GS_TEX_COUNT, 1);
981 OUT_RING(ring, 0);
982
983 OUT_PKT4(ring, REG_A6XX_TPL1_FS_TEX_COUNT, 1);
984 OUT_RING(ring, 0);
985 #endif
986 }
987
988 #if 0
989 OUT_PKT4(ring, REG_A6XX_TPL1_CS_TEX_COUNT, 1);
990 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_COMPUTE].enabled_mask ?
991 ~0 : ctx->tex[PIPE_SHADER_COMPUTE].num_textures);
992 #endif
993
994 if (dirty & FD_DIRTY_SHADER_SSBO)
995 emit_ssbos(ctx, ring, SB6_CS_IBO, &ctx->shaderbuf[PIPE_SHADER_COMPUTE]);
996
997 if (dirty & FD_DIRTY_SHADER_IMAGE)
998 fd6_emit_images(ctx, ring, PIPE_SHADER_COMPUTE);
999 }
1000
1001
1002 /* emit setup at begin of new cmdstream buffer (don't rely on previous
1003 * state, there could have been a context switch between ioctls):
1004 */
1005 void
1006 fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
1007 {
1008 //struct fd_context *ctx = batch->ctx;
1009
1010 fd6_cache_flush(batch, ring);
1011
1012 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1013 OUT_RING(ring, 0xfffff);
1014
1015 /*
1016 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
1017 0000000500024048: 70d08003 00000000 001c5000 00000005
1018 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
1019 0000000500024058: 70d08003 00000010 001c7000 00000005
1020
1021 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
1022 0000000500024068: 70268000
1023 */
1024
1025 WRITE(REG_A6XX_RB_CCU_CNTL, 0x7c400004);
1026 WRITE(REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
1027 WRITE(REG_A6XX_SP_UNKNOWN_AE04, 0x8);
1028 WRITE(REG_A6XX_SP_UNKNOWN_AE00, 0);
1029 WRITE(REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
1030 WRITE(REG_A6XX_SP_UNKNOWN_B605, 0x44);
1031 WRITE(REG_A6XX_SP_UNKNOWN_B600, 0x100000);
1032 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
1033 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
1034
1035 WRITE(REG_A6XX_VPC_UNKNOWN_9600, 0);
1036 WRITE(REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
1037 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
1038 WRITE(REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
1039 WRITE(REG_A6XX_SP_IBO_COUNT, 0);
1040 WRITE(REG_A6XX_SP_UNKNOWN_B182, 0);
1041 WRITE(REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
1042 WRITE(REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
1043 WRITE(REG_A6XX_UCHE_CLIENT_PF, 4);
1044 WRITE(REG_A6XX_RB_UNKNOWN_8E01, 0x0);
1045 WRITE(REG_A6XX_SP_UNKNOWN_AB00, 0x5);
1046 WRITE(REG_A6XX_VFD_UNKNOWN_A009, 0x00000001);
1047 WRITE(REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
1048 WRITE(REG_A6XX_PC_MODE_CNTL, 0x1f);
1049
1050 OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
1051 OUT_RING(ring, 0);
1052
1053 WRITE(REG_A6XX_GRAS_UNKNOWN_8101, 0);
1054 WRITE(REG_A6XX_GRAS_UNKNOWN_8109, 0);
1055 WRITE(REG_A6XX_GRAS_UNKNOWN_8110, 0);
1056
1057 WRITE(REG_A6XX_RB_RENDER_CONTROL0, 0x401);
1058 WRITE(REG_A6XX_RB_RENDER_CONTROL1, 0);
1059 WRITE(REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
1060 WRITE(REG_A6XX_RB_UNKNOWN_8810, 0);
1061 WRITE(REG_A6XX_RB_UNKNOWN_8818, 0);
1062 WRITE(REG_A6XX_RB_UNKNOWN_8819, 0);
1063 WRITE(REG_A6XX_RB_UNKNOWN_881A, 0);
1064 WRITE(REG_A6XX_RB_UNKNOWN_881B, 0);
1065 WRITE(REG_A6XX_RB_UNKNOWN_881C, 0);
1066 WRITE(REG_A6XX_RB_UNKNOWN_881D, 0);
1067 WRITE(REG_A6XX_RB_UNKNOWN_881E, 0);
1068 WRITE(REG_A6XX_RB_UNKNOWN_88F0, 0);
1069
1070 WRITE(REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
1071 WRITE(REG_A6XX_VPC_UNKNOWN_9107, 0);
1072
1073 WRITE(REG_A6XX_VPC_UNKNOWN_9236,
1074 A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(0));
1075 WRITE(REG_A6XX_VPC_UNKNOWN_9300, 0);
1076
1077 WRITE(REG_A6XX_VPC_SO_OVERRIDE, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
1078
1079 WRITE(REG_A6XX_PC_UNKNOWN_9801, 0);
1080 WRITE(REG_A6XX_PC_UNKNOWN_9806, 0);
1081 WRITE(REG_A6XX_PC_UNKNOWN_9980, 0);
1082
1083 WRITE(REG_A6XX_PC_UNKNOWN_9B06, 0);
1084 WRITE(REG_A6XX_PC_UNKNOWN_9B06, 0);
1085
1086 WRITE(REG_A6XX_SP_UNKNOWN_A81B, 0);
1087
1088 WRITE(REG_A6XX_SP_UNKNOWN_B183, 0);
1089
1090 WRITE(REG_A6XX_GRAS_UNKNOWN_8099, 0);
1091 WRITE(REG_A6XX_GRAS_UNKNOWN_809B, 0);
1092 WRITE(REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1093 WRITE(REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1094 WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
1095 WRITE(REG_A6XX_VPC_UNKNOWN_9211, 0);
1096 WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
1097 WRITE(REG_A6XX_PC_UNKNOWN_9981, 0x3);
1098 WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
1099 WRITE(REG_A6XX_VPC_UNKNOWN_9108, 0x3);
1100 WRITE(REG_A6XX_SP_TP_UNKNOWN_B304, 0);
1101 WRITE(REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
1102 WRITE(REG_A6XX_RB_UNKNOWN_8804, 0);
1103 WRITE(REG_A6XX_GRAS_UNKNOWN_80A4, 0);
1104 WRITE(REG_A6XX_GRAS_UNKNOWN_80A5, 0);
1105 WRITE(REG_A6XX_GRAS_UNKNOWN_80A6, 0);
1106 WRITE(REG_A6XX_RB_UNKNOWN_8805, 0);
1107 WRITE(REG_A6XX_RB_UNKNOWN_8806, 0);
1108 WRITE(REG_A6XX_RB_UNKNOWN_8878, 0);
1109 WRITE(REG_A6XX_RB_UNKNOWN_8879, 0);
1110 WRITE(REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1111
1112 emit_marker6(ring, 7);
1113
1114 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
1115 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
1116
1117 WRITE(REG_A6XX_VFD_UNKNOWN_A008, 0);
1118
1119 OUT_PKT4(ring, REG_A6XX_PC_MODE_CNTL, 1);
1120 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
1121
1122 /* we don't use this yet.. probably best to disable.. */
1123 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1124 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1125 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1126 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1127 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1128 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1129
1130 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
1131 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
1132 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
1133 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
1134
1135 OUT_PKT4(ring, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
1136 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
1137 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1138
1139 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1140 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
1141
1142 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
1143 OUT_RING(ring, 0x00000000); /* UNKNOWN_E2AB */
1144
1145 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1146 OUT_RING(ring, 0x00000000);
1147 OUT_RING(ring, 0x00000000);
1148 OUT_RING(ring, 0x00000000);
1149
1150 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
1151 OUT_RING(ring, 0x00000000);
1152 OUT_RING(ring, 0x00000000);
1153 OUT_RING(ring, 0x00000000);
1154 OUT_RING(ring, 0x00000000);
1155 OUT_RING(ring, 0x00000000);
1156 OUT_RING(ring, 0x00000000);
1157
1158 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
1159 OUT_RING(ring, 0x00000000);
1160 OUT_RING(ring, 0x00000000);
1161 OUT_RING(ring, 0x00000000);
1162 OUT_RING(ring, 0x00000000);
1163 OUT_RING(ring, 0x00000000);
1164 OUT_RING(ring, 0x00000000);
1165
1166 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
1167 OUT_RING(ring, 0x00000000);
1168 OUT_RING(ring, 0x00000000);
1169 OUT_RING(ring, 0x00000000);
1170
1171 OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1);
1172 OUT_RING(ring, 0x00000000);
1173
1174 OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
1175 OUT_RING(ring, 0x00000000);
1176
1177 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1178 OUT_RING(ring, 0x00000000);
1179
1180 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
1181 OUT_RING(ring, 0x00000000);
1182 }
1183
1184 static void
1185 fd6_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
1186 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
1187 unsigned sizedwords)
1188 {
1189 struct fd_bo *src_bo = fd_resource(src)->bo;
1190 struct fd_bo *dst_bo = fd_resource(dst)->bo;
1191 unsigned i;
1192
1193 for (i = 0; i < sizedwords; i++) {
1194 OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
1195 OUT_RING(ring, 0x00000000);
1196 OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
1197 OUT_RELOC (ring, src_bo, src_off, 0, 0);
1198
1199 dst_off += 4;
1200 src_off += 4;
1201 }
1202 }
1203
1204 void
1205 fd6_emit_init(struct pipe_context *pctx)
1206 {
1207 struct fd_context *ctx = fd_context(pctx);
1208 ctx->emit_const = fd6_emit_const;
1209 ctx->emit_const_bo = fd6_emit_const_bo;
1210 ctx->emit_ib = fd6_emit_ib;
1211 ctx->mem_to_mem = fd6_mem_to_mem;
1212 }