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freedreno/a6xx: WFI before RB_CCU_CNTL writes
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_helpers.h"
32 #include "util/u_format.h"
33 #include "util/u_viewport.h"
34
35 #include "freedreno_resource.h"
36 #include "freedreno_query_hw.h"
37
38 #include "fd6_emit.h"
39 #include "fd6_blend.h"
40 #include "fd6_context.h"
41 #include "fd6_image.h"
42 #include "fd6_program.h"
43 #include "fd6_rasterizer.h"
44 #include "fd6_texture.h"
45 #include "fd6_format.h"
46 #include "fd6_zsa.h"
47
48 /* regid: base const register
49 * prsc or dwords: buffer containing constant values
50 * sizedwords: size of const value buffer
51 */
52 static void
53 fd6_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
54 uint32_t regid, uint32_t offset, uint32_t sizedwords,
55 const uint32_t *dwords, struct pipe_resource *prsc)
56 {
57 uint32_t i, sz, align_sz;
58 enum a6xx_state_src src;
59
60 debug_assert((regid % 4) == 0);
61
62 if (prsc) {
63 sz = 0;
64 src = SS6_INDIRECT;
65 } else {
66 sz = sizedwords;
67 src = SS6_DIRECT;
68 }
69
70 align_sz = align(sz, 4);
71
72 OUT_PKT7(ring, fd6_stage2opcode(type), 3 + align_sz);
73 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
74 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
75 CP_LOAD_STATE6_0_STATE_SRC(src) |
76 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
77 CP_LOAD_STATE6_0_NUM_UNIT(DIV_ROUND_UP(sizedwords, 4)));
78 if (prsc) {
79 struct fd_bo *bo = fd_resource(prsc)->bo;
80 OUT_RELOC(ring, bo, offset, 0, 0);
81 } else {
82 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
83 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
84 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
85 }
86
87 for (i = 0; i < sz; i++) {
88 OUT_RING(ring, dwords[i]);
89 }
90
91 /* Zero-pad to multiple of 4 dwords */
92 for (i = sz; i < align_sz; i++) {
93 OUT_RING(ring, 0);
94 }
95 }
96
97 static void
98 fd6_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
99 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
100 {
101 uint32_t anum = align(num, 2);
102 uint32_t i;
103
104 debug_assert((regid % 4) == 0);
105
106 OUT_PKT7(ring, fd6_stage2opcode(type), 3 + (2 * anum));
107 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
108 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS)|
109 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
110 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
111 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
112 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
113 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
114
115 for (i = 0; i < num; i++) {
116 if (prscs[i]) {
117 if (write) {
118 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
119 } else {
120 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
121 }
122 } else {
123 OUT_RING(ring, 0xbad00000 | (i << 16));
124 OUT_RING(ring, 0xbad00000 | (i << 16));
125 }
126 }
127
128 for (; i < anum; i++) {
129 OUT_RING(ring, 0xffffffff);
130 OUT_RING(ring, 0xffffffff);
131 }
132 }
133
134 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
135 * the same as a6xx then move this somewhere common ;-)
136 *
137 * Entry layout looks like (total size, 0x60 bytes):
138 */
139
140 struct PACKED bcolor_entry {
141 uint32_t fp32[4];
142 uint16_t ui16[4];
143 int16_t si16[4];
144 uint16_t fp16[4];
145 uint16_t rgb565;
146 uint16_t rgb5a1;
147 uint16_t rgba4;
148 uint8_t __pad0[2];
149 uint8_t ui8[4];
150 int8_t si8[4];
151 uint32_t rgb10a2;
152 uint32_t z24; /* also s8? */
153 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
154 uint8_t __pad1[56];
155 };
156
157 #define FD6_BORDER_COLOR_SIZE sizeof(struct bcolor_entry)
158 #define FD6_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD6_BORDER_COLOR_SIZE)
159
160 static void
161 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
162 {
163 unsigned i, j;
164 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
165
166 for (i = 0; i < tex->num_samplers; i++) {
167 struct bcolor_entry *e = &entries[i];
168 struct pipe_sampler_state *sampler = tex->samplers[i];
169 union pipe_color_union *bc;
170
171 if (!sampler)
172 continue;
173
174 bc = &sampler->border_color;
175
176 /*
177 * XXX HACK ALERT XXX
178 *
179 * The border colors need to be swizzled in a particular
180 * format-dependent order. Even though samplers don't know about
181 * formats, we can assume that with a GL state tracker, there's a
182 * 1:1 correspondence between sampler and texture. Take advantage
183 * of that knowledge.
184 */
185 if ((i >= tex->num_textures) || !tex->textures[i])
186 continue;
187
188 struct pipe_sampler_view *view = tex->textures[i];
189 enum pipe_format format = view->format;
190 const struct util_format_description *desc =
191 util_format_description(format);
192
193 e->rgb565 = 0;
194 e->rgb5a1 = 0;
195 e->rgba4 = 0;
196 e->rgb10a2 = 0;
197 e->z24 = 0;
198
199 unsigned char swiz[4];
200
201 fd6_tex_swiz(format, swiz,
202 view->swizzle_r, view->swizzle_g,
203 view->swizzle_b, view->swizzle_a);
204
205 for (j = 0; j < 4; j++) {
206 int c = swiz[j];
207 int cd = c;
208
209 /*
210 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the
211 * stencil border color value in bc->ui[0] but according
212 * to desc->swizzle and desc->channel, the .x component
213 * is NONE and the stencil value is in the y component.
214 * Meanwhile the hardware wants this in the .x componetn.
215 */
216 if ((format == PIPE_FORMAT_X24S8_UINT) ||
217 (format == PIPE_FORMAT_X32_S8X24_UINT)) {
218 if (j == 0) {
219 c = 1;
220 cd = 0;
221 } else {
222 continue;
223 }
224 }
225
226 if (c >= 4)
227 continue;
228
229 if (desc->channel[c].pure_integer) {
230 uint16_t clamped;
231 switch (desc->channel[c].size) {
232 case 2:
233 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
234 clamped = CLAMP(bc->ui[j], 0, 0x3);
235 break;
236 case 8:
237 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
238 clamped = CLAMP(bc->i[j], -128, 127);
239 else
240 clamped = CLAMP(bc->ui[j], 0, 255);
241 break;
242 case 10:
243 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
244 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
245 break;
246 case 16:
247 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
248 clamped = CLAMP(bc->i[j], -32768, 32767);
249 else
250 clamped = CLAMP(bc->ui[j], 0, 65535);
251 break;
252 default:
253 assert(!"Unexpected bit size");
254 case 32:
255 clamped = 0;
256 break;
257 }
258 e->fp32[cd] = bc->ui[j];
259 e->fp16[cd] = clamped;
260 } else {
261 float f = bc->f[j];
262 float f_u = CLAMP(f, 0, 1);
263 float f_s = CLAMP(f, -1, 1);
264
265 e->fp32[c] = fui(f);
266 e->fp16[c] = util_float_to_half(f);
267 e->srgb[c] = util_float_to_half(f_u);
268 e->ui16[c] = f_u * 0xffff;
269 e->si16[c] = f_s * 0x7fff;
270 e->ui8[c] = f_u * 0xff;
271 e->si8[c] = f_s * 0x7f;
272 if (c == 1)
273 e->rgb565 |= (int)(f_u * 0x3f) << 5;
274 else if (c < 3)
275 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
276 if (c == 3)
277 e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
278 else
279 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
280 if (c == 3)
281 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
282 else
283 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
284 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
285 if (c == 0)
286 e->z24 = f_u * 0xffffff;
287 }
288 }
289
290 #ifdef DEBUG
291 memset(&e->__pad0, 0, sizeof(e->__pad0));
292 memset(&e->__pad1, 0, sizeof(e->__pad1));
293 #endif
294 }
295 }
296
297 static void
298 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
299 {
300 struct fd6_context *fd6_ctx = fd6_context(ctx);
301 struct bcolor_entry *entries;
302 unsigned off;
303 void *ptr;
304
305 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
306
307 u_upload_alloc(fd6_ctx->border_color_uploader,
308 0, FD6_BORDER_COLOR_UPLOAD_SIZE,
309 FD6_BORDER_COLOR_UPLOAD_SIZE, &off,
310 &fd6_ctx->border_color_buf,
311 &ptr);
312
313 entries = ptr;
314
315 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
316 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
317 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
318
319 OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
320 OUT_RELOC(ring, fd_resource(fd6_ctx->border_color_buf)->bo, off, 0, 0);
321
322 u_upload_unmap(fd6_ctx->border_color_uploader);
323 }
324
325 static void
326 fd6_emit_fb_tex(struct fd_ringbuffer *state, struct fd_context *ctx)
327 {
328 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
329 struct pipe_surface *psurf = pfb->cbufs[0];
330 struct fd_resource *rsc = fd_resource(psurf->texture);
331
332 uint32_t texconst0 = fd6_tex_const_0(psurf->texture, psurf->u.tex.level,
333 psurf->format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
334 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W);
335
336 /* always TILE6_2 mode in GMEM.. which also means no swap: */
337 texconst0 &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
338 texconst0 |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
339
340 OUT_RING(state, texconst0);
341 OUT_RING(state, A6XX_TEX_CONST_1_WIDTH(pfb->width) |
342 A6XX_TEX_CONST_1_HEIGHT(pfb->height));
343 OUT_RINGP(state, A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
344 A6XX_TEX_CONST_2_FETCHSIZE(TFETCH6_2_BYTE),
345 &ctx->batch->fb_read_patches);
346 OUT_RING(state, A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layer_size));
347
348 OUT_RING(state, A6XX_TEX_CONST_4_BASE_LO(ctx->screen->gmem_base));
349 OUT_RING(state, A6XX_TEX_CONST_5_BASE_HI(ctx->screen->gmem_base >> 32) |
350 A6XX_TEX_CONST_5_DEPTH(1));
351 OUT_RING(state, 0); /* texconst6 */
352 OUT_RING(state, 0); /* texconst7 */
353 OUT_RING(state, 0); /* texconst8 */
354 OUT_RING(state, 0); /* texconst9 */
355 OUT_RING(state, 0); /* texconst10 */
356 OUT_RING(state, 0); /* texconst11 */
357 OUT_RING(state, 0);
358 OUT_RING(state, 0);
359 OUT_RING(state, 0);
360 OUT_RING(state, 0);
361 }
362
363 bool
364 fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
365 enum pipe_shader_type type, struct fd_texture_stateobj *tex,
366 unsigned bcolor_offset,
367 /* can be NULL if no image/SSBO/fb state to merge in: */
368 const struct ir3_shader_variant *v, struct fd_context *ctx)
369 {
370 bool needs_border = false;
371 unsigned opcode, tex_samp_reg, tex_const_reg, tex_count_reg;
372 enum a6xx_state_block sb;
373
374 switch (type) {
375 case PIPE_SHADER_VERTEX:
376 sb = SB6_VS_TEX;
377 opcode = CP_LOAD_STATE6_GEOM;
378 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
379 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
380 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
381 break;
382 case PIPE_SHADER_FRAGMENT:
383 sb = SB6_FS_TEX;
384 opcode = CP_LOAD_STATE6_FRAG;
385 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
386 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
387 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
388 break;
389 case PIPE_SHADER_COMPUTE:
390 sb = SB6_CS_TEX;
391 opcode = CP_LOAD_STATE6_FRAG;
392 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
393 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
394 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
395 break;
396 default:
397 unreachable("bad state block");
398 }
399
400 if (tex->num_samplers > 0) {
401 struct fd_ringbuffer *state =
402 fd_ringbuffer_new_object(pipe, tex->num_samplers * 4 * 4);
403 for (unsigned i = 0; i < tex->num_samplers; i++) {
404 static const struct fd6_sampler_stateobj dummy_sampler = {};
405 const struct fd6_sampler_stateobj *sampler = tex->samplers[i] ?
406 fd6_sampler_stateobj(tex->samplers[i]) : &dummy_sampler;
407 OUT_RING(state, sampler->texsamp0);
408 OUT_RING(state, sampler->texsamp1);
409 OUT_RING(state, sampler->texsamp2 |
410 A6XX_TEX_SAMP_2_BCOLOR_OFFSET((i + bcolor_offset) * sizeof(struct bcolor_entry)));
411 OUT_RING(state, sampler->texsamp3);
412 needs_border |= sampler->needs_border;
413 }
414
415 /* output sampler state: */
416 OUT_PKT7(ring, opcode, 3);
417 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
418 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
419 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
420 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
421 CP_LOAD_STATE6_0_NUM_UNIT(tex->num_samplers));
422 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
423
424 OUT_PKT4(ring, tex_samp_reg, 2);
425 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
426
427 fd_ringbuffer_del(state);
428 }
429
430 unsigned num_merged_textures = tex->num_textures;
431 unsigned num_textures = tex->num_textures;
432 if (v) {
433 num_merged_textures += v->image_mapping.num_tex;
434
435 if (v->fb_read)
436 num_merged_textures++;
437
438 /* There could be more bound textures than what the shader uses.
439 * Which isn't known at shader compile time. So in the case we
440 * are merging tex state, only emit the textures that the shader
441 * uses (since the image/SSBO related tex state comes immediately
442 * after)
443 */
444 num_textures = v->image_mapping.tex_base;
445 }
446
447 if (num_merged_textures > 0) {
448 struct fd_ringbuffer *state =
449 fd_ringbuffer_new_object(pipe, num_merged_textures * 16 * 4);
450 for (unsigned i = 0; i < num_textures; i++) {
451 static const struct fd6_pipe_sampler_view dummy_view = {};
452 const struct fd6_pipe_sampler_view *view = tex->textures[i] ?
453 fd6_pipe_sampler_view(tex->textures[i]) : &dummy_view;
454 struct fd_resource *rsc = NULL;
455
456 if (view->base.texture)
457 rsc = fd_resource(view->base.texture);
458
459 OUT_RING(state, view->texconst0);
460 OUT_RING(state, view->texconst1);
461 OUT_RING(state, view->texconst2);
462 OUT_RING(state, view->texconst3);
463
464 if (rsc) {
465 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
466 rsc = rsc->stencil;
467 OUT_RELOC(state, rsc->bo, view->offset,
468 (uint64_t)view->texconst5 << 32, 0);
469 } else {
470 OUT_RING(state, 0x00000000);
471 OUT_RING(state, view->texconst5);
472 }
473
474 OUT_RING(state, view->texconst6);
475
476 if (rsc && view->ubwc_enabled) {
477 OUT_RELOC(state, rsc->bo, view->ubwc_offset, 0, 0);
478 } else {
479 OUT_RING(state, 0);
480 OUT_RING(state, 0);
481 }
482
483 OUT_RING(state, view->texconst9);
484 OUT_RING(state, view->texconst10);
485 OUT_RING(state, view->texconst11);
486 OUT_RING(state, 0);
487 OUT_RING(state, 0);
488 OUT_RING(state, 0);
489 OUT_RING(state, 0);
490 }
491
492 if (v) {
493 const struct ir3_ibo_mapping *mapping = &v->image_mapping;
494 struct fd_shaderbuf_stateobj *buf = &ctx->shaderbuf[type];
495 struct fd_shaderimg_stateobj *img = &ctx->shaderimg[type];
496
497 for (unsigned i = 0; i < mapping->num_tex; i++) {
498 unsigned idx = mapping->tex_to_image[i];
499 if (idx & IBO_SSBO) {
500 fd6_emit_ssbo_tex(state, &buf->sb[idx & ~IBO_SSBO]);
501 } else {
502 fd6_emit_image_tex(state, &img->si[idx]);
503 }
504 }
505
506 if (v->fb_read) {
507 fd6_emit_fb_tex(state, ctx);
508 }
509 }
510
511 /* emit texture state: */
512 OUT_PKT7(ring, opcode, 3);
513 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
514 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
515 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
516 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
517 CP_LOAD_STATE6_0_NUM_UNIT(num_merged_textures));
518 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
519
520 OUT_PKT4(ring, tex_const_reg, 2);
521 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
522
523 fd_ringbuffer_del(state);
524 }
525
526 OUT_PKT4(ring, tex_count_reg, 1);
527 OUT_RING(ring, num_merged_textures);
528
529 return needs_border;
530 }
531
532 /* Emits combined texture state, which also includes any Image/SSBO
533 * related texture state merged in (because we must have all texture
534 * state for a given stage in a single buffer). In the fast-path, if
535 * we don't need to merge in any image/ssbo related texture state, we
536 * just use cached texture stateobj. Otherwise we generate a single-
537 * use stateobj.
538 *
539 * TODO Is there some sane way we can still use cached texture stateobj
540 * with image/ssbo in use?
541 *
542 * returns whether border_color is required:
543 */
544 static bool
545 fd6_emit_combined_textures(struct fd_ringbuffer *ring, struct fd6_emit *emit,
546 enum pipe_shader_type type, const struct ir3_shader_variant *v)
547 {
548 struct fd_context *ctx = emit->ctx;
549 bool needs_border = false;
550
551 static const struct {
552 enum fd6_state_id state_id;
553 unsigned enable_mask;
554 } s[PIPE_SHADER_TYPES] = {
555 [PIPE_SHADER_VERTEX] = { FD6_GROUP_VS_TEX, 0x7 },
556 [PIPE_SHADER_FRAGMENT] = { FD6_GROUP_FS_TEX, 0x6 },
557 };
558
559 debug_assert(s[type].state_id);
560
561 if (!v->image_mapping.num_tex && !v->fb_read) {
562 /* in the fast-path, when we don't have to mix in any image/SSBO
563 * related texture state, we can just lookup the stateobj and
564 * re-emit that:
565 *
566 * Also, framebuffer-read is a slow-path because an extra
567 * texture needs to be inserted.
568 *
569 * TODO we can probably simmplify things if we also treated
570 * border_color as a slow-path.. this way the tex state key
571 * wouldn't depend on bcolor_offset.. but fb_read might rather
572 * be *somehow* a fast-path if we eventually used it for PLS.
573 * I suppose there would be no harm in just *always* inserting
574 * an fb_read texture?
575 */
576 if ((ctx->dirty_shader[type] & FD_DIRTY_SHADER_TEX) &&
577 ctx->tex[type].num_textures > 0) {
578 struct fd6_texture_state *tex = fd6_texture_state(ctx,
579 type, &ctx->tex[type]);
580
581 needs_border |= tex->needs_border;
582
583 fd6_emit_add_group(emit, tex->stateobj, s[type].state_id,
584 s[type].enable_mask);
585 }
586 } else {
587 /* In the slow-path, create a one-shot texture state object
588 * if either TEX|PROG|SSBO|IMAGE state is dirty:
589 */
590 if ((ctx->dirty_shader[type] &
591 (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
592 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) ||
593 v->fb_read) {
594 struct fd_texture_stateobj *tex = &ctx->tex[type];
595 struct fd_ringbuffer *stateobj =
596 fd_submit_new_ringbuffer(ctx->batch->submit,
597 0x1000, FD_RINGBUFFER_STREAMING);
598 unsigned bcolor_offset =
599 fd6_border_color_offset(ctx, type, tex);
600
601 needs_border |= fd6_emit_textures(ctx->pipe, stateobj, type, tex,
602 bcolor_offset, v, ctx);
603
604 fd6_emit_add_group(emit, stateobj, s[type].state_id,
605 s[type].enable_mask);
606
607 fd_ringbuffer_del(stateobj);
608 }
609 }
610
611 return needs_border;
612 }
613
614 static struct fd_ringbuffer *
615 build_vbo_state(struct fd6_emit *emit, const struct ir3_shader_variant *vp)
616 {
617 const struct fd_vertex_state *vtx = emit->vtx;
618 int32_t i, j;
619
620 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
621 4 * (10 * vp->inputs_count + 2), FD_RINGBUFFER_STREAMING);
622
623 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
624 if (vp->inputs[i].sysval)
625 continue;
626 if (vp->inputs[i].compmask) {
627 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
628 const struct pipe_vertex_buffer *vb =
629 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
630 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
631 enum pipe_format pfmt = elem->src_format;
632 enum a6xx_vtx_fmt fmt = fd6_pipe2vtx(pfmt);
633 bool isint = util_format_is_pure_integer(pfmt);
634 uint32_t off = vb->buffer_offset + elem->src_offset;
635 uint32_t size = fd_bo_size(rsc->bo) - off;
636 debug_assert(fmt != ~0);
637
638 #ifdef DEBUG
639 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
640 */
641 if (off > fd_bo_size(rsc->bo))
642 continue;
643 #endif
644
645 OUT_PKT4(ring, REG_A6XX_VFD_FETCH(j), 4);
646 OUT_RELOC(ring, rsc->bo, off, 0, 0);
647 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
648 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
649
650 OUT_PKT4(ring, REG_A6XX_VFD_DECODE(j), 2);
651 OUT_RING(ring, A6XX_VFD_DECODE_INSTR_IDX(j) |
652 A6XX_VFD_DECODE_INSTR_FORMAT(fmt) |
653 COND(elem->instance_divisor, A6XX_VFD_DECODE_INSTR_INSTANCED) |
654 A6XX_VFD_DECODE_INSTR_SWAP(fd6_pipe2swap(pfmt)) |
655 A6XX_VFD_DECODE_INSTR_UNK30 |
656 COND(!isint, A6XX_VFD_DECODE_INSTR_FLOAT));
657 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
658
659 OUT_PKT4(ring, REG_A6XX_VFD_DEST_CNTL(j), 1);
660 OUT_RING(ring, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
661 A6XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
662
663 j++;
664 }
665 }
666
667 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_0, 1);
668 OUT_RING(ring, A6XX_VFD_CONTROL_0_VTXCNT(j) | (j << 8));
669
670 return ring;
671 }
672
673 static struct fd_ringbuffer *
674 build_lrz(struct fd6_emit *emit, bool binning_pass)
675 {
676 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(emit->ctx->zsa);
677 struct pipe_framebuffer_state *pfb = &emit->ctx->batch->framebuffer;
678 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
679 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
680 uint32_t rb_lrz_cntl = zsa->rb_lrz_cntl;
681
682 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
683 16, FD_RINGBUFFER_STREAMING);
684
685 if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid) {
686 gras_lrz_cntl = 0;
687 rb_lrz_cntl = 0;
688 } else if (binning_pass && zsa->lrz_write) {
689 gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_LRZ_WRITE;
690 }
691
692 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
693 OUT_RING(ring, gras_lrz_cntl);
694
695 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
696 OUT_RING(ring, rb_lrz_cntl);
697
698 return ring;
699 }
700
701 static void
702 fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3_stream_output_info *info)
703 {
704 struct fd_context *ctx = emit->ctx;
705 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
706 struct fd_streamout_stateobj *so = &ctx->streamout;
707
708 emit->streamout_mask = 0;
709
710 for (unsigned i = 0; i < so->num_targets; i++) {
711 struct pipe_stream_output_target *target = so->targets[i];
712
713 if (!target)
714 continue;
715
716 unsigned offset = (so->offsets[i] * info->stride[i] * 4) +
717 target->buffer_offset;
718
719 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(i), 3);
720 /* VPC_SO[i].BUFFER_BASE_LO: */
721 OUT_RELOCW(ring, fd_resource(target->buffer)->bo, 0, 0, 0);
722 OUT_RING(ring, target->buffer_size + offset);
723
724 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(i), 3);
725 OUT_RING(ring, offset);
726 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
727 // TODO just give hw a dummy addr for now.. we should
728 // be using this an then CP_MEM_TO_REG to set the
729 // VPC_SO[i].BUFFER_OFFSET for the next draw..
730 OUT_RELOCW(ring, fd6_context(ctx)->blit_mem, 0x100, 0, 0);
731
732 emit->streamout_mask |= (1 << i);
733 }
734
735 if (emit->streamout_mask) {
736 const struct fd6_streamout_state *tf = &prog->tf;
737
738 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * tf->prog_count));
739 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
740 OUT_RING(ring, tf->vpc_so_buf_cntl);
741 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0));
742 OUT_RING(ring, tf->ncomp[0]);
743 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1));
744 OUT_RING(ring, tf->ncomp[1]);
745 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(2));
746 OUT_RING(ring, tf->ncomp[2]);
747 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3));
748 OUT_RING(ring, tf->ncomp[3]);
749 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
750 OUT_RING(ring, A6XX_VPC_SO_CNTL_ENABLE);
751 for (unsigned i = 0; i < tf->prog_count; i++) {
752 OUT_RING(ring, REG_A6XX_VPC_SO_PROG);
753 OUT_RING(ring, tf->prog[i]);
754 }
755
756 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
757 OUT_RING(ring, 0x0);
758 } else {
759 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 4);
760 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
761 OUT_RING(ring, 0);
762 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
763 OUT_RING(ring, 0);
764
765 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
766 OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
767 }
768
769 }
770
771 void
772 fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
773 {
774 struct fd_context *ctx = emit->ctx;
775 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
776 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
777 const struct ir3_shader_variant *vp = emit->vs;
778 const struct ir3_shader_variant *fp = emit->fs;
779 const enum fd_dirty_3d_state dirty = emit->dirty;
780 bool needs_border = false;
781
782 emit_marker6(ring, 5);
783
784 /* NOTE: we track fb_read differently than _BLEND_ENABLED since
785 * we might at some point decide to do sysmem in some cases when
786 * blend is enabled:
787 */
788 if (fp->fb_read)
789 ctx->batch->gmem_reason |= FD_GMEM_FB_READ;
790
791 if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE)) {
792 struct fd_ringbuffer *state;
793
794 state = build_vbo_state(emit, emit->vs);
795 fd6_emit_add_group(emit, state, FD6_GROUP_VBO, 0x6);
796 fd_ringbuffer_del(state);
797
798 state = build_vbo_state(emit, emit->bs);
799 fd6_emit_add_group(emit, state, FD6_GROUP_VBO_BINNING, 0x1);
800 fd_ringbuffer_del(state);
801 }
802
803 if (dirty & FD_DIRTY_ZSA) {
804 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
805
806 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
807 fd6_emit_add_group(emit, zsa->stateobj_no_alpha, FD6_GROUP_ZSA, 0x7);
808 else
809 fd6_emit_add_group(emit, zsa->stateobj, FD6_GROUP_ZSA, 0x7);
810 }
811
812 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && pfb->zsbuf) {
813 struct fd_ringbuffer *state;
814
815 state = build_lrz(emit, false);
816 fd6_emit_add_group(emit, state, FD6_GROUP_LRZ, 0x6);
817 fd_ringbuffer_del(state);
818
819 state = build_lrz(emit, true);
820 fd6_emit_add_group(emit, state, FD6_GROUP_LRZ_BINNING, 0x1);
821 fd_ringbuffer_del(state);
822 }
823
824 if (dirty & FD_DIRTY_STENCIL_REF) {
825 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
826
827 OUT_PKT4(ring, REG_A6XX_RB_STENCILREF, 1);
828 OUT_RING(ring, A6XX_RB_STENCILREF_REF(sr->ref_value[0]) |
829 A6XX_RB_STENCILREF_BFREF(sr->ref_value[1]));
830 }
831
832 /* NOTE: scissor enabled bit is part of rasterizer state: */
833 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
834 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
835
836 OUT_PKT4(ring, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
837 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
838 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
839 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
840 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
841
842 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
843 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
844 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
845 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
846 }
847
848 if (dirty & FD_DIRTY_VIEWPORT) {
849 struct pipe_scissor_state *scissor = &ctx->viewport_scissor;
850
851 OUT_PKT4(ring, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
852 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
853 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
854 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
855 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
856 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
857 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
858
859 OUT_PKT4(ring, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
860 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
861 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
862 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
863 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
864
865 unsigned guardband_x = fd_calc_guardband(scissor->maxx - scissor->minx);
866 unsigned guardband_y = fd_calc_guardband(scissor->maxy - scissor->miny);
867
868 OUT_PKT4(ring, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
869 OUT_RING(ring, A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_x) |
870 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_y));
871 }
872
873 if (dirty & FD_DIRTY_PROG) {
874 fd6_emit_add_group(emit, prog->stateobj, FD6_GROUP_PROG, 0x6);
875 fd6_emit_add_group(emit, prog->binning_stateobj,
876 FD6_GROUP_PROG_BINNING, 0x1);
877
878 /* emit remaining non-stateobj program state, ie. what depends
879 * on other emit state, so cannot be pre-baked. This could
880 * be moved to a separate stateobj which is dynamically
881 * created.
882 */
883 fd6_program_emit(ring, emit);
884 }
885
886 if (dirty & FD_DIRTY_RASTERIZER) {
887 struct fd6_rasterizer_stateobj *rasterizer =
888 fd6_rasterizer_stateobj(ctx->rasterizer);
889 fd6_emit_add_group(emit, rasterizer->stateobj,
890 FD6_GROUP_RASTERIZER, 0x7);
891 }
892
893 /* Since the primitive restart state is not part of a tracked object, we
894 * re-emit this register every time.
895 */
896 if (emit->info && ctx->rasterizer) {
897 struct fd6_rasterizer_stateobj *rasterizer =
898 fd6_rasterizer_stateobj(ctx->rasterizer);
899 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9806, 1);
900 OUT_RING(ring, 0);
901 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9990, 1);
902 OUT_RING(ring, 0);
903 OUT_PKT4(ring, REG_A6XX_VFD_UNKNOWN_A008, 1);
904 OUT_RING(ring, 0);
905
906 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
907 OUT_RING(ring, rasterizer->pc_primitive_cntl |
908 COND(emit->info->primitive_restart && emit->info->index_size,
909 A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART));
910 }
911
912 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
913 unsigned nr = pfb->nr_cbufs;
914
915 if (ctx->rasterizer->rasterizer_discard)
916 nr = 0;
917
918 OUT_PKT4(ring, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
919 OUT_RING(ring, COND(fp->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
920 COND(fp->writes_smask && pfb->samples > 1,
921 A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
922 OUT_RING(ring, A6XX_RB_FS_OUTPUT_CNTL1_MRT(nr));
923
924 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL1, 1);
925 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL1_MRT(nr));
926 }
927
928 #define DIRTY_CONST (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST | \
929 FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)
930
931 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & DIRTY_CONST) {
932 struct fd_ringbuffer *vsconstobj = fd_submit_new_ringbuffer(
933 ctx->batch->submit, 0x1000, FD_RINGBUFFER_STREAMING);
934
935 OUT_WFI5(vsconstobj);
936 ir3_emit_vs_consts(vp, vsconstobj, ctx, emit->info);
937 fd6_emit_add_group(emit, vsconstobj, FD6_GROUP_VS_CONST, 0x7);
938 fd_ringbuffer_del(vsconstobj);
939 }
940
941 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & DIRTY_CONST) {
942 struct fd_ringbuffer *fsconstobj = fd_submit_new_ringbuffer(
943 ctx->batch->submit, 0x1000, FD_RINGBUFFER_STREAMING);
944
945 OUT_WFI5(fsconstobj);
946 ir3_emit_fs_consts(fp, fsconstobj, ctx);
947 fd6_emit_add_group(emit, fsconstobj, FD6_GROUP_FS_CONST, 0x6);
948 fd_ringbuffer_del(fsconstobj);
949 }
950
951 struct ir3_stream_output_info *info = &vp->shader->stream_output;
952 if (info->num_outputs)
953 fd6_emit_streamout(ring, emit, info);
954
955 if (dirty & FD_DIRTY_BLEND) {
956 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
957 uint32_t i;
958
959 for (i = 0; i < pfb->nr_cbufs; i++) {
960 enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
961 bool is_int = util_format_is_pure_integer(format);
962 bool has_alpha = util_format_has_alpha(format);
963 uint32_t control = blend->rb_mrt[i].control;
964 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
965
966 if (is_int) {
967 control &= A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
968 control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
969 }
970
971 if (has_alpha) {
972 blend_control |= blend->rb_mrt[i].blend_control_rgb;
973 } else {
974 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
975 control &= ~A6XX_RB_MRT_CONTROL_BLEND2;
976 }
977
978 OUT_PKT4(ring, REG_A6XX_RB_MRT_CONTROL(i), 1);
979 OUT_RING(ring, control);
980
981 OUT_PKT4(ring, REG_A6XX_RB_MRT_BLEND_CONTROL(i), 1);
982 OUT_RING(ring, blend_control);
983 }
984
985 OUT_PKT4(ring, REG_A6XX_SP_BLEND_CNTL, 1);
986 OUT_RING(ring, blend->sp_blend_cntl);
987 }
988
989 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK)) {
990 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
991
992 OUT_PKT4(ring, REG_A6XX_RB_BLEND_CNTL, 1);
993 OUT_RING(ring, blend->rb_blend_cntl |
994 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(ctx->sample_mask));
995 }
996
997 if (dirty & FD_DIRTY_BLEND_COLOR) {
998 struct pipe_blend_color *bcolor = &ctx->blend_color;
999
1000 OUT_PKT4(ring, REG_A6XX_RB_BLEND_RED_F32, 4);
1001 OUT_RING(ring, A6XX_RB_BLEND_RED_F32(bcolor->color[0]));
1002 OUT_RING(ring, A6XX_RB_BLEND_GREEN_F32(bcolor->color[1]));
1003 OUT_RING(ring, A6XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
1004 OUT_RING(ring, A6XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
1005 }
1006
1007 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_VERTEX, vp);
1008 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_FRAGMENT, fp);
1009
1010 if (needs_border)
1011 emit_border_color(ctx, ring);
1012
1013 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] &
1014 (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)) {
1015 struct fd_ringbuffer *state =
1016 fd6_build_ibo_state(ctx, fp, PIPE_SHADER_FRAGMENT);
1017 struct fd_ringbuffer *obj = fd_submit_new_ringbuffer(
1018 ctx->batch->submit, 9 * 4, FD_RINGBUFFER_STREAMING);
1019 const struct ir3_ibo_mapping *mapping = &fp->image_mapping;
1020
1021 OUT_PKT7(obj, CP_LOAD_STATE6, 3);
1022 OUT_RING(obj, CP_LOAD_STATE6_0_DST_OFF(0) |
1023 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1024 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1025 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_IBO) |
1026 CP_LOAD_STATE6_0_NUM_UNIT(mapping->num_ibo));
1027 OUT_RB(obj, state);
1028
1029 OUT_PKT4(obj, REG_A6XX_SP_IBO_LO, 2);
1030 OUT_RB(obj, state);
1031
1032 OUT_PKT4(obj, REG_A6XX_SP_IBO_COUNT, 1);
1033 OUT_RING(obj, mapping->num_ibo);
1034
1035 fd6_emit_add_group(emit, obj, FD6_GROUP_IBO, 0x6);
1036 fd_ringbuffer_del(obj);
1037 fd_ringbuffer_del(state);
1038 }
1039
1040 if (emit->num_groups > 0) {
1041 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3 * emit->num_groups);
1042 for (unsigned i = 0; i < emit->num_groups; i++) {
1043 struct fd6_state_group *g = &emit->groups[i];
1044 unsigned n = fd_ringbuffer_size(g->stateobj) / 4;
1045
1046 if (n == 0) {
1047 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1048 CP_SET_DRAW_STATE__0_DISABLE |
1049 CP_SET_DRAW_STATE__0_ENABLE_MASK(g->enable_mask) |
1050 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
1051 OUT_RING(ring, 0x00000000);
1052 OUT_RING(ring, 0x00000000);
1053 } else {
1054 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(n) |
1055 CP_SET_DRAW_STATE__0_ENABLE_MASK(g->enable_mask) |
1056 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
1057 OUT_RB(ring, g->stateobj);
1058 }
1059
1060 fd_ringbuffer_del(g->stateobj);
1061 }
1062 emit->num_groups = 0;
1063 }
1064 }
1065
1066 void
1067 fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
1068 struct ir3_shader_variant *cp)
1069 {
1070 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
1071
1072 if (dirty & (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
1073 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) {
1074 struct fd_texture_stateobj *tex = &ctx->tex[PIPE_SHADER_COMPUTE];
1075 unsigned bcolor_offset = fd6_border_color_offset(ctx, PIPE_SHADER_COMPUTE, tex);
1076
1077 bool needs_border = fd6_emit_textures(ctx->pipe, ring, PIPE_SHADER_COMPUTE, tex,
1078 bcolor_offset, cp, ctx);
1079
1080 if (needs_border)
1081 emit_border_color(ctx, ring);
1082
1083 OUT_PKT4(ring, REG_A6XX_SP_VS_TEX_COUNT, 1);
1084 OUT_RING(ring, 0);
1085
1086 OUT_PKT4(ring, REG_A6XX_SP_HS_TEX_COUNT, 1);
1087 OUT_RING(ring, 0);
1088
1089 OUT_PKT4(ring, REG_A6XX_SP_DS_TEX_COUNT, 1);
1090 OUT_RING(ring, 0);
1091
1092 OUT_PKT4(ring, REG_A6XX_SP_GS_TEX_COUNT, 1);
1093 OUT_RING(ring, 0);
1094
1095 OUT_PKT4(ring, REG_A6XX_SP_FS_TEX_COUNT, 1);
1096 OUT_RING(ring, 0);
1097 }
1098
1099 if (dirty & (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)) {
1100 struct fd_ringbuffer *state =
1101 fd6_build_ibo_state(ctx, cp, PIPE_SHADER_COMPUTE);
1102 const struct ir3_ibo_mapping *mapping = &cp->image_mapping;
1103
1104 OUT_PKT7(ring, CP_LOAD_STATE6_FRAG, 3);
1105 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
1106 CP_LOAD_STATE6_0_STATE_TYPE(ST6_IBO) |
1107 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1108 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_CS_SHADER) |
1109 CP_LOAD_STATE6_0_NUM_UNIT(mapping->num_ibo));
1110 OUT_RB(ring, state);
1111
1112 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_LO, 2);
1113 OUT_RB(ring, state);
1114
1115 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_COUNT, 1);
1116 OUT_RING(ring, mapping->num_ibo);
1117
1118 fd_ringbuffer_del(state);
1119 }
1120 }
1121
1122
1123 /* emit setup at begin of new cmdstream buffer (don't rely on previous
1124 * state, there could have been a context switch between ioctls):
1125 */
1126 void
1127 fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
1128 {
1129 //struct fd_context *ctx = batch->ctx;
1130
1131 fd6_cache_inv(batch, ring);
1132
1133 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1134 OUT_RING(ring, 0xfffff);
1135
1136 /*
1137 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
1138 0000000500024048: 70d08003 00000000 001c5000 00000005
1139 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
1140 0000000500024058: 70d08003 00000010 001c7000 00000005
1141
1142 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
1143 0000000500024068: 70268000
1144 */
1145
1146 OUT_WFI5(ring);
1147
1148 WRITE(REG_A6XX_RB_CCU_CNTL, 0x7c400004);
1149 WRITE(REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
1150 WRITE(REG_A6XX_SP_UNKNOWN_AE04, 0x8);
1151 WRITE(REG_A6XX_SP_UNKNOWN_AE00, 0);
1152 WRITE(REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
1153 WRITE(REG_A6XX_SP_UNKNOWN_B605, 0x44);
1154 WRITE(REG_A6XX_SP_UNKNOWN_B600, 0x100000);
1155 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
1156 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
1157
1158 WRITE(REG_A6XX_VPC_UNKNOWN_9600, 0);
1159 WRITE(REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
1160 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE04, 0x80000);
1161 WRITE(REG_A6XX_SP_UNKNOWN_AE03, 0x1430);
1162 WRITE(REG_A6XX_SP_IBO_COUNT, 0);
1163 WRITE(REG_A6XX_SP_UNKNOWN_B182, 0);
1164 WRITE(REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
1165 WRITE(REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
1166 WRITE(REG_A6XX_UCHE_CLIENT_PF, 4);
1167 WRITE(REG_A6XX_RB_UNKNOWN_8E01, 0x1);
1168 WRITE(REG_A6XX_SP_UNKNOWN_AB00, 0x5);
1169 WRITE(REG_A6XX_VFD_UNKNOWN_A009, 0x00000001);
1170 WRITE(REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
1171 WRITE(REG_A6XX_PC_MODE_CNTL, 0x1f);
1172
1173 OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
1174 OUT_RING(ring, 0);
1175
1176 WRITE(REG_A6XX_GRAS_UNKNOWN_8101, 0);
1177 WRITE(REG_A6XX_GRAS_SAMPLE_CNTL, 0);
1178 WRITE(REG_A6XX_GRAS_UNKNOWN_8110, 0x2);
1179
1180 WRITE(REG_A6XX_RB_RENDER_CONTROL0, 0x401);
1181 WRITE(REG_A6XX_RB_RENDER_CONTROL1, 0);
1182 WRITE(REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
1183 WRITE(REG_A6XX_RB_SAMPLE_CNTL, 0);
1184 WRITE(REG_A6XX_RB_UNKNOWN_8818, 0);
1185 WRITE(REG_A6XX_RB_UNKNOWN_8819, 0);
1186 WRITE(REG_A6XX_RB_UNKNOWN_881A, 0);
1187 WRITE(REG_A6XX_RB_UNKNOWN_881B, 0);
1188 WRITE(REG_A6XX_RB_UNKNOWN_881C, 0);
1189 WRITE(REG_A6XX_RB_UNKNOWN_881D, 0);
1190 WRITE(REG_A6XX_RB_UNKNOWN_881E, 0);
1191 WRITE(REG_A6XX_RB_UNKNOWN_88F0, 0);
1192
1193 WRITE(REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
1194 WRITE(REG_A6XX_VPC_UNKNOWN_9107, 0);
1195
1196 WRITE(REG_A6XX_VPC_UNKNOWN_9236,
1197 A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(0));
1198 WRITE(REG_A6XX_VPC_UNKNOWN_9300, 0);
1199
1200 WRITE(REG_A6XX_VPC_SO_OVERRIDE, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
1201
1202 WRITE(REG_A6XX_PC_UNKNOWN_9801, 0);
1203 WRITE(REG_A6XX_PC_UNKNOWN_9806, 0);
1204 WRITE(REG_A6XX_PC_UNKNOWN_9980, 0);
1205
1206 WRITE(REG_A6XX_PC_UNKNOWN_9B06, 0);
1207 WRITE(REG_A6XX_PC_UNKNOWN_9B06, 0);
1208
1209 WRITE(REG_A6XX_SP_UNKNOWN_A81B, 0);
1210
1211 WRITE(REG_A6XX_SP_UNKNOWN_B183, 0);
1212
1213 WRITE(REG_A6XX_GRAS_UNKNOWN_8099, 0);
1214 WRITE(REG_A6XX_GRAS_UNKNOWN_809B, 0);
1215 WRITE(REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1216 WRITE(REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1217 WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
1218 WRITE(REG_A6XX_VPC_UNKNOWN_9211, 0);
1219 WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
1220 WRITE(REG_A6XX_PC_UNKNOWN_9981, 0x3);
1221 WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
1222 WRITE(REG_A6XX_VPC_UNKNOWN_9108, 0x3);
1223 WRITE(REG_A6XX_SP_TP_UNKNOWN_B304, 0);
1224 /* NOTE blob seems to (mostly?) use 0xb2 for SP_TP_UNKNOWN_B309
1225 * but this seems to kill texture gather offsets.
1226 */
1227 WRITE(REG_A6XX_SP_TP_UNKNOWN_B309, 0xa2);
1228 WRITE(REG_A6XX_RB_UNKNOWN_8804, 0);
1229 WRITE(REG_A6XX_GRAS_UNKNOWN_80A4, 0);
1230 WRITE(REG_A6XX_GRAS_UNKNOWN_80A5, 0);
1231 WRITE(REG_A6XX_GRAS_UNKNOWN_80A6, 0);
1232 WRITE(REG_A6XX_RB_UNKNOWN_8805, 0);
1233 WRITE(REG_A6XX_RB_UNKNOWN_8806, 0);
1234 WRITE(REG_A6XX_RB_UNKNOWN_8878, 0);
1235 WRITE(REG_A6XX_RB_UNKNOWN_8879, 0);
1236 WRITE(REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1237
1238 emit_marker6(ring, 7);
1239
1240 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
1241 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
1242
1243 WRITE(REG_A6XX_VFD_UNKNOWN_A008, 0);
1244
1245 OUT_PKT4(ring, REG_A6XX_PC_MODE_CNTL, 1);
1246 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
1247
1248 /* we don't use this yet.. probably best to disable.. */
1249 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1250 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1251 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1252 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1253 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1254 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1255
1256 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1257 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
1258
1259 OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1);
1260 OUT_RING(ring, 0x00000000);
1261
1262 OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
1263 OUT_RING(ring, 0x00000000);
1264
1265 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1266 OUT_RING(ring, 0x00000000);
1267
1268 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
1269 OUT_RING(ring, 0x00000000);
1270 }
1271
1272 static void
1273 fd6_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
1274 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
1275 unsigned sizedwords)
1276 {
1277 struct fd_bo *src_bo = fd_resource(src)->bo;
1278 struct fd_bo *dst_bo = fd_resource(dst)->bo;
1279 unsigned i;
1280
1281 for (i = 0; i < sizedwords; i++) {
1282 OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
1283 OUT_RING(ring, 0x00000000);
1284 OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
1285 OUT_RELOC (ring, src_bo, src_off, 0, 0);
1286
1287 dst_off += 4;
1288 src_off += 4;
1289 }
1290 }
1291
1292 /* this is *almost* the same as fd6_cache_flush().. which I guess
1293 * could be re-worked to be something a bit more generic w/ param
1294 * indicating what needs to be flushed.. although that would mean
1295 * figuring out which events trigger what state to flush..
1296 */
1297 static void
1298 fd6_framebuffer_barrier(struct fd_context *ctx)
1299 {
1300 struct fd6_context *fd6_ctx = fd6_context(ctx);
1301 struct fd_batch *batch = ctx->batch;
1302 struct fd_ringbuffer *ring = batch->draw;
1303 unsigned seqno;
1304
1305 seqno = fd6_event_write(batch, ring, CACHE_FLUSH_AND_INV_EVENT, true);
1306
1307 OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);
1308 OUT_RING(ring, 0x00000013);
1309 OUT_RELOC(ring, fd6_ctx->blit_mem, 0, 0, 0);
1310 OUT_RING(ring, seqno);
1311 OUT_RING(ring, 0xffffffff);
1312 OUT_RING(ring, 0x00000010);
1313
1314 fd6_event_write(batch, ring, UNK_1D, true);
1315 fd6_event_write(batch, ring, UNK_1C, true);
1316
1317 seqno = fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
1318
1319 fd6_event_write(batch, ring, 0x31, false);
1320
1321 OUT_PKT7(ring, CP_UNK_A6XX_14, 4);
1322 OUT_RING(ring, 0x00000000);
1323 OUT_RELOC(ring, fd6_ctx->blit_mem, 0, 0, 0);
1324 OUT_RING(ring, seqno);
1325 }
1326
1327 void
1328 fd6_emit_init(struct pipe_context *pctx)
1329 {
1330 struct fd_context *ctx = fd_context(pctx);
1331 ctx->emit_const = fd6_emit_const;
1332 ctx->emit_const_bo = fd6_emit_const_bo;
1333 ctx->emit_ib = fd6_emit_ib;
1334 ctx->mem_to_mem = fd6_mem_to_mem;
1335 ctx->framebuffer_barrier = fd6_framebuffer_barrier;
1336 }