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freedreno/a6xx: UBWC support
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_helpers.h"
32 #include "util/u_format.h"
33 #include "util/u_viewport.h"
34
35 #include "freedreno_resource.h"
36 #include "freedreno_query_hw.h"
37
38 #include "fd6_emit.h"
39 #include "fd6_blend.h"
40 #include "fd6_context.h"
41 #include "fd6_image.h"
42 #include "fd6_program.h"
43 #include "fd6_rasterizer.h"
44 #include "fd6_texture.h"
45 #include "fd6_format.h"
46 #include "fd6_zsa.h"
47
48 static uint32_t
49 shader_t_to_opcode(gl_shader_stage type)
50 {
51 switch (type) {
52 case MESA_SHADER_VERTEX:
53 case MESA_SHADER_TESS_CTRL:
54 case MESA_SHADER_TESS_EVAL:
55 case MESA_SHADER_GEOMETRY:
56 return CP_LOAD_STATE6_GEOM;
57 case MESA_SHADER_FRAGMENT:
58 case MESA_SHADER_COMPUTE:
59 case MESA_SHADER_KERNEL:
60 return CP_LOAD_STATE6_FRAG;
61 default:
62 unreachable("bad shader type");
63 }
64 }
65
66 /* regid: base const register
67 * prsc or dwords: buffer containing constant values
68 * sizedwords: size of const value buffer
69 */
70 static void
71 fd6_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
72 uint32_t regid, uint32_t offset, uint32_t sizedwords,
73 const uint32_t *dwords, struct pipe_resource *prsc)
74 {
75 uint32_t i, sz;
76 enum a6xx_state_src src;
77
78 debug_assert((regid % 4) == 0);
79 debug_assert((sizedwords % 4) == 0);
80
81 if (prsc) {
82 sz = 0;
83 src = SS6_INDIRECT;
84 } else {
85 sz = sizedwords;
86 src = SS6_DIRECT;
87 }
88
89 OUT_PKT7(ring, shader_t_to_opcode(type), 3 + sz);
90 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
91 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
92 CP_LOAD_STATE6_0_STATE_SRC(src) |
93 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
94 CP_LOAD_STATE6_0_NUM_UNIT(sizedwords/4));
95 if (prsc) {
96 struct fd_bo *bo = fd_resource(prsc)->bo;
97 OUT_RELOC(ring, bo, offset, 0, 0);
98 } else {
99 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
100 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
101 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
102 }
103 for (i = 0; i < sz; i++) {
104 OUT_RING(ring, dwords[i]);
105 }
106 }
107
108 static void
109 fd6_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
110 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
111 {
112 uint32_t anum = align(num, 2);
113 uint32_t i;
114
115 debug_assert((regid % 4) == 0);
116
117 OUT_PKT7(ring, shader_t_to_opcode(type), 3 + (2 * anum));
118 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
119 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS)|
120 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
121 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
122 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
123 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
124 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
125
126 for (i = 0; i < num; i++) {
127 if (prscs[i]) {
128 if (write) {
129 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
130 } else {
131 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
132 }
133 } else {
134 OUT_RING(ring, 0xbad00000 | (i << 16));
135 OUT_RING(ring, 0xbad00000 | (i << 16));
136 }
137 }
138
139 for (; i < anum; i++) {
140 OUT_RING(ring, 0xffffffff);
141 OUT_RING(ring, 0xffffffff);
142 }
143 }
144
145 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
146 * the same as a6xx then move this somewhere common ;-)
147 *
148 * Entry layout looks like (total size, 0x60 bytes):
149 */
150
151 struct PACKED bcolor_entry {
152 uint32_t fp32[4];
153 uint16_t ui16[4];
154 int16_t si16[4];
155 uint16_t fp16[4];
156 uint16_t rgb565;
157 uint16_t rgb5a1;
158 uint16_t rgba4;
159 uint8_t __pad0[2];
160 uint8_t ui8[4];
161 int8_t si8[4];
162 uint32_t rgb10a2;
163 uint32_t z24; /* also s8? */
164 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
165 uint8_t __pad1[24];
166 };
167
168 #define FD6_BORDER_COLOR_SIZE 0x60
169 #define FD6_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD6_BORDER_COLOR_SIZE)
170
171 static void
172 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
173 {
174 unsigned i, j;
175 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
176
177 for (i = 0; i < tex->num_samplers; i++) {
178 struct bcolor_entry *e = &entries[i];
179 struct pipe_sampler_state *sampler = tex->samplers[i];
180 union pipe_color_union *bc;
181
182 if (!sampler)
183 continue;
184
185 bc = &sampler->border_color;
186
187 /*
188 * XXX HACK ALERT XXX
189 *
190 * The border colors need to be swizzled in a particular
191 * format-dependent order. Even though samplers don't know about
192 * formats, we can assume that with a GL state tracker, there's a
193 * 1:1 correspondence between sampler and texture. Take advantage
194 * of that knowledge.
195 */
196 if ((i >= tex->num_textures) || !tex->textures[i])
197 continue;
198
199 enum pipe_format format = tex->textures[i]->format;
200 const struct util_format_description *desc =
201 util_format_description(format);
202
203 e->rgb565 = 0;
204 e->rgb5a1 = 0;
205 e->rgba4 = 0;
206 e->rgb10a2 = 0;
207 e->z24 = 0;
208
209 for (j = 0; j < 4; j++) {
210 int c = desc->swizzle[j];
211 int cd = c;
212
213 /*
214 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the
215 * stencil border color value in bc->ui[0] but according
216 * to desc->swizzle and desc->channel, the .x component
217 * is NONE and the stencil value is in the y component.
218 * Meanwhile the hardware wants this in the .x componetn.
219 */
220 if ((format == PIPE_FORMAT_X24S8_UINT) ||
221 (format == PIPE_FORMAT_X32_S8X24_UINT)) {
222 if (j == 0) {
223 c = 1;
224 cd = 0;
225 } else {
226 continue;
227 }
228 }
229
230 if (c >= 4)
231 continue;
232
233 if (desc->channel[c].pure_integer) {
234 uint16_t clamped;
235 switch (desc->channel[c].size) {
236 case 2:
237 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
238 clamped = CLAMP(bc->ui[j], 0, 0x3);
239 break;
240 case 8:
241 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
242 clamped = CLAMP(bc->i[j], -128, 127);
243 else
244 clamped = CLAMP(bc->ui[j], 0, 255);
245 break;
246 case 10:
247 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
248 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
249 break;
250 case 16:
251 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
252 clamped = CLAMP(bc->i[j], -32768, 32767);
253 else
254 clamped = CLAMP(bc->ui[j], 0, 65535);
255 break;
256 default:
257 assert(!"Unexpected bit size");
258 case 32:
259 clamped = 0;
260 break;
261 }
262 e->fp32[cd] = bc->ui[j];
263 e->fp16[cd] = clamped;
264 } else {
265 float f = bc->f[j];
266 float f_u = CLAMP(f, 0, 1);
267 float f_s = CLAMP(f, -1, 1);
268
269 e->fp32[c] = fui(f);
270 e->fp16[c] = util_float_to_half(f);
271 e->srgb[c] = util_float_to_half(f_u);
272 e->ui16[c] = f_u * 0xffff;
273 e->si16[c] = f_s * 0x7fff;
274 e->ui8[c] = f_u * 0xff;
275 e->si8[c] = f_s * 0x7f;
276 if (c == 1)
277 e->rgb565 |= (int)(f_u * 0x3f) << 5;
278 else if (c < 3)
279 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
280 if (c == 3)
281 e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
282 else
283 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
284 if (c == 3)
285 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
286 else
287 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
288 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
289 if (c == 0)
290 e->z24 = f_u * 0xffffff;
291 }
292 }
293
294 #ifdef DEBUG
295 memset(&e->__pad0, 0, sizeof(e->__pad0));
296 memset(&e->__pad1, 0, sizeof(e->__pad1));
297 #endif
298 }
299 }
300
301 static void
302 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
303 {
304 struct fd6_context *fd6_ctx = fd6_context(ctx);
305 struct bcolor_entry *entries;
306 unsigned off;
307 void *ptr;
308
309 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
310
311 u_upload_alloc(fd6_ctx->border_color_uploader,
312 0, FD6_BORDER_COLOR_UPLOAD_SIZE,
313 FD6_BORDER_COLOR_UPLOAD_SIZE, &off,
314 &fd6_ctx->border_color_buf,
315 &ptr);
316
317 entries = ptr;
318
319 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
320 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
321 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
322
323 OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
324 OUT_RELOC(ring, fd_resource(fd6_ctx->border_color_buf)->bo, off, 0, 0);
325
326 u_upload_unmap(fd6_ctx->border_color_uploader);
327 }
328
329 bool
330 fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
331 enum a6xx_state_block sb, struct fd_texture_stateobj *tex,
332 unsigned bcolor_offset,
333 /* can be NULL if no image/SSBO state to merge in: */
334 const struct ir3_shader_variant *v, struct fd_shaderbuf_stateobj *buf,
335 struct fd_shaderimg_stateobj *img)
336 {
337 bool needs_border = false;
338 unsigned opcode, tex_samp_reg, tex_const_reg, tex_count_reg;
339
340 switch (sb) {
341 case SB6_VS_TEX:
342 opcode = CP_LOAD_STATE6_GEOM;
343 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
344 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
345 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
346 break;
347 case SB6_FS_TEX:
348 opcode = CP_LOAD_STATE6_FRAG;
349 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
350 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
351 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
352 break;
353 case SB6_CS_TEX:
354 opcode = CP_LOAD_STATE6_FRAG;
355 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
356 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
357 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
358 break;
359 default:
360 unreachable("bad state block");
361 }
362
363 if (tex->num_samplers > 0) {
364 struct fd_ringbuffer *state =
365 fd_ringbuffer_new_object(pipe, tex->num_samplers * 4 * 4);
366 for (unsigned i = 0; i < tex->num_samplers; i++) {
367 static const struct fd6_sampler_stateobj dummy_sampler = {};
368 const struct fd6_sampler_stateobj *sampler = tex->samplers[i] ?
369 fd6_sampler_stateobj(tex->samplers[i]) : &dummy_sampler;
370 OUT_RING(state, sampler->texsamp0);
371 OUT_RING(state, sampler->texsamp1);
372 OUT_RING(state, sampler->texsamp2 |
373 A6XX_TEX_SAMP_2_BCOLOR_OFFSET((i + bcolor_offset) * sizeof(struct bcolor_entry)));
374 OUT_RING(state, sampler->texsamp3);
375 needs_border |= sampler->needs_border;
376 }
377
378 /* output sampler state: */
379 OUT_PKT7(ring, opcode, 3);
380 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
381 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
382 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
383 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
384 CP_LOAD_STATE6_0_NUM_UNIT(tex->num_samplers));
385 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
386
387 OUT_PKT4(ring, tex_samp_reg, 2);
388 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
389
390 fd_ringbuffer_del(state);
391 }
392
393 unsigned num_merged_textures = tex->num_textures;
394 unsigned num_textures = tex->num_textures;
395 if (v) {
396 num_merged_textures += v->image_mapping.num_tex;
397
398 /* There could be more bound textures than what the shader uses.
399 * Which isn't known at shader compile time. So in the case we
400 * are merging tex state, only emit the textures that the shader
401 * uses (since the image/SSBO related tex state comes immediately
402 * after)
403 */
404 num_textures = v->image_mapping.tex_base;
405 }
406
407 if (num_merged_textures > 0) {
408 struct fd_ringbuffer *state =
409 fd_ringbuffer_new_object(pipe, num_merged_textures * 16 * 4);
410 for (unsigned i = 0; i < num_textures; i++) {
411 static const struct fd6_pipe_sampler_view dummy_view = {};
412 const struct fd6_pipe_sampler_view *view = tex->textures[i] ?
413 fd6_pipe_sampler_view(tex->textures[i]) : &dummy_view;
414 struct fd_resource *rsc = NULL;
415
416 if (view->base.texture)
417 rsc = fd_resource(view->base.texture);
418
419 OUT_RING(state, view->texconst0);
420 OUT_RING(state, view->texconst1);
421 OUT_RING(state, view->texconst2);
422 OUT_RING(state, view->texconst3 |
423 COND(rsc && view->ubwc_enabled,
424 A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_UNK27));
425
426 if (rsc) {
427 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
428 rsc = rsc->stencil;
429 OUT_RELOC(state, rsc->bo, view->offset + rsc->offset,
430 (uint64_t)view->texconst5 << 32, 0);
431 } else {
432 OUT_RING(state, 0x00000000);
433 OUT_RING(state, view->texconst5);
434 }
435
436 OUT_RING(state, view->texconst6);
437
438 if (rsc && view->ubwc_enabled) {
439 OUT_RELOC(state, rsc->bo, view->offset + rsc->ubwc_offset, 0, 0);
440 } else {
441 OUT_RING(state, 0);
442 OUT_RING(state, 0);
443 }
444
445 OUT_RING(state, view->texconst9);
446 OUT_RING(state, view->texconst10);
447 OUT_RING(state, view->texconst11);
448 OUT_RING(state, 0);
449 OUT_RING(state, 0);
450 OUT_RING(state, 0);
451 OUT_RING(state, 0);
452 }
453
454 if (v) {
455 const struct ir3_ibo_mapping *mapping = &v->image_mapping;
456
457 for (unsigned i = 0; i < mapping->num_tex; i++) {
458 unsigned idx = mapping->tex_to_image[i];
459 if (idx & IBO_SSBO) {
460 fd6_emit_ssbo_tex(state, &buf->sb[idx & ~IBO_SSBO]);
461 } else {
462 fd6_emit_image_tex(state, &img->si[idx]);
463 }
464 }
465 }
466
467 /* emit texture state: */
468 OUT_PKT7(ring, opcode, 3);
469 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
470 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
471 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
472 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
473 CP_LOAD_STATE6_0_NUM_UNIT(num_merged_textures));
474 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
475
476 OUT_PKT4(ring, tex_const_reg, 2);
477 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
478
479 fd_ringbuffer_del(state);
480 }
481
482 OUT_PKT4(ring, tex_count_reg, 1);
483 OUT_RING(ring, num_merged_textures);
484
485 return needs_border;
486 }
487
488 /* Emits combined texture state, which also includes any Image/SSBO
489 * related texture state merged in (because we must have all texture
490 * state for a given stage in a single buffer). In the fast-path, if
491 * we don't need to merge in any image/ssbo related texture state, we
492 * just use cached texture stateobj. Otherwise we generate a single-
493 * use stateobj.
494 *
495 * TODO Is there some sane way we can still use cached texture stateobj
496 * with image/ssbo in use?
497 *
498 * returns whether border_color is required:
499 */
500 static bool
501 fd6_emit_combined_textures(struct fd_ringbuffer *ring, struct fd6_emit *emit,
502 enum pipe_shader_type type, const struct ir3_shader_variant *v)
503 {
504 struct fd_context *ctx = emit->ctx;
505 bool needs_border = false;
506
507 static const struct {
508 enum a6xx_state_block sb;
509 enum fd6_state_id state_id;
510 } s[PIPE_SHADER_TYPES] = {
511 [PIPE_SHADER_VERTEX] = { SB6_VS_TEX, FD6_GROUP_VS_TEX },
512 [PIPE_SHADER_FRAGMENT] = { SB6_FS_TEX, FD6_GROUP_FS_TEX },
513 };
514
515 debug_assert(s[type].state_id);
516
517 if (!v->image_mapping.num_tex) {
518 /* in the fast-path, when we don't have to mix in any image/SSBO
519 * related texture state, we can just lookup the stateobj and
520 * re-emit that:
521 */
522 if ((ctx->dirty_shader[type] & FD_DIRTY_SHADER_TEX) &&
523 ctx->tex[type].num_textures > 0) {
524 struct fd6_texture_state *tex = fd6_texture_state(ctx,
525 s[type].sb, &ctx->tex[type]);
526
527 needs_border |= tex->needs_border;
528
529 fd6_emit_add_group(emit, tex->stateobj, s[type].state_id, 0x7);
530 }
531 } else {
532 /* In the slow-path, create a one-shot texture state object
533 * if either TEX|PROG|SSBO|IMAGE state is dirty:
534 */
535 if (ctx->dirty_shader[type] &
536 (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
537 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) {
538 struct fd_texture_stateobj *tex = &ctx->tex[type];
539 struct fd_shaderbuf_stateobj *buf = &ctx->shaderbuf[type];
540 struct fd_shaderimg_stateobj *img = &ctx->shaderimg[type];
541 struct fd_ringbuffer *stateobj =
542 fd_submit_new_ringbuffer(ctx->batch->submit,
543 0x1000, FD_RINGBUFFER_STREAMING);
544 unsigned bcolor_offset =
545 fd6_border_color_offset(ctx, s[type].sb, tex);
546
547 needs_border |= fd6_emit_textures(ctx->pipe, stateobj, s[type].sb, tex,
548 bcolor_offset, v, buf, img);
549
550 fd6_emit_add_group(emit, stateobj, s[type].state_id, 0x7);
551
552 fd_ringbuffer_del(stateobj);
553 }
554 }
555
556 return needs_border;
557 }
558
559 static struct fd_ringbuffer *
560 build_vbo_state(struct fd6_emit *emit, const struct ir3_shader_variant *vp)
561 {
562 const struct fd_vertex_state *vtx = emit->vtx;
563 int32_t i, j;
564
565 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
566 4 * (10 * vp->inputs_count + 2), FD_RINGBUFFER_STREAMING);
567
568 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
569 if (vp->inputs[i].sysval)
570 continue;
571 if (vp->inputs[i].compmask) {
572 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
573 const struct pipe_vertex_buffer *vb =
574 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
575 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
576 enum pipe_format pfmt = elem->src_format;
577 enum a6xx_vtx_fmt fmt = fd6_pipe2vtx(pfmt);
578 bool isint = util_format_is_pure_integer(pfmt);
579 uint32_t off = vb->buffer_offset + elem->src_offset;
580 uint32_t size = fd_bo_size(rsc->bo) - off;
581 debug_assert(fmt != ~0);
582
583 #ifdef DEBUG
584 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
585 */
586 if (off > fd_bo_size(rsc->bo))
587 continue;
588 #endif
589
590 OUT_PKT4(ring, REG_A6XX_VFD_FETCH(j), 4);
591 OUT_RELOC(ring, rsc->bo, off, 0, 0);
592 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
593 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
594
595 OUT_PKT4(ring, REG_A6XX_VFD_DECODE(j), 2);
596 OUT_RING(ring, A6XX_VFD_DECODE_INSTR_IDX(j) |
597 A6XX_VFD_DECODE_INSTR_FORMAT(fmt) |
598 COND(elem->instance_divisor, A6XX_VFD_DECODE_INSTR_INSTANCED) |
599 A6XX_VFD_DECODE_INSTR_SWAP(fd6_pipe2swap(pfmt)) |
600 A6XX_VFD_DECODE_INSTR_UNK30 |
601 COND(!isint, A6XX_VFD_DECODE_INSTR_FLOAT));
602 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
603
604 OUT_PKT4(ring, REG_A6XX_VFD_DEST_CNTL(j), 1);
605 OUT_RING(ring, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
606 A6XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
607
608 j++;
609 }
610 }
611
612 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_0, 1);
613 OUT_RING(ring, A6XX_VFD_CONTROL_0_VTXCNT(j) | (j << 8));
614
615 return ring;
616 }
617
618 static struct fd_ringbuffer *
619 build_lrz(struct fd6_emit *emit, bool binning_pass)
620 {
621 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(emit->ctx->zsa);
622 struct pipe_framebuffer_state *pfb = &emit->ctx->batch->framebuffer;
623 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
624 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
625 uint32_t rb_lrz_cntl = zsa->rb_lrz_cntl;
626
627 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
628 16, FD_RINGBUFFER_STREAMING);
629
630 if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid) {
631 gras_lrz_cntl = 0;
632 rb_lrz_cntl = 0;
633 } else if (binning_pass && zsa->lrz_write) {
634 gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_LRZ_WRITE;
635 }
636
637 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
638 OUT_RING(ring, gras_lrz_cntl);
639
640 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
641 OUT_RING(ring, rb_lrz_cntl);
642
643 return ring;
644 }
645
646 static void
647 fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3_stream_output_info *info)
648 {
649 struct fd_context *ctx = emit->ctx;
650 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
651 struct fd_streamout_stateobj *so = &ctx->streamout;
652
653 emit->streamout_mask = 0;
654
655 for (unsigned i = 0; i < so->num_targets; i++) {
656 struct pipe_stream_output_target *target = so->targets[i];
657
658 if (!target)
659 continue;
660
661 unsigned offset = (so->offsets[i] * info->stride[i] * 4) +
662 target->buffer_offset;
663
664 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(i), 3);
665 /* VPC_SO[i].BUFFER_BASE_LO: */
666 OUT_RELOCW(ring, fd_resource(target->buffer)->bo, 0, 0, 0);
667 OUT_RING(ring, target->buffer_size + offset);
668
669 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(i), 3);
670 OUT_RING(ring, offset);
671 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
672 // TODO just give hw a dummy addr for now.. we should
673 // be using this an then CP_MEM_TO_REG to set the
674 // VPC_SO[i].BUFFER_OFFSET for the next draw..
675 OUT_RELOCW(ring, fd6_context(ctx)->blit_mem, 0x100, 0, 0);
676
677 emit->streamout_mask |= (1 << i);
678 }
679
680 if (emit->streamout_mask) {
681 const struct fd6_streamout_state *tf = &prog->tf;
682
683 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * tf->prog_count));
684 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
685 OUT_RING(ring, tf->vpc_so_buf_cntl);
686 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0));
687 OUT_RING(ring, tf->ncomp[0]);
688 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1));
689 OUT_RING(ring, tf->ncomp[1]);
690 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(2));
691 OUT_RING(ring, tf->ncomp[2]);
692 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3));
693 OUT_RING(ring, tf->ncomp[3]);
694 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
695 OUT_RING(ring, A6XX_VPC_SO_CNTL_ENABLE);
696 for (unsigned i = 0; i < tf->prog_count; i++) {
697 OUT_RING(ring, REG_A6XX_VPC_SO_PROG);
698 OUT_RING(ring, tf->prog[i]);
699 }
700
701 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
702 OUT_RING(ring, 0x0);
703 } else {
704 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 4);
705 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
706 OUT_RING(ring, 0);
707 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
708 OUT_RING(ring, 0);
709
710 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
711 OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
712 }
713
714 }
715
716 void
717 fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
718 {
719 struct fd_context *ctx = emit->ctx;
720 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
721 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
722 const struct ir3_shader_variant *vp = emit->vs;
723 const struct ir3_shader_variant *fp = emit->fs;
724 const enum fd_dirty_3d_state dirty = emit->dirty;
725 bool needs_border = false;
726
727 emit_marker6(ring, 5);
728
729 if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE)) {
730 struct fd_ringbuffer *state;
731
732 state = build_vbo_state(emit, emit->vs);
733 fd6_emit_add_group(emit, state, FD6_GROUP_VBO, 0x6);
734 fd_ringbuffer_del(state);
735
736 state = build_vbo_state(emit, emit->bs);
737 fd6_emit_add_group(emit, state, FD6_GROUP_VBO_BINNING, 0x1);
738 fd_ringbuffer_del(state);
739 }
740
741 if (dirty & FD_DIRTY_ZSA) {
742 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
743
744 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
745 fd6_emit_add_group(emit, zsa->stateobj_no_alpha, FD6_GROUP_ZSA, 0x7);
746 else
747 fd6_emit_add_group(emit, zsa->stateobj, FD6_GROUP_ZSA, 0x7);
748 }
749
750 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && pfb->zsbuf) {
751 struct fd_ringbuffer *state;
752
753 state = build_lrz(emit, false);
754 fd6_emit_add_group(emit, state, FD6_GROUP_LRZ, 0x6);
755 fd_ringbuffer_del(state);
756
757 state = build_lrz(emit, true);
758 fd6_emit_add_group(emit, state, FD6_GROUP_LRZ_BINNING, 0x1);
759 fd_ringbuffer_del(state);
760 }
761
762 if (dirty & FD_DIRTY_STENCIL_REF) {
763 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
764
765 OUT_PKT4(ring, REG_A6XX_RB_STENCILREF, 1);
766 OUT_RING(ring, A6XX_RB_STENCILREF_REF(sr->ref_value[0]) |
767 A6XX_RB_STENCILREF_BFREF(sr->ref_value[1]));
768 }
769
770 /* NOTE: scissor enabled bit is part of rasterizer state: */
771 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
772 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
773
774 OUT_PKT4(ring, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
775 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
776 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
777 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
778 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
779
780 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
781 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
782 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
783 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
784 }
785
786 if (dirty & FD_DIRTY_VIEWPORT) {
787 struct pipe_scissor_state *scissor = &ctx->viewport_scissor;
788
789 OUT_PKT4(ring, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
790 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
791 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
792 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
793 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
794 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
795 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
796
797 OUT_PKT4(ring, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
798 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
799 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
800 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
801 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
802
803 unsigned guardband_x = fd_calc_guardband(scissor->maxx - scissor->minx);
804 unsigned guardband_y = fd_calc_guardband(scissor->maxy - scissor->miny);
805
806 OUT_PKT4(ring, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
807 OUT_RING(ring, A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_x) |
808 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_y));
809 }
810
811 if (dirty & FD_DIRTY_PROG) {
812 fd6_emit_add_group(emit, prog->stateobj, FD6_GROUP_PROG, 0x6);
813 fd6_emit_add_group(emit, prog->binning_stateobj,
814 FD6_GROUP_PROG_BINNING, 0x1);
815
816 /* emit remaining non-stateobj program state, ie. what depends
817 * on other emit state, so cannot be pre-baked. This could
818 * be moved to a separate stateobj which is dynamically
819 * created.
820 */
821 fd6_program_emit(ring, emit);
822 }
823
824 if (dirty & FD_DIRTY_RASTERIZER) {
825 struct fd6_rasterizer_stateobj *rasterizer =
826 fd6_rasterizer_stateobj(ctx->rasterizer);
827 fd6_emit_add_group(emit, rasterizer->stateobj,
828 FD6_GROUP_RASTERIZER, 0x7);
829 }
830
831 /* Since the primitive restart state is not part of a tracked object, we
832 * re-emit this register every time.
833 */
834 if (emit->info && ctx->rasterizer) {
835 struct fd6_rasterizer_stateobj *rasterizer =
836 fd6_rasterizer_stateobj(ctx->rasterizer);
837 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9806, 1);
838 OUT_RING(ring, 0);
839 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9990, 1);
840 OUT_RING(ring, 0);
841 OUT_PKT4(ring, REG_A6XX_VFD_UNKNOWN_A008, 1);
842 OUT_RING(ring, 0);
843
844 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
845 OUT_RING(ring, rasterizer->pc_primitive_cntl |
846 COND(emit->info->primitive_restart && emit->info->index_size,
847 A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART));
848 }
849
850 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
851 unsigned nr = pfb->nr_cbufs;
852
853 if (ctx->rasterizer->rasterizer_discard)
854 nr = 0;
855
856 OUT_PKT4(ring, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
857 OUT_RING(ring, COND(fp->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z));
858 OUT_RING(ring, A6XX_RB_FS_OUTPUT_CNTL1_MRT(nr));
859
860 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL1, 1);
861 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL1_MRT(nr));
862 }
863
864 #define DIRTY_CONST (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST | \
865 FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)
866
867 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & DIRTY_CONST) {
868 struct fd_ringbuffer *vsconstobj = fd_submit_new_ringbuffer(
869 ctx->batch->submit, 0x1000, FD_RINGBUFFER_STREAMING);
870
871 OUT_WFI5(vsconstobj);
872 ir3_emit_vs_consts(vp, vsconstobj, ctx, emit->info);
873 fd6_emit_add_group(emit, vsconstobj, FD6_GROUP_VS_CONST, 0x7);
874 fd_ringbuffer_del(vsconstobj);
875 }
876
877 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & DIRTY_CONST) {
878 struct fd_ringbuffer *fsconstobj = fd_submit_new_ringbuffer(
879 ctx->batch->submit, 0x1000, FD_RINGBUFFER_STREAMING);
880
881 OUT_WFI5(fsconstobj);
882 ir3_emit_fs_consts(fp, fsconstobj, ctx);
883 fd6_emit_add_group(emit, fsconstobj, FD6_GROUP_FS_CONST, 0x6);
884 fd_ringbuffer_del(fsconstobj);
885 }
886
887 struct ir3_stream_output_info *info = &vp->shader->stream_output;
888 if (info->num_outputs)
889 fd6_emit_streamout(ring, emit, info);
890
891 if (dirty & FD_DIRTY_BLEND) {
892 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
893 uint32_t i;
894
895 for (i = 0; i < pfb->nr_cbufs; i++) {
896 enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
897 bool is_int = util_format_is_pure_integer(format);
898 bool has_alpha = util_format_has_alpha(format);
899 uint32_t control = blend->rb_mrt[i].control;
900 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
901
902 if (is_int) {
903 control &= A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
904 control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
905 }
906
907 if (has_alpha) {
908 blend_control |= blend->rb_mrt[i].blend_control_rgb;
909 } else {
910 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
911 control &= ~A6XX_RB_MRT_CONTROL_BLEND2;
912 }
913
914 OUT_PKT4(ring, REG_A6XX_RB_MRT_CONTROL(i), 1);
915 OUT_RING(ring, control);
916
917 OUT_PKT4(ring, REG_A6XX_RB_MRT_BLEND_CONTROL(i), 1);
918 OUT_RING(ring, blend_control);
919 }
920
921 OUT_PKT4(ring, REG_A6XX_SP_BLEND_CNTL, 1);
922 OUT_RING(ring, blend->sp_blend_cntl);
923 }
924
925 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK)) {
926 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
927
928 OUT_PKT4(ring, REG_A6XX_RB_BLEND_CNTL, 1);
929 OUT_RING(ring, blend->rb_blend_cntl |
930 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(ctx->sample_mask));
931 }
932
933 if (dirty & FD_DIRTY_BLEND_COLOR) {
934 struct pipe_blend_color *bcolor = &ctx->blend_color;
935
936 OUT_PKT4(ring, REG_A6XX_RB_BLEND_RED_F32, 4);
937 OUT_RING(ring, A6XX_RB_BLEND_RED_F32(bcolor->color[0]));
938 OUT_RING(ring, A6XX_RB_BLEND_GREEN_F32(bcolor->color[1]));
939 OUT_RING(ring, A6XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
940 OUT_RING(ring, A6XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
941 }
942
943 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_VERTEX, vp);
944 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_FRAGMENT, fp);
945
946 if (needs_border)
947 emit_border_color(ctx, ring);
948
949 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] &
950 (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)) {
951 struct fd_ringbuffer *state =
952 fd6_build_ibo_state(ctx, fp, PIPE_SHADER_FRAGMENT);
953 struct fd_ringbuffer *obj = fd_submit_new_ringbuffer(
954 ctx->batch->submit, 9 * 4, FD_RINGBUFFER_STREAMING);
955 const struct ir3_ibo_mapping *mapping = &fp->image_mapping;
956
957 OUT_PKT7(obj, CP_LOAD_STATE6, 3);
958 OUT_RING(obj, CP_LOAD_STATE6_0_DST_OFF(0) |
959 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
960 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
961 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_IBO) |
962 CP_LOAD_STATE6_0_NUM_UNIT(mapping->num_ibo));
963 OUT_RB(obj, state);
964
965 OUT_PKT4(obj, REG_A6XX_SP_IBO_LO, 2);
966 OUT_RB(obj, state);
967
968 OUT_PKT4(obj, REG_A6XX_SP_IBO_COUNT, 1);
969 OUT_RING(obj, mapping->num_ibo);
970
971 fd6_emit_add_group(emit, obj, FD6_GROUP_IBO, 0x7);
972 fd_ringbuffer_del(obj);
973 fd_ringbuffer_del(state);
974 }
975
976 if (emit->num_groups > 0) {
977 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3 * emit->num_groups);
978 for (unsigned i = 0; i < emit->num_groups; i++) {
979 struct fd6_state_group *g = &emit->groups[i];
980 unsigned n = fd_ringbuffer_size(g->stateobj) / 4;
981
982 if (n == 0) {
983 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
984 CP_SET_DRAW_STATE__0_DISABLE |
985 CP_SET_DRAW_STATE__0_ENABLE_MASK(g->enable_mask) |
986 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
987 OUT_RING(ring, 0x00000000);
988 OUT_RING(ring, 0x00000000);
989 } else {
990 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(n) |
991 CP_SET_DRAW_STATE__0_ENABLE_MASK(g->enable_mask) |
992 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
993 OUT_RB(ring, g->stateobj);
994 }
995
996 fd_ringbuffer_del(g->stateobj);
997 }
998 emit->num_groups = 0;
999 }
1000 }
1001
1002 void
1003 fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
1004 struct ir3_shader_variant *cp)
1005 {
1006 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
1007
1008 if (dirty & (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
1009 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) {
1010 struct fd_texture_stateobj *tex = &ctx->tex[PIPE_SHADER_COMPUTE];
1011 struct fd_shaderbuf_stateobj *buf = &ctx->shaderbuf[PIPE_SHADER_COMPUTE];
1012 struct fd_shaderimg_stateobj *img = &ctx->shaderimg[PIPE_SHADER_COMPUTE];
1013 unsigned bcolor_offset = fd6_border_color_offset(ctx, SB6_CS_TEX, tex);
1014
1015 bool needs_border = fd6_emit_textures(ctx->pipe, ring, SB6_CS_TEX, tex,
1016 bcolor_offset, cp, buf, img);
1017
1018 if (needs_border)
1019 emit_border_color(ctx, ring);
1020
1021 OUT_PKT4(ring, REG_A6XX_SP_VS_TEX_COUNT, 1);
1022 OUT_RING(ring, 0);
1023
1024 OUT_PKT4(ring, REG_A6XX_SP_HS_TEX_COUNT, 1);
1025 OUT_RING(ring, 0);
1026
1027 OUT_PKT4(ring, REG_A6XX_SP_DS_TEX_COUNT, 1);
1028 OUT_RING(ring, 0);
1029
1030 OUT_PKT4(ring, REG_A6XX_SP_GS_TEX_COUNT, 1);
1031 OUT_RING(ring, 0);
1032
1033 OUT_PKT4(ring, REG_A6XX_SP_FS_TEX_COUNT, 1);
1034 OUT_RING(ring, 0);
1035 }
1036
1037 if (dirty & (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)) {
1038 struct fd_ringbuffer *state =
1039 fd6_build_ibo_state(ctx, cp, PIPE_SHADER_COMPUTE);
1040 const struct ir3_ibo_mapping *mapping = &cp->image_mapping;
1041
1042 OUT_PKT7(ring, CP_LOAD_STATE6_FRAG, 3);
1043 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
1044 CP_LOAD_STATE6_0_STATE_TYPE(ST6_IBO) |
1045 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1046 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_CS_SHADER) |
1047 CP_LOAD_STATE6_0_NUM_UNIT(mapping->num_ibo));
1048 OUT_RB(ring, state);
1049
1050 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_LO, 2);
1051 OUT_RB(ring, state);
1052
1053 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_COUNT, 1);
1054 OUT_RING(ring, mapping->num_ibo);
1055
1056 fd_ringbuffer_del(state);
1057 }
1058 }
1059
1060
1061 /* emit setup at begin of new cmdstream buffer (don't rely on previous
1062 * state, there could have been a context switch between ioctls):
1063 */
1064 void
1065 fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
1066 {
1067 //struct fd_context *ctx = batch->ctx;
1068
1069 fd6_cache_inv(batch, ring);
1070
1071 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1072 OUT_RING(ring, 0xfffff);
1073
1074 /*
1075 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
1076 0000000500024048: 70d08003 00000000 001c5000 00000005
1077 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
1078 0000000500024058: 70d08003 00000010 001c7000 00000005
1079
1080 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
1081 0000000500024068: 70268000
1082 */
1083
1084 WRITE(REG_A6XX_RB_CCU_CNTL, 0x7c400004);
1085 WRITE(REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
1086 WRITE(REG_A6XX_SP_UNKNOWN_AE04, 0x8);
1087 WRITE(REG_A6XX_SP_UNKNOWN_AE00, 0);
1088 WRITE(REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
1089 WRITE(REG_A6XX_SP_UNKNOWN_B605, 0x44);
1090 WRITE(REG_A6XX_SP_UNKNOWN_B600, 0x100000);
1091 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
1092 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
1093
1094 WRITE(REG_A6XX_VPC_UNKNOWN_9600, 0);
1095 WRITE(REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
1096 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
1097 WRITE(REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
1098 WRITE(REG_A6XX_SP_IBO_COUNT, 0);
1099 WRITE(REG_A6XX_SP_UNKNOWN_B182, 0);
1100 WRITE(REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
1101 WRITE(REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
1102 WRITE(REG_A6XX_UCHE_CLIENT_PF, 4);
1103 WRITE(REG_A6XX_RB_UNKNOWN_8E01, 0x0);
1104 WRITE(REG_A6XX_SP_UNKNOWN_AB00, 0x5);
1105 WRITE(REG_A6XX_VFD_UNKNOWN_A009, 0x00000001);
1106 WRITE(REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
1107 WRITE(REG_A6XX_PC_MODE_CNTL, 0x1f);
1108
1109 OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
1110 OUT_RING(ring, 0);
1111
1112 WRITE(REG_A6XX_GRAS_UNKNOWN_8101, 0);
1113 WRITE(REG_A6XX_GRAS_UNKNOWN_8109, 0);
1114 WRITE(REG_A6XX_GRAS_UNKNOWN_8110, 0);
1115
1116 WRITE(REG_A6XX_RB_RENDER_CONTROL0, 0x401);
1117 WRITE(REG_A6XX_RB_RENDER_CONTROL1, 0);
1118 WRITE(REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
1119 WRITE(REG_A6XX_RB_UNKNOWN_8810, 0);
1120 WRITE(REG_A6XX_RB_UNKNOWN_8818, 0);
1121 WRITE(REG_A6XX_RB_UNKNOWN_8819, 0);
1122 WRITE(REG_A6XX_RB_UNKNOWN_881A, 0);
1123 WRITE(REG_A6XX_RB_UNKNOWN_881B, 0);
1124 WRITE(REG_A6XX_RB_UNKNOWN_881C, 0);
1125 WRITE(REG_A6XX_RB_UNKNOWN_881D, 0);
1126 WRITE(REG_A6XX_RB_UNKNOWN_881E, 0);
1127 WRITE(REG_A6XX_RB_UNKNOWN_88F0, 0);
1128
1129 WRITE(REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
1130 WRITE(REG_A6XX_VPC_UNKNOWN_9107, 0);
1131
1132 WRITE(REG_A6XX_VPC_UNKNOWN_9236,
1133 A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(0));
1134 WRITE(REG_A6XX_VPC_UNKNOWN_9300, 0);
1135
1136 WRITE(REG_A6XX_VPC_SO_OVERRIDE, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
1137
1138 WRITE(REG_A6XX_PC_UNKNOWN_9801, 0);
1139 WRITE(REG_A6XX_PC_UNKNOWN_9806, 0);
1140 WRITE(REG_A6XX_PC_UNKNOWN_9980, 0);
1141
1142 WRITE(REG_A6XX_PC_UNKNOWN_9B06, 0);
1143 WRITE(REG_A6XX_PC_UNKNOWN_9B06, 0);
1144
1145 WRITE(REG_A6XX_SP_UNKNOWN_A81B, 0);
1146
1147 WRITE(REG_A6XX_SP_UNKNOWN_B183, 0);
1148
1149 WRITE(REG_A6XX_GRAS_UNKNOWN_8099, 0);
1150 WRITE(REG_A6XX_GRAS_UNKNOWN_809B, 0);
1151 WRITE(REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1152 WRITE(REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1153 WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
1154 WRITE(REG_A6XX_VPC_UNKNOWN_9211, 0);
1155 WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
1156 WRITE(REG_A6XX_PC_UNKNOWN_9981, 0x3);
1157 WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
1158 WRITE(REG_A6XX_VPC_UNKNOWN_9108, 0x3);
1159 WRITE(REG_A6XX_SP_TP_UNKNOWN_B304, 0);
1160 WRITE(REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
1161 WRITE(REG_A6XX_RB_UNKNOWN_8804, 0);
1162 WRITE(REG_A6XX_GRAS_UNKNOWN_80A4, 0);
1163 WRITE(REG_A6XX_GRAS_UNKNOWN_80A5, 0);
1164 WRITE(REG_A6XX_GRAS_UNKNOWN_80A6, 0);
1165 WRITE(REG_A6XX_RB_UNKNOWN_8805, 0);
1166 WRITE(REG_A6XX_RB_UNKNOWN_8806, 0);
1167 WRITE(REG_A6XX_RB_UNKNOWN_8878, 0);
1168 WRITE(REG_A6XX_RB_UNKNOWN_8879, 0);
1169 WRITE(REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1170
1171 emit_marker6(ring, 7);
1172
1173 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
1174 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
1175
1176 WRITE(REG_A6XX_VFD_UNKNOWN_A008, 0);
1177
1178 OUT_PKT4(ring, REG_A6XX_PC_MODE_CNTL, 1);
1179 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
1180
1181 /* we don't use this yet.. probably best to disable.. */
1182 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1183 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1184 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1185 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1186 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1187 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1188
1189 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1190 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
1191
1192 OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1);
1193 OUT_RING(ring, 0x00000000);
1194
1195 OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
1196 OUT_RING(ring, 0x00000000);
1197
1198 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1199 OUT_RING(ring, 0x00000000);
1200
1201 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
1202 OUT_RING(ring, 0x00000000);
1203 }
1204
1205 static void
1206 fd6_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
1207 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
1208 unsigned sizedwords)
1209 {
1210 struct fd_bo *src_bo = fd_resource(src)->bo;
1211 struct fd_bo *dst_bo = fd_resource(dst)->bo;
1212 unsigned i;
1213
1214 for (i = 0; i < sizedwords; i++) {
1215 OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
1216 OUT_RING(ring, 0x00000000);
1217 OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
1218 OUT_RELOC (ring, src_bo, src_off, 0, 0);
1219
1220 dst_off += 4;
1221 src_off += 4;
1222 }
1223 }
1224
1225 void
1226 fd6_emit_init(struct pipe_context *pctx)
1227 {
1228 struct fd_context *ctx = fd_context(pctx);
1229 ctx->emit_const = fd6_emit_const;
1230 ctx->emit_const_bo = fd6_emit_const_bo;
1231 ctx->emit_ib = fd6_emit_ib;
1232 ctx->mem_to_mem = fd6_mem_to_mem;
1233 }