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freedreno/a6xx: more bcolor fixes
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_helpers.h"
32 #include "util/u_format.h"
33 #include "util/u_viewport.h"
34
35 #include "freedreno_resource.h"
36 #include "freedreno_query_hw.h"
37
38 #include "fd6_emit.h"
39 #include "fd6_blend.h"
40 #include "fd6_context.h"
41 #include "fd6_image.h"
42 #include "fd6_program.h"
43 #include "fd6_rasterizer.h"
44 #include "fd6_texture.h"
45 #include "fd6_format.h"
46 #include "fd6_zsa.h"
47
48 static uint32_t
49 shader_t_to_opcode(gl_shader_stage type)
50 {
51 switch (type) {
52 case MESA_SHADER_VERTEX:
53 case MESA_SHADER_TESS_CTRL:
54 case MESA_SHADER_TESS_EVAL:
55 case MESA_SHADER_GEOMETRY:
56 return CP_LOAD_STATE6_GEOM;
57 case MESA_SHADER_FRAGMENT:
58 case MESA_SHADER_COMPUTE:
59 case MESA_SHADER_KERNEL:
60 return CP_LOAD_STATE6_FRAG;
61 default:
62 unreachable("bad shader type");
63 }
64 }
65
66 /* regid: base const register
67 * prsc or dwords: buffer containing constant values
68 * sizedwords: size of const value buffer
69 */
70 static void
71 fd6_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
72 uint32_t regid, uint32_t offset, uint32_t sizedwords,
73 const uint32_t *dwords, struct pipe_resource *prsc)
74 {
75 uint32_t i, sz;
76 enum a6xx_state_src src;
77
78 debug_assert((regid % 4) == 0);
79 debug_assert((sizedwords % 4) == 0);
80
81 if (prsc) {
82 sz = 0;
83 src = SS6_INDIRECT;
84 } else {
85 sz = sizedwords;
86 src = SS6_DIRECT;
87 }
88
89 OUT_PKT7(ring, shader_t_to_opcode(type), 3 + sz);
90 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
91 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
92 CP_LOAD_STATE6_0_STATE_SRC(src) |
93 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
94 CP_LOAD_STATE6_0_NUM_UNIT(sizedwords/4));
95 if (prsc) {
96 struct fd_bo *bo = fd_resource(prsc)->bo;
97 OUT_RELOC(ring, bo, offset, 0, 0);
98 } else {
99 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
100 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
101 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
102 }
103 for (i = 0; i < sz; i++) {
104 OUT_RING(ring, dwords[i]);
105 }
106 }
107
108 static void
109 fd6_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
110 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
111 {
112 uint32_t anum = align(num, 2);
113 uint32_t i;
114
115 debug_assert((regid % 4) == 0);
116
117 OUT_PKT7(ring, shader_t_to_opcode(type), 3 + (2 * anum));
118 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
119 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS)|
120 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
121 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
122 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
123 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
124 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
125
126 for (i = 0; i < num; i++) {
127 if (prscs[i]) {
128 if (write) {
129 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
130 } else {
131 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
132 }
133 } else {
134 OUT_RING(ring, 0xbad00000 | (i << 16));
135 OUT_RING(ring, 0xbad00000 | (i << 16));
136 }
137 }
138
139 for (; i < anum; i++) {
140 OUT_RING(ring, 0xffffffff);
141 OUT_RING(ring, 0xffffffff);
142 }
143 }
144
145 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
146 * the same as a6xx then move this somewhere common ;-)
147 *
148 * Entry layout looks like (total size, 0x60 bytes):
149 */
150
151 struct PACKED bcolor_entry {
152 uint32_t fp32[4];
153 uint16_t ui16[4];
154 int16_t si16[4];
155 uint16_t fp16[4];
156 uint16_t rgb565;
157 uint16_t rgb5a1;
158 uint16_t rgba4;
159 uint8_t __pad0[2];
160 uint8_t ui8[4];
161 int8_t si8[4];
162 uint32_t rgb10a2;
163 uint32_t z24; /* also s8? */
164 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
165 uint8_t __pad1[56];
166 };
167
168 #define FD6_BORDER_COLOR_SIZE sizeof(struct bcolor_entry)
169 #define FD6_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD6_BORDER_COLOR_SIZE)
170
171 static void
172 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
173 {
174 unsigned i, j;
175 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
176
177 for (i = 0; i < tex->num_samplers; i++) {
178 struct bcolor_entry *e = &entries[i];
179 struct pipe_sampler_state *sampler = tex->samplers[i];
180 union pipe_color_union *bc;
181
182 if (!sampler)
183 continue;
184
185 bc = &sampler->border_color;
186
187 /*
188 * XXX HACK ALERT XXX
189 *
190 * The border colors need to be swizzled in a particular
191 * format-dependent order. Even though samplers don't know about
192 * formats, we can assume that with a GL state tracker, there's a
193 * 1:1 correspondence between sampler and texture. Take advantage
194 * of that knowledge.
195 */
196 if ((i >= tex->num_textures) || !tex->textures[i])
197 continue;
198
199 struct pipe_sampler_view *view = tex->textures[i];
200 enum pipe_format format = view->format;
201 const struct util_format_description *desc =
202 util_format_description(format);
203
204 e->rgb565 = 0;
205 e->rgb5a1 = 0;
206 e->rgba4 = 0;
207 e->rgb10a2 = 0;
208 e->z24 = 0;
209
210 unsigned char swiz[4];
211
212 fd6_tex_swiz(format, swiz,
213 view->swizzle_r, view->swizzle_g,
214 view->swizzle_b, view->swizzle_a);
215
216 for (j = 0; j < 4; j++) {
217 int c = swiz[j];
218 int cd = c;
219
220 /*
221 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the
222 * stencil border color value in bc->ui[0] but according
223 * to desc->swizzle and desc->channel, the .x component
224 * is NONE and the stencil value is in the y component.
225 * Meanwhile the hardware wants this in the .x componetn.
226 */
227 if ((format == PIPE_FORMAT_X24S8_UINT) ||
228 (format == PIPE_FORMAT_X32_S8X24_UINT)) {
229 if (j == 0) {
230 c = 1;
231 cd = 0;
232 } else {
233 continue;
234 }
235 }
236
237 if (c >= 4)
238 continue;
239
240 if (desc->channel[c].pure_integer) {
241 uint16_t clamped;
242 switch (desc->channel[c].size) {
243 case 2:
244 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
245 clamped = CLAMP(bc->ui[j], 0, 0x3);
246 break;
247 case 8:
248 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
249 clamped = CLAMP(bc->i[j], -128, 127);
250 else
251 clamped = CLAMP(bc->ui[j], 0, 255);
252 break;
253 case 10:
254 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
255 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
256 break;
257 case 16:
258 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
259 clamped = CLAMP(bc->i[j], -32768, 32767);
260 else
261 clamped = CLAMP(bc->ui[j], 0, 65535);
262 break;
263 default:
264 assert(!"Unexpected bit size");
265 case 32:
266 clamped = 0;
267 break;
268 }
269 e->fp32[cd] = bc->ui[j];
270 e->fp16[cd] = clamped;
271 } else {
272 float f = bc->f[j];
273 float f_u = CLAMP(f, 0, 1);
274 float f_s = CLAMP(f, -1, 1);
275
276 e->fp32[c] = fui(f);
277 e->fp16[c] = util_float_to_half(f);
278 e->srgb[c] = util_float_to_half(f_u);
279 e->ui16[c] = f_u * 0xffff;
280 e->si16[c] = f_s * 0x7fff;
281 e->ui8[c] = f_u * 0xff;
282 e->si8[c] = f_s * 0x7f;
283 if (c == 1)
284 e->rgb565 |= (int)(f_u * 0x3f) << 5;
285 else if (c < 3)
286 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
287 if (c == 3)
288 e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
289 else
290 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
291 if (c == 3)
292 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
293 else
294 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
295 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
296 if (c == 0)
297 e->z24 = f_u * 0xffffff;
298 }
299 }
300
301 #ifdef DEBUG
302 memset(&e->__pad0, 0, sizeof(e->__pad0));
303 memset(&e->__pad1, 0, sizeof(e->__pad1));
304 #endif
305 }
306 }
307
308 static void
309 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
310 {
311 struct fd6_context *fd6_ctx = fd6_context(ctx);
312 struct bcolor_entry *entries;
313 unsigned off;
314 void *ptr;
315
316 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
317
318 u_upload_alloc(fd6_ctx->border_color_uploader,
319 0, FD6_BORDER_COLOR_UPLOAD_SIZE,
320 FD6_BORDER_COLOR_UPLOAD_SIZE, &off,
321 &fd6_ctx->border_color_buf,
322 &ptr);
323
324 entries = ptr;
325
326 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
327 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
328 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
329
330 OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
331 OUT_RELOC(ring, fd_resource(fd6_ctx->border_color_buf)->bo, off, 0, 0);
332
333 u_upload_unmap(fd6_ctx->border_color_uploader);
334 }
335
336 bool
337 fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
338 enum a6xx_state_block sb, struct fd_texture_stateobj *tex,
339 unsigned bcolor_offset,
340 /* can be NULL if no image/SSBO state to merge in: */
341 const struct ir3_shader_variant *v, struct fd_shaderbuf_stateobj *buf,
342 struct fd_shaderimg_stateobj *img)
343 {
344 bool needs_border = false;
345 unsigned opcode, tex_samp_reg, tex_const_reg, tex_count_reg;
346
347 switch (sb) {
348 case SB6_VS_TEX:
349 opcode = CP_LOAD_STATE6_GEOM;
350 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
351 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
352 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
353 break;
354 case SB6_FS_TEX:
355 opcode = CP_LOAD_STATE6_FRAG;
356 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
357 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
358 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
359 break;
360 case SB6_CS_TEX:
361 opcode = CP_LOAD_STATE6_FRAG;
362 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
363 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
364 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
365 break;
366 default:
367 unreachable("bad state block");
368 }
369
370 if (tex->num_samplers > 0) {
371 struct fd_ringbuffer *state =
372 fd_ringbuffer_new_object(pipe, tex->num_samplers * 4 * 4);
373 for (unsigned i = 0; i < tex->num_samplers; i++) {
374 static const struct fd6_sampler_stateobj dummy_sampler = {};
375 const struct fd6_sampler_stateobj *sampler = tex->samplers[i] ?
376 fd6_sampler_stateobj(tex->samplers[i]) : &dummy_sampler;
377 OUT_RING(state, sampler->texsamp0);
378 OUT_RING(state, sampler->texsamp1);
379 OUT_RING(state, sampler->texsamp2 |
380 A6XX_TEX_SAMP_2_BCOLOR_OFFSET((i + bcolor_offset) * sizeof(struct bcolor_entry)));
381 OUT_RING(state, sampler->texsamp3);
382 needs_border |= sampler->needs_border;
383 }
384
385 /* output sampler state: */
386 OUT_PKT7(ring, opcode, 3);
387 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
388 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
389 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
390 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
391 CP_LOAD_STATE6_0_NUM_UNIT(tex->num_samplers));
392 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
393
394 OUT_PKT4(ring, tex_samp_reg, 2);
395 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
396
397 fd_ringbuffer_del(state);
398 }
399
400 unsigned num_merged_textures = tex->num_textures;
401 unsigned num_textures = tex->num_textures;
402 if (v) {
403 num_merged_textures += v->image_mapping.num_tex;
404
405 /* There could be more bound textures than what the shader uses.
406 * Which isn't known at shader compile time. So in the case we
407 * are merging tex state, only emit the textures that the shader
408 * uses (since the image/SSBO related tex state comes immediately
409 * after)
410 */
411 num_textures = v->image_mapping.tex_base;
412 }
413
414 if (num_merged_textures > 0) {
415 struct fd_ringbuffer *state =
416 fd_ringbuffer_new_object(pipe, num_merged_textures * 16 * 4);
417 for (unsigned i = 0; i < num_textures; i++) {
418 static const struct fd6_pipe_sampler_view dummy_view = {};
419 const struct fd6_pipe_sampler_view *view = tex->textures[i] ?
420 fd6_pipe_sampler_view(tex->textures[i]) : &dummy_view;
421 struct fd_resource *rsc = NULL;
422
423 if (view->base.texture)
424 rsc = fd_resource(view->base.texture);
425
426 OUT_RING(state, view->texconst0);
427 OUT_RING(state, view->texconst1);
428 OUT_RING(state, view->texconst2);
429 OUT_RING(state, view->texconst3 |
430 COND(rsc && view->ubwc_enabled,
431 A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_UNK27));
432
433 if (rsc) {
434 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
435 rsc = rsc->stencil;
436 OUT_RELOC(state, rsc->bo, view->offset + rsc->offset,
437 (uint64_t)view->texconst5 << 32, 0);
438 } else {
439 OUT_RING(state, 0x00000000);
440 OUT_RING(state, view->texconst5);
441 }
442
443 OUT_RING(state, view->texconst6);
444
445 if (rsc && view->ubwc_enabled) {
446 OUT_RELOC(state, rsc->bo, view->offset + rsc->ubwc_offset, 0, 0);
447 } else {
448 OUT_RING(state, 0);
449 OUT_RING(state, 0);
450 }
451
452 OUT_RING(state, view->texconst9);
453 OUT_RING(state, view->texconst10);
454 OUT_RING(state, view->texconst11);
455 OUT_RING(state, 0);
456 OUT_RING(state, 0);
457 OUT_RING(state, 0);
458 OUT_RING(state, 0);
459 }
460
461 if (v) {
462 const struct ir3_ibo_mapping *mapping = &v->image_mapping;
463
464 for (unsigned i = 0; i < mapping->num_tex; i++) {
465 unsigned idx = mapping->tex_to_image[i];
466 if (idx & IBO_SSBO) {
467 fd6_emit_ssbo_tex(state, &buf->sb[idx & ~IBO_SSBO]);
468 } else {
469 fd6_emit_image_tex(state, &img->si[idx]);
470 }
471 }
472 }
473
474 /* emit texture state: */
475 OUT_PKT7(ring, opcode, 3);
476 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
477 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
478 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
479 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
480 CP_LOAD_STATE6_0_NUM_UNIT(num_merged_textures));
481 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
482
483 OUT_PKT4(ring, tex_const_reg, 2);
484 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
485
486 fd_ringbuffer_del(state);
487 }
488
489 OUT_PKT4(ring, tex_count_reg, 1);
490 OUT_RING(ring, num_merged_textures);
491
492 return needs_border;
493 }
494
495 /* Emits combined texture state, which also includes any Image/SSBO
496 * related texture state merged in (because we must have all texture
497 * state for a given stage in a single buffer). In the fast-path, if
498 * we don't need to merge in any image/ssbo related texture state, we
499 * just use cached texture stateobj. Otherwise we generate a single-
500 * use stateobj.
501 *
502 * TODO Is there some sane way we can still use cached texture stateobj
503 * with image/ssbo in use?
504 *
505 * returns whether border_color is required:
506 */
507 static bool
508 fd6_emit_combined_textures(struct fd_ringbuffer *ring, struct fd6_emit *emit,
509 enum pipe_shader_type type, const struct ir3_shader_variant *v)
510 {
511 struct fd_context *ctx = emit->ctx;
512 bool needs_border = false;
513
514 static const struct {
515 enum a6xx_state_block sb;
516 enum fd6_state_id state_id;
517 } s[PIPE_SHADER_TYPES] = {
518 [PIPE_SHADER_VERTEX] = { SB6_VS_TEX, FD6_GROUP_VS_TEX },
519 [PIPE_SHADER_FRAGMENT] = { SB6_FS_TEX, FD6_GROUP_FS_TEX },
520 };
521
522 debug_assert(s[type].state_id);
523
524 if (!v->image_mapping.num_tex) {
525 /* in the fast-path, when we don't have to mix in any image/SSBO
526 * related texture state, we can just lookup the stateobj and
527 * re-emit that:
528 */
529 if ((ctx->dirty_shader[type] & FD_DIRTY_SHADER_TEX) &&
530 ctx->tex[type].num_textures > 0) {
531 struct fd6_texture_state *tex = fd6_texture_state(ctx,
532 s[type].sb, &ctx->tex[type]);
533
534 needs_border |= tex->needs_border;
535
536 fd6_emit_add_group(emit, tex->stateobj, s[type].state_id, 0x7);
537 }
538 } else {
539 /* In the slow-path, create a one-shot texture state object
540 * if either TEX|PROG|SSBO|IMAGE state is dirty:
541 */
542 if (ctx->dirty_shader[type] &
543 (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
544 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) {
545 struct fd_texture_stateobj *tex = &ctx->tex[type];
546 struct fd_shaderbuf_stateobj *buf = &ctx->shaderbuf[type];
547 struct fd_shaderimg_stateobj *img = &ctx->shaderimg[type];
548 struct fd_ringbuffer *stateobj =
549 fd_submit_new_ringbuffer(ctx->batch->submit,
550 0x1000, FD_RINGBUFFER_STREAMING);
551 unsigned bcolor_offset =
552 fd6_border_color_offset(ctx, s[type].sb, tex);
553
554 needs_border |= fd6_emit_textures(ctx->pipe, stateobj, s[type].sb, tex,
555 bcolor_offset, v, buf, img);
556
557 fd6_emit_add_group(emit, stateobj, s[type].state_id, 0x7);
558
559 fd_ringbuffer_del(stateobj);
560 }
561 }
562
563 return needs_border;
564 }
565
566 static struct fd_ringbuffer *
567 build_vbo_state(struct fd6_emit *emit, const struct ir3_shader_variant *vp)
568 {
569 const struct fd_vertex_state *vtx = emit->vtx;
570 int32_t i, j;
571
572 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
573 4 * (10 * vp->inputs_count + 2), FD_RINGBUFFER_STREAMING);
574
575 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
576 if (vp->inputs[i].sysval)
577 continue;
578 if (vp->inputs[i].compmask) {
579 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
580 const struct pipe_vertex_buffer *vb =
581 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
582 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
583 enum pipe_format pfmt = elem->src_format;
584 enum a6xx_vtx_fmt fmt = fd6_pipe2vtx(pfmt);
585 bool isint = util_format_is_pure_integer(pfmt);
586 uint32_t off = vb->buffer_offset + elem->src_offset;
587 uint32_t size = fd_bo_size(rsc->bo) - off;
588 debug_assert(fmt != ~0);
589
590 #ifdef DEBUG
591 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
592 */
593 if (off > fd_bo_size(rsc->bo))
594 continue;
595 #endif
596
597 OUT_PKT4(ring, REG_A6XX_VFD_FETCH(j), 4);
598 OUT_RELOC(ring, rsc->bo, off, 0, 0);
599 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
600 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
601
602 OUT_PKT4(ring, REG_A6XX_VFD_DECODE(j), 2);
603 OUT_RING(ring, A6XX_VFD_DECODE_INSTR_IDX(j) |
604 A6XX_VFD_DECODE_INSTR_FORMAT(fmt) |
605 COND(elem->instance_divisor, A6XX_VFD_DECODE_INSTR_INSTANCED) |
606 A6XX_VFD_DECODE_INSTR_SWAP(fd6_pipe2swap(pfmt)) |
607 A6XX_VFD_DECODE_INSTR_UNK30 |
608 COND(!isint, A6XX_VFD_DECODE_INSTR_FLOAT));
609 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
610
611 OUT_PKT4(ring, REG_A6XX_VFD_DEST_CNTL(j), 1);
612 OUT_RING(ring, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
613 A6XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
614
615 j++;
616 }
617 }
618
619 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_0, 1);
620 OUT_RING(ring, A6XX_VFD_CONTROL_0_VTXCNT(j) | (j << 8));
621
622 return ring;
623 }
624
625 static struct fd_ringbuffer *
626 build_lrz(struct fd6_emit *emit, bool binning_pass)
627 {
628 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(emit->ctx->zsa);
629 struct pipe_framebuffer_state *pfb = &emit->ctx->batch->framebuffer;
630 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
631 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
632 uint32_t rb_lrz_cntl = zsa->rb_lrz_cntl;
633
634 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
635 16, FD_RINGBUFFER_STREAMING);
636
637 if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid) {
638 gras_lrz_cntl = 0;
639 rb_lrz_cntl = 0;
640 } else if (binning_pass && zsa->lrz_write) {
641 gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_LRZ_WRITE;
642 }
643
644 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
645 OUT_RING(ring, gras_lrz_cntl);
646
647 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
648 OUT_RING(ring, rb_lrz_cntl);
649
650 return ring;
651 }
652
653 static void
654 fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3_stream_output_info *info)
655 {
656 struct fd_context *ctx = emit->ctx;
657 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
658 struct fd_streamout_stateobj *so = &ctx->streamout;
659
660 emit->streamout_mask = 0;
661
662 for (unsigned i = 0; i < so->num_targets; i++) {
663 struct pipe_stream_output_target *target = so->targets[i];
664
665 if (!target)
666 continue;
667
668 unsigned offset = (so->offsets[i] * info->stride[i] * 4) +
669 target->buffer_offset;
670
671 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(i), 3);
672 /* VPC_SO[i].BUFFER_BASE_LO: */
673 OUT_RELOCW(ring, fd_resource(target->buffer)->bo, 0, 0, 0);
674 OUT_RING(ring, target->buffer_size + offset);
675
676 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(i), 3);
677 OUT_RING(ring, offset);
678 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
679 // TODO just give hw a dummy addr for now.. we should
680 // be using this an then CP_MEM_TO_REG to set the
681 // VPC_SO[i].BUFFER_OFFSET for the next draw..
682 OUT_RELOCW(ring, fd6_context(ctx)->blit_mem, 0x100, 0, 0);
683
684 emit->streamout_mask |= (1 << i);
685 }
686
687 if (emit->streamout_mask) {
688 const struct fd6_streamout_state *tf = &prog->tf;
689
690 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * tf->prog_count));
691 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
692 OUT_RING(ring, tf->vpc_so_buf_cntl);
693 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0));
694 OUT_RING(ring, tf->ncomp[0]);
695 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1));
696 OUT_RING(ring, tf->ncomp[1]);
697 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(2));
698 OUT_RING(ring, tf->ncomp[2]);
699 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3));
700 OUT_RING(ring, tf->ncomp[3]);
701 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
702 OUT_RING(ring, A6XX_VPC_SO_CNTL_ENABLE);
703 for (unsigned i = 0; i < tf->prog_count; i++) {
704 OUT_RING(ring, REG_A6XX_VPC_SO_PROG);
705 OUT_RING(ring, tf->prog[i]);
706 }
707
708 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
709 OUT_RING(ring, 0x0);
710 } else {
711 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 4);
712 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
713 OUT_RING(ring, 0);
714 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
715 OUT_RING(ring, 0);
716
717 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
718 OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
719 }
720
721 }
722
723 void
724 fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
725 {
726 struct fd_context *ctx = emit->ctx;
727 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
728 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
729 const struct ir3_shader_variant *vp = emit->vs;
730 const struct ir3_shader_variant *fp = emit->fs;
731 const enum fd_dirty_3d_state dirty = emit->dirty;
732 bool needs_border = false;
733
734 emit_marker6(ring, 5);
735
736 if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE)) {
737 struct fd_ringbuffer *state;
738
739 state = build_vbo_state(emit, emit->vs);
740 fd6_emit_add_group(emit, state, FD6_GROUP_VBO, 0x6);
741 fd_ringbuffer_del(state);
742
743 state = build_vbo_state(emit, emit->bs);
744 fd6_emit_add_group(emit, state, FD6_GROUP_VBO_BINNING, 0x1);
745 fd_ringbuffer_del(state);
746 }
747
748 if (dirty & FD_DIRTY_ZSA) {
749 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
750
751 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
752 fd6_emit_add_group(emit, zsa->stateobj_no_alpha, FD6_GROUP_ZSA, 0x7);
753 else
754 fd6_emit_add_group(emit, zsa->stateobj, FD6_GROUP_ZSA, 0x7);
755 }
756
757 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && pfb->zsbuf) {
758 struct fd_ringbuffer *state;
759
760 state = build_lrz(emit, false);
761 fd6_emit_add_group(emit, state, FD6_GROUP_LRZ, 0x6);
762 fd_ringbuffer_del(state);
763
764 state = build_lrz(emit, true);
765 fd6_emit_add_group(emit, state, FD6_GROUP_LRZ_BINNING, 0x1);
766 fd_ringbuffer_del(state);
767 }
768
769 if (dirty & FD_DIRTY_STENCIL_REF) {
770 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
771
772 OUT_PKT4(ring, REG_A6XX_RB_STENCILREF, 1);
773 OUT_RING(ring, A6XX_RB_STENCILREF_REF(sr->ref_value[0]) |
774 A6XX_RB_STENCILREF_BFREF(sr->ref_value[1]));
775 }
776
777 /* NOTE: scissor enabled bit is part of rasterizer state: */
778 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
779 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
780
781 OUT_PKT4(ring, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
782 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
783 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
784 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
785 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
786
787 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
788 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
789 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
790 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
791 }
792
793 if (dirty & FD_DIRTY_VIEWPORT) {
794 struct pipe_scissor_state *scissor = &ctx->viewport_scissor;
795
796 OUT_PKT4(ring, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
797 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
798 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
799 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
800 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
801 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
802 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
803
804 OUT_PKT4(ring, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
805 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
806 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
807 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
808 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
809
810 unsigned guardband_x = fd_calc_guardband(scissor->maxx - scissor->minx);
811 unsigned guardband_y = fd_calc_guardband(scissor->maxy - scissor->miny);
812
813 OUT_PKT4(ring, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
814 OUT_RING(ring, A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_x) |
815 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_y));
816 }
817
818 if (dirty & FD_DIRTY_PROG) {
819 fd6_emit_add_group(emit, prog->stateobj, FD6_GROUP_PROG, 0x6);
820 fd6_emit_add_group(emit, prog->binning_stateobj,
821 FD6_GROUP_PROG_BINNING, 0x1);
822
823 /* emit remaining non-stateobj program state, ie. what depends
824 * on other emit state, so cannot be pre-baked. This could
825 * be moved to a separate stateobj which is dynamically
826 * created.
827 */
828 fd6_program_emit(ring, emit);
829 }
830
831 if (dirty & FD_DIRTY_RASTERIZER) {
832 struct fd6_rasterizer_stateobj *rasterizer =
833 fd6_rasterizer_stateobj(ctx->rasterizer);
834 fd6_emit_add_group(emit, rasterizer->stateobj,
835 FD6_GROUP_RASTERIZER, 0x7);
836 }
837
838 /* Since the primitive restart state is not part of a tracked object, we
839 * re-emit this register every time.
840 */
841 if (emit->info && ctx->rasterizer) {
842 struct fd6_rasterizer_stateobj *rasterizer =
843 fd6_rasterizer_stateobj(ctx->rasterizer);
844 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9806, 1);
845 OUT_RING(ring, 0);
846 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9990, 1);
847 OUT_RING(ring, 0);
848 OUT_PKT4(ring, REG_A6XX_VFD_UNKNOWN_A008, 1);
849 OUT_RING(ring, 0);
850
851 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
852 OUT_RING(ring, rasterizer->pc_primitive_cntl |
853 COND(emit->info->primitive_restart && emit->info->index_size,
854 A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART));
855 }
856
857 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
858 unsigned nr = pfb->nr_cbufs;
859
860 if (ctx->rasterizer->rasterizer_discard)
861 nr = 0;
862
863 OUT_PKT4(ring, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
864 OUT_RING(ring, COND(fp->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z));
865 OUT_RING(ring, A6XX_RB_FS_OUTPUT_CNTL1_MRT(nr));
866
867 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL1, 1);
868 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL1_MRT(nr));
869 }
870
871 #define DIRTY_CONST (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST | \
872 FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)
873
874 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & DIRTY_CONST) {
875 struct fd_ringbuffer *vsconstobj = fd_submit_new_ringbuffer(
876 ctx->batch->submit, 0x1000, FD_RINGBUFFER_STREAMING);
877
878 OUT_WFI5(vsconstobj);
879 ir3_emit_vs_consts(vp, vsconstobj, ctx, emit->info);
880 fd6_emit_add_group(emit, vsconstobj, FD6_GROUP_VS_CONST, 0x7);
881 fd_ringbuffer_del(vsconstobj);
882 }
883
884 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & DIRTY_CONST) {
885 struct fd_ringbuffer *fsconstobj = fd_submit_new_ringbuffer(
886 ctx->batch->submit, 0x1000, FD_RINGBUFFER_STREAMING);
887
888 OUT_WFI5(fsconstobj);
889 ir3_emit_fs_consts(fp, fsconstobj, ctx);
890 fd6_emit_add_group(emit, fsconstobj, FD6_GROUP_FS_CONST, 0x6);
891 fd_ringbuffer_del(fsconstobj);
892 }
893
894 struct ir3_stream_output_info *info = &vp->shader->stream_output;
895 if (info->num_outputs)
896 fd6_emit_streamout(ring, emit, info);
897
898 if (dirty & FD_DIRTY_BLEND) {
899 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
900 uint32_t i;
901
902 for (i = 0; i < pfb->nr_cbufs; i++) {
903 enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
904 bool is_int = util_format_is_pure_integer(format);
905 bool has_alpha = util_format_has_alpha(format);
906 uint32_t control = blend->rb_mrt[i].control;
907 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
908
909 if (is_int) {
910 control &= A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
911 control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
912 }
913
914 if (has_alpha) {
915 blend_control |= blend->rb_mrt[i].blend_control_rgb;
916 } else {
917 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
918 control &= ~A6XX_RB_MRT_CONTROL_BLEND2;
919 }
920
921 OUT_PKT4(ring, REG_A6XX_RB_MRT_CONTROL(i), 1);
922 OUT_RING(ring, control);
923
924 OUT_PKT4(ring, REG_A6XX_RB_MRT_BLEND_CONTROL(i), 1);
925 OUT_RING(ring, blend_control);
926 }
927
928 OUT_PKT4(ring, REG_A6XX_SP_BLEND_CNTL, 1);
929 OUT_RING(ring, blend->sp_blend_cntl);
930 }
931
932 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK)) {
933 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
934
935 OUT_PKT4(ring, REG_A6XX_RB_BLEND_CNTL, 1);
936 OUT_RING(ring, blend->rb_blend_cntl |
937 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(ctx->sample_mask));
938 }
939
940 if (dirty & FD_DIRTY_BLEND_COLOR) {
941 struct pipe_blend_color *bcolor = &ctx->blend_color;
942
943 OUT_PKT4(ring, REG_A6XX_RB_BLEND_RED_F32, 4);
944 OUT_RING(ring, A6XX_RB_BLEND_RED_F32(bcolor->color[0]));
945 OUT_RING(ring, A6XX_RB_BLEND_GREEN_F32(bcolor->color[1]));
946 OUT_RING(ring, A6XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
947 OUT_RING(ring, A6XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
948 }
949
950 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_VERTEX, vp);
951 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_FRAGMENT, fp);
952
953 if (needs_border)
954 emit_border_color(ctx, ring);
955
956 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] &
957 (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)) {
958 struct fd_ringbuffer *state =
959 fd6_build_ibo_state(ctx, fp, PIPE_SHADER_FRAGMENT);
960 struct fd_ringbuffer *obj = fd_submit_new_ringbuffer(
961 ctx->batch->submit, 9 * 4, FD_RINGBUFFER_STREAMING);
962 const struct ir3_ibo_mapping *mapping = &fp->image_mapping;
963
964 OUT_PKT7(obj, CP_LOAD_STATE6, 3);
965 OUT_RING(obj, CP_LOAD_STATE6_0_DST_OFF(0) |
966 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
967 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
968 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_IBO) |
969 CP_LOAD_STATE6_0_NUM_UNIT(mapping->num_ibo));
970 OUT_RB(obj, state);
971
972 OUT_PKT4(obj, REG_A6XX_SP_IBO_LO, 2);
973 OUT_RB(obj, state);
974
975 OUT_PKT4(obj, REG_A6XX_SP_IBO_COUNT, 1);
976 OUT_RING(obj, mapping->num_ibo);
977
978 fd6_emit_add_group(emit, obj, FD6_GROUP_IBO, 0x7);
979 fd_ringbuffer_del(obj);
980 fd_ringbuffer_del(state);
981 }
982
983 if (emit->num_groups > 0) {
984 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3 * emit->num_groups);
985 for (unsigned i = 0; i < emit->num_groups; i++) {
986 struct fd6_state_group *g = &emit->groups[i];
987 unsigned n = fd_ringbuffer_size(g->stateobj) / 4;
988
989 if (n == 0) {
990 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
991 CP_SET_DRAW_STATE__0_DISABLE |
992 CP_SET_DRAW_STATE__0_ENABLE_MASK(g->enable_mask) |
993 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
994 OUT_RING(ring, 0x00000000);
995 OUT_RING(ring, 0x00000000);
996 } else {
997 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(n) |
998 CP_SET_DRAW_STATE__0_ENABLE_MASK(g->enable_mask) |
999 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
1000 OUT_RB(ring, g->stateobj);
1001 }
1002
1003 fd_ringbuffer_del(g->stateobj);
1004 }
1005 emit->num_groups = 0;
1006 }
1007 }
1008
1009 void
1010 fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
1011 struct ir3_shader_variant *cp)
1012 {
1013 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
1014
1015 if (dirty & (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
1016 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) {
1017 struct fd_texture_stateobj *tex = &ctx->tex[PIPE_SHADER_COMPUTE];
1018 struct fd_shaderbuf_stateobj *buf = &ctx->shaderbuf[PIPE_SHADER_COMPUTE];
1019 struct fd_shaderimg_stateobj *img = &ctx->shaderimg[PIPE_SHADER_COMPUTE];
1020 unsigned bcolor_offset = fd6_border_color_offset(ctx, SB6_CS_TEX, tex);
1021
1022 bool needs_border = fd6_emit_textures(ctx->pipe, ring, SB6_CS_TEX, tex,
1023 bcolor_offset, cp, buf, img);
1024
1025 if (needs_border)
1026 emit_border_color(ctx, ring);
1027
1028 OUT_PKT4(ring, REG_A6XX_SP_VS_TEX_COUNT, 1);
1029 OUT_RING(ring, 0);
1030
1031 OUT_PKT4(ring, REG_A6XX_SP_HS_TEX_COUNT, 1);
1032 OUT_RING(ring, 0);
1033
1034 OUT_PKT4(ring, REG_A6XX_SP_DS_TEX_COUNT, 1);
1035 OUT_RING(ring, 0);
1036
1037 OUT_PKT4(ring, REG_A6XX_SP_GS_TEX_COUNT, 1);
1038 OUT_RING(ring, 0);
1039
1040 OUT_PKT4(ring, REG_A6XX_SP_FS_TEX_COUNT, 1);
1041 OUT_RING(ring, 0);
1042 }
1043
1044 if (dirty & (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)) {
1045 struct fd_ringbuffer *state =
1046 fd6_build_ibo_state(ctx, cp, PIPE_SHADER_COMPUTE);
1047 const struct ir3_ibo_mapping *mapping = &cp->image_mapping;
1048
1049 OUT_PKT7(ring, CP_LOAD_STATE6_FRAG, 3);
1050 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
1051 CP_LOAD_STATE6_0_STATE_TYPE(ST6_IBO) |
1052 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1053 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_CS_SHADER) |
1054 CP_LOAD_STATE6_0_NUM_UNIT(mapping->num_ibo));
1055 OUT_RB(ring, state);
1056
1057 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_LO, 2);
1058 OUT_RB(ring, state);
1059
1060 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_COUNT, 1);
1061 OUT_RING(ring, mapping->num_ibo);
1062
1063 fd_ringbuffer_del(state);
1064 }
1065 }
1066
1067
1068 /* emit setup at begin of new cmdstream buffer (don't rely on previous
1069 * state, there could have been a context switch between ioctls):
1070 */
1071 void
1072 fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
1073 {
1074 //struct fd_context *ctx = batch->ctx;
1075
1076 fd6_cache_inv(batch, ring);
1077
1078 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1079 OUT_RING(ring, 0xfffff);
1080
1081 /*
1082 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
1083 0000000500024048: 70d08003 00000000 001c5000 00000005
1084 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
1085 0000000500024058: 70d08003 00000010 001c7000 00000005
1086
1087 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
1088 0000000500024068: 70268000
1089 */
1090
1091 WRITE(REG_A6XX_RB_CCU_CNTL, 0x7c400004);
1092 WRITE(REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
1093 WRITE(REG_A6XX_SP_UNKNOWN_AE04, 0x8);
1094 WRITE(REG_A6XX_SP_UNKNOWN_AE00, 0);
1095 WRITE(REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
1096 WRITE(REG_A6XX_SP_UNKNOWN_B605, 0x44);
1097 WRITE(REG_A6XX_SP_UNKNOWN_B600, 0x100000);
1098 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
1099 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
1100
1101 WRITE(REG_A6XX_VPC_UNKNOWN_9600, 0);
1102 WRITE(REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
1103 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
1104 WRITE(REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
1105 WRITE(REG_A6XX_SP_IBO_COUNT, 0);
1106 WRITE(REG_A6XX_SP_UNKNOWN_B182, 0);
1107 WRITE(REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
1108 WRITE(REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
1109 WRITE(REG_A6XX_UCHE_CLIENT_PF, 4);
1110 WRITE(REG_A6XX_RB_UNKNOWN_8E01, 0x0);
1111 WRITE(REG_A6XX_SP_UNKNOWN_AB00, 0x5);
1112 WRITE(REG_A6XX_VFD_UNKNOWN_A009, 0x00000001);
1113 WRITE(REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
1114 WRITE(REG_A6XX_PC_MODE_CNTL, 0x1f);
1115
1116 OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
1117 OUT_RING(ring, 0);
1118
1119 WRITE(REG_A6XX_GRAS_UNKNOWN_8101, 0);
1120 WRITE(REG_A6XX_GRAS_UNKNOWN_8109, 0);
1121 WRITE(REG_A6XX_GRAS_UNKNOWN_8110, 0);
1122
1123 WRITE(REG_A6XX_RB_RENDER_CONTROL0, 0x401);
1124 WRITE(REG_A6XX_RB_RENDER_CONTROL1, 0);
1125 WRITE(REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
1126 WRITE(REG_A6XX_RB_UNKNOWN_8810, 0);
1127 WRITE(REG_A6XX_RB_UNKNOWN_8818, 0);
1128 WRITE(REG_A6XX_RB_UNKNOWN_8819, 0);
1129 WRITE(REG_A6XX_RB_UNKNOWN_881A, 0);
1130 WRITE(REG_A6XX_RB_UNKNOWN_881B, 0);
1131 WRITE(REG_A6XX_RB_UNKNOWN_881C, 0);
1132 WRITE(REG_A6XX_RB_UNKNOWN_881D, 0);
1133 WRITE(REG_A6XX_RB_UNKNOWN_881E, 0);
1134 WRITE(REG_A6XX_RB_UNKNOWN_88F0, 0);
1135
1136 WRITE(REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
1137 WRITE(REG_A6XX_VPC_UNKNOWN_9107, 0);
1138
1139 WRITE(REG_A6XX_VPC_UNKNOWN_9236,
1140 A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(0));
1141 WRITE(REG_A6XX_VPC_UNKNOWN_9300, 0);
1142
1143 WRITE(REG_A6XX_VPC_SO_OVERRIDE, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
1144
1145 WRITE(REG_A6XX_PC_UNKNOWN_9801, 0);
1146 WRITE(REG_A6XX_PC_UNKNOWN_9806, 0);
1147 WRITE(REG_A6XX_PC_UNKNOWN_9980, 0);
1148
1149 WRITE(REG_A6XX_PC_UNKNOWN_9B06, 0);
1150 WRITE(REG_A6XX_PC_UNKNOWN_9B06, 0);
1151
1152 WRITE(REG_A6XX_SP_UNKNOWN_A81B, 0);
1153
1154 WRITE(REG_A6XX_SP_UNKNOWN_B183, 0);
1155
1156 WRITE(REG_A6XX_GRAS_UNKNOWN_8099, 0);
1157 WRITE(REG_A6XX_GRAS_UNKNOWN_809B, 0);
1158 WRITE(REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1159 WRITE(REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1160 WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
1161 WRITE(REG_A6XX_VPC_UNKNOWN_9211, 0);
1162 WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
1163 WRITE(REG_A6XX_PC_UNKNOWN_9981, 0x3);
1164 WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
1165 WRITE(REG_A6XX_VPC_UNKNOWN_9108, 0x3);
1166 WRITE(REG_A6XX_SP_TP_UNKNOWN_B304, 0);
1167 WRITE(REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
1168 WRITE(REG_A6XX_RB_UNKNOWN_8804, 0);
1169 WRITE(REG_A6XX_GRAS_UNKNOWN_80A4, 0);
1170 WRITE(REG_A6XX_GRAS_UNKNOWN_80A5, 0);
1171 WRITE(REG_A6XX_GRAS_UNKNOWN_80A6, 0);
1172 WRITE(REG_A6XX_RB_UNKNOWN_8805, 0);
1173 WRITE(REG_A6XX_RB_UNKNOWN_8806, 0);
1174 WRITE(REG_A6XX_RB_UNKNOWN_8878, 0);
1175 WRITE(REG_A6XX_RB_UNKNOWN_8879, 0);
1176 WRITE(REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1177
1178 emit_marker6(ring, 7);
1179
1180 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
1181 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
1182
1183 WRITE(REG_A6XX_VFD_UNKNOWN_A008, 0);
1184
1185 OUT_PKT4(ring, REG_A6XX_PC_MODE_CNTL, 1);
1186 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
1187
1188 /* we don't use this yet.. probably best to disable.. */
1189 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1190 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1191 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1192 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1193 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1194 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1195
1196 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1197 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
1198
1199 OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1);
1200 OUT_RING(ring, 0x00000000);
1201
1202 OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
1203 OUT_RING(ring, 0x00000000);
1204
1205 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1206 OUT_RING(ring, 0x00000000);
1207
1208 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
1209 OUT_RING(ring, 0x00000000);
1210 }
1211
1212 static void
1213 fd6_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
1214 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
1215 unsigned sizedwords)
1216 {
1217 struct fd_bo *src_bo = fd_resource(src)->bo;
1218 struct fd_bo *dst_bo = fd_resource(dst)->bo;
1219 unsigned i;
1220
1221 for (i = 0; i < sizedwords; i++) {
1222 OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
1223 OUT_RING(ring, 0x00000000);
1224 OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
1225 OUT_RELOC (ring, src_bo, src_off, 0, 0);
1226
1227 dst_off += 4;
1228 src_off += 4;
1229 }
1230 }
1231
1232 void
1233 fd6_emit_init(struct pipe_context *pctx)
1234 {
1235 struct fd_context *ctx = fd_context(pctx);
1236 ctx->emit_const = fd6_emit_const;
1237 ctx->emit_const_bo = fd6_emit_const_bo;
1238 ctx->emit_ib = fd6_emit_ib;
1239 ctx->mem_to_mem = fd6_mem_to_mem;
1240 }