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freedreno/a6xx: split out const emit
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_helpers.h"
32 #include "util/format/u_format.h"
33 #include "util/u_viewport.h"
34
35 #include "freedreno_log.h"
36 #include "freedreno_resource.h"
37 #include "freedreno_query_hw.h"
38
39 #include "fd6_emit.h"
40 #include "fd6_blend.h"
41 #include "fd6_const.h"
42 #include "fd6_context.h"
43 #include "fd6_image.h"
44 #include "fd6_program.h"
45 #include "fd6_rasterizer.h"
46 #include "fd6_texture.h"
47 #include "fd6_format.h"
48 #include "fd6_zsa.h"
49
50 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
51 * the same as a6xx then move this somewhere common ;-)
52 *
53 * Entry layout looks like (total size, 0x60 bytes):
54 */
55
56 struct PACKED bcolor_entry {
57 uint32_t fp32[4];
58 uint16_t ui16[4];
59 int16_t si16[4];
60 uint16_t fp16[4];
61 uint16_t rgb565;
62 uint16_t rgb5a1;
63 uint16_t rgba4;
64 uint8_t __pad0[2];
65 uint8_t ui8[4];
66 int8_t si8[4];
67 uint32_t rgb10a2;
68 uint32_t z24; /* also s8? */
69 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
70 uint8_t __pad1[56];
71 };
72
73 #define FD6_BORDER_COLOR_SIZE sizeof(struct bcolor_entry)
74 #define FD6_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD6_BORDER_COLOR_SIZE)
75
76 static void
77 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
78 {
79 unsigned i, j;
80 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
81
82 for (i = 0; i < tex->num_samplers; i++) {
83 struct bcolor_entry *e = &entries[i];
84 struct pipe_sampler_state *sampler = tex->samplers[i];
85 union pipe_color_union *bc;
86
87 if (!sampler)
88 continue;
89
90 bc = &sampler->border_color;
91
92 /*
93 * XXX HACK ALERT XXX
94 *
95 * The border colors need to be swizzled in a particular
96 * format-dependent order. Even though samplers don't know about
97 * formats, we can assume that with a GL state tracker, there's a
98 * 1:1 correspondence between sampler and texture. Take advantage
99 * of that knowledge.
100 */
101 if ((i >= tex->num_textures) || !tex->textures[i])
102 continue;
103
104 struct pipe_sampler_view *view = tex->textures[i];
105 enum pipe_format format = view->format;
106 const struct util_format_description *desc =
107 util_format_description(format);
108
109 e->rgb565 = 0;
110 e->rgb5a1 = 0;
111 e->rgba4 = 0;
112 e->rgb10a2 = 0;
113 e->z24 = 0;
114
115 unsigned char swiz[4];
116
117 fd6_tex_swiz(format, swiz,
118 view->swizzle_r, view->swizzle_g,
119 view->swizzle_b, view->swizzle_a);
120
121 for (j = 0; j < 4; j++) {
122 int c = swiz[j];
123 int cd = c;
124
125 /*
126 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the
127 * stencil border color value in bc->ui[0] but according
128 * to desc->swizzle and desc->channel, the .x/.w component
129 * is NONE and the stencil value is in the y component.
130 * Meanwhile the hardware wants this in the .w component
131 * for x24s8 and the .x component for x32_s8x24.
132 */
133 if ((format == PIPE_FORMAT_X24S8_UINT) ||
134 (format == PIPE_FORMAT_X32_S8X24_UINT)) {
135 if (j == 0) {
136 c = 1;
137 cd = (format == PIPE_FORMAT_X32_S8X24_UINT) ? 0 : 3;
138 } else {
139 continue;
140 }
141 }
142
143 if (c >= 4)
144 continue;
145
146 if (desc->channel[c].pure_integer) {
147 uint16_t clamped;
148 switch (desc->channel[c].size) {
149 case 2:
150 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
151 clamped = CLAMP(bc->ui[j], 0, 0x3);
152 break;
153 case 8:
154 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
155 clamped = CLAMP(bc->i[j], -128, 127);
156 else
157 clamped = CLAMP(bc->ui[j], 0, 255);
158 break;
159 case 10:
160 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
161 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
162 break;
163 case 16:
164 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
165 clamped = CLAMP(bc->i[j], -32768, 32767);
166 else
167 clamped = CLAMP(bc->ui[j], 0, 65535);
168 break;
169 default:
170 assert(!"Unexpected bit size");
171 case 32:
172 clamped = 0;
173 break;
174 }
175 e->fp32[cd] = bc->ui[j];
176 e->fp16[cd] = clamped;
177 } else {
178 float f = bc->f[j];
179 float f_u = CLAMP(f, 0, 1);
180 float f_s = CLAMP(f, -1, 1);
181
182 e->fp32[c] = fui(f);
183 e->fp16[c] = util_float_to_half(f);
184 e->srgb[c] = util_float_to_half(f_u);
185 e->ui16[c] = f_u * 0xffff;
186 e->si16[c] = f_s * 0x7fff;
187 e->ui8[c] = f_u * 0xff;
188 e->si8[c] = f_s * 0x7f;
189 if (c == 1)
190 e->rgb565 |= (int)(f_u * 0x3f) << 5;
191 else if (c < 3)
192 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
193 if (c == 3)
194 e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
195 else
196 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
197 if (c == 3)
198 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
199 else
200 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
201 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
202 if (c == 0)
203 e->z24 = f_u * 0xffffff;
204 }
205 }
206
207 #ifdef DEBUG
208 memset(&e->__pad0, 0, sizeof(e->__pad0));
209 memset(&e->__pad1, 0, sizeof(e->__pad1));
210 #endif
211 }
212 }
213
214 static void
215 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
216 {
217 struct fd6_context *fd6_ctx = fd6_context(ctx);
218 struct bcolor_entry *entries;
219 unsigned off;
220 void *ptr;
221
222 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
223
224 u_upload_alloc(fd6_ctx->border_color_uploader,
225 0, FD6_BORDER_COLOR_UPLOAD_SIZE,
226 FD6_BORDER_COLOR_UPLOAD_SIZE, &off,
227 &fd6_ctx->border_color_buf,
228 &ptr);
229
230 entries = ptr;
231
232 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
233 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
234 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
235
236 OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
237 OUT_RELOC(ring, fd_resource(fd6_ctx->border_color_buf)->bo, off, 0, 0);
238
239 u_upload_unmap(fd6_ctx->border_color_uploader);
240 }
241
242 static void
243 fd6_emit_fb_tex(struct fd_ringbuffer *state, struct fd_context *ctx)
244 {
245 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
246 struct pipe_surface *psurf = pfb->cbufs[0];
247 struct fd_resource *rsc = fd_resource(psurf->texture);
248
249 uint32_t texconst0 = fd6_tex_const_0(psurf->texture, psurf->u.tex.level,
250 psurf->format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
251 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W);
252
253 /* always TILE6_2 mode in GMEM.. which also means no swap: */
254 texconst0 &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
255 texconst0 |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
256
257 OUT_RING(state, texconst0);
258 OUT_RING(state, A6XX_TEX_CONST_1_WIDTH(pfb->width) |
259 A6XX_TEX_CONST_1_HEIGHT(pfb->height));
260 OUT_RINGP(state, A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
261 A6XX_TEX_CONST_2_FETCHSIZE(TFETCH6_2_BYTE),
262 &ctx->batch->fb_read_patches);
263 OUT_RING(state, A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size));
264
265 OUT_RING(state, A6XX_TEX_CONST_4_BASE_LO(ctx->screen->gmem_base));
266 OUT_RING(state, A6XX_TEX_CONST_5_BASE_HI(ctx->screen->gmem_base >> 32) |
267 A6XX_TEX_CONST_5_DEPTH(1));
268 OUT_RING(state, 0); /* texconst6 */
269 OUT_RING(state, 0); /* texconst7 */
270 OUT_RING(state, 0); /* texconst8 */
271 OUT_RING(state, 0); /* texconst9 */
272 OUT_RING(state, 0); /* texconst10 */
273 OUT_RING(state, 0); /* texconst11 */
274 OUT_RING(state, 0);
275 OUT_RING(state, 0);
276 OUT_RING(state, 0);
277 OUT_RING(state, 0);
278 }
279
280 bool
281 fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
282 enum pipe_shader_type type, struct fd_texture_stateobj *tex,
283 unsigned bcolor_offset,
284 /* can be NULL if no image/SSBO/fb state to merge in: */
285 const struct ir3_shader_variant *v, struct fd_context *ctx)
286 {
287 bool needs_border = false;
288 unsigned opcode, tex_samp_reg, tex_const_reg, tex_count_reg;
289 enum a6xx_state_block sb;
290
291 switch (type) {
292 case PIPE_SHADER_VERTEX:
293 sb = SB6_VS_TEX;
294 opcode = CP_LOAD_STATE6_GEOM;
295 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
296 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
297 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
298 break;
299 case PIPE_SHADER_TESS_CTRL:
300 sb = SB6_HS_TEX;
301 opcode = CP_LOAD_STATE6_GEOM;
302 tex_samp_reg = REG_A6XX_SP_HS_TEX_SAMP_LO;
303 tex_const_reg = REG_A6XX_SP_HS_TEX_CONST_LO;
304 tex_count_reg = REG_A6XX_SP_HS_TEX_COUNT;
305 break;
306 case PIPE_SHADER_TESS_EVAL:
307 sb = SB6_DS_TEX;
308 opcode = CP_LOAD_STATE6_GEOM;
309 tex_samp_reg = REG_A6XX_SP_DS_TEX_SAMP_LO;
310 tex_const_reg = REG_A6XX_SP_DS_TEX_CONST_LO;
311 tex_count_reg = REG_A6XX_SP_DS_TEX_COUNT;
312 break;
313 case PIPE_SHADER_GEOMETRY:
314 sb = SB6_GS_TEX;
315 opcode = CP_LOAD_STATE6_GEOM;
316 tex_samp_reg = REG_A6XX_SP_GS_TEX_SAMP_LO;
317 tex_const_reg = REG_A6XX_SP_GS_TEX_CONST_LO;
318 tex_count_reg = REG_A6XX_SP_GS_TEX_COUNT;
319 break;
320 case PIPE_SHADER_FRAGMENT:
321 sb = SB6_FS_TEX;
322 opcode = CP_LOAD_STATE6_FRAG;
323 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
324 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
325 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
326 break;
327 case PIPE_SHADER_COMPUTE:
328 sb = SB6_CS_TEX;
329 opcode = CP_LOAD_STATE6_FRAG;
330 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
331 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
332 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
333 break;
334 default:
335 unreachable("bad state block");
336 }
337
338 if (tex->num_samplers > 0) {
339 struct fd_ringbuffer *state =
340 fd_ringbuffer_new_object(pipe, tex->num_samplers * 4 * 4);
341 for (unsigned i = 0; i < tex->num_samplers; i++) {
342 static const struct fd6_sampler_stateobj dummy_sampler = {};
343 const struct fd6_sampler_stateobj *sampler = tex->samplers[i] ?
344 fd6_sampler_stateobj(tex->samplers[i]) : &dummy_sampler;
345 OUT_RING(state, sampler->texsamp0);
346 OUT_RING(state, sampler->texsamp1);
347 OUT_RING(state, sampler->texsamp2 |
348 A6XX_TEX_SAMP_2_BCOLOR_OFFSET((i + bcolor_offset) * sizeof(struct bcolor_entry)));
349 OUT_RING(state, sampler->texsamp3);
350 needs_border |= sampler->needs_border;
351 }
352
353 /* output sampler state: */
354 OUT_PKT7(ring, opcode, 3);
355 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
356 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
357 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
358 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
359 CP_LOAD_STATE6_0_NUM_UNIT(tex->num_samplers));
360 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
361
362 OUT_PKT4(ring, tex_samp_reg, 2);
363 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
364
365 fd_ringbuffer_del(state);
366 }
367
368 unsigned num_merged_textures = tex->num_textures;
369 unsigned num_textures = tex->num_textures;
370 if (v) {
371 num_merged_textures += v->image_mapping.num_tex;
372
373 if (v->fb_read)
374 num_merged_textures++;
375
376 /* There could be more bound textures than what the shader uses.
377 * Which isn't known at shader compile time. So in the case we
378 * are merging tex state, only emit the textures that the shader
379 * uses (since the image/SSBO related tex state comes immediately
380 * after)
381 */
382 num_textures = v->image_mapping.tex_base;
383 }
384
385 if (num_merged_textures > 0) {
386 struct fd_ringbuffer *state =
387 fd_ringbuffer_new_object(pipe, num_merged_textures * 16 * 4);
388 for (unsigned i = 0; i < num_textures; i++) {
389 static const struct fd6_pipe_sampler_view dummy_view = {};
390 const struct fd6_pipe_sampler_view *view = tex->textures[i] ?
391 fd6_pipe_sampler_view(tex->textures[i]) : &dummy_view;
392 struct fd_resource *rsc = NULL;
393
394 if (view->base.texture)
395 rsc = fd_resource(view->base.texture);
396
397 OUT_RING(state, view->texconst0);
398 OUT_RING(state, view->texconst1);
399 OUT_RING(state, view->texconst2);
400 OUT_RING(state, view->texconst3);
401
402 if (rsc) {
403 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
404 rsc = rsc->stencil;
405 OUT_RELOC(state, rsc->bo, view->offset,
406 (uint64_t)view->texconst5 << 32, 0);
407 } else {
408 OUT_RING(state, 0x00000000);
409 OUT_RING(state, view->texconst5);
410 }
411
412 OUT_RING(state, view->texconst6);
413
414 if (rsc && view->ubwc_enabled) {
415 OUT_RELOC(state, rsc->bo, view->ubwc_offset, 0, 0);
416 } else {
417 OUT_RING(state, 0);
418 OUT_RING(state, 0);
419 }
420
421 OUT_RING(state, view->texconst9);
422 OUT_RING(state, view->texconst10);
423 OUT_RING(state, view->texconst11);
424 OUT_RING(state, 0);
425 OUT_RING(state, 0);
426 OUT_RING(state, 0);
427 OUT_RING(state, 0);
428 }
429
430 if (v) {
431 const struct ir3_ibo_mapping *mapping = &v->image_mapping;
432 struct fd_shaderbuf_stateobj *buf = &ctx->shaderbuf[type];
433 struct fd_shaderimg_stateobj *img = &ctx->shaderimg[type];
434
435 for (unsigned i = 0; i < mapping->num_tex; i++) {
436 unsigned idx = mapping->tex_to_image[i];
437 if (idx & IBO_SSBO) {
438 fd6_emit_ssbo_tex(state, &buf->sb[idx & ~IBO_SSBO]);
439 } else {
440 fd6_emit_image_tex(state, &img->si[idx]);
441 }
442 }
443
444 if (v->fb_read) {
445 fd6_emit_fb_tex(state, ctx);
446 }
447 }
448
449 /* emit texture state: */
450 OUT_PKT7(ring, opcode, 3);
451 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
452 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
453 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
454 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
455 CP_LOAD_STATE6_0_NUM_UNIT(num_merged_textures));
456 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
457
458 OUT_PKT4(ring, tex_const_reg, 2);
459 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
460
461 fd_ringbuffer_del(state);
462 }
463
464 OUT_PKT4(ring, tex_count_reg, 1);
465 OUT_RING(ring, num_merged_textures);
466
467 return needs_border;
468 }
469
470 /* Emits combined texture state, which also includes any Image/SSBO
471 * related texture state merged in (because we must have all texture
472 * state for a given stage in a single buffer). In the fast-path, if
473 * we don't need to merge in any image/ssbo related texture state, we
474 * just use cached texture stateobj. Otherwise we generate a single-
475 * use stateobj.
476 *
477 * TODO Is there some sane way we can still use cached texture stateobj
478 * with image/ssbo in use?
479 *
480 * returns whether border_color is required:
481 */
482 static bool
483 fd6_emit_combined_textures(struct fd_ringbuffer *ring, struct fd6_emit *emit,
484 enum pipe_shader_type type, const struct ir3_shader_variant *v)
485 {
486 struct fd_context *ctx = emit->ctx;
487 bool needs_border = false;
488
489 static const struct {
490 enum fd6_state_id state_id;
491 unsigned enable_mask;
492 } s[PIPE_SHADER_TYPES] = {
493 [PIPE_SHADER_VERTEX] = { FD6_GROUP_VS_TEX, ENABLE_ALL },
494 [PIPE_SHADER_TESS_CTRL] = { FD6_GROUP_HS_TEX, ENABLE_ALL },
495 [PIPE_SHADER_TESS_EVAL] = { FD6_GROUP_DS_TEX, ENABLE_ALL },
496 [PIPE_SHADER_GEOMETRY] = { FD6_GROUP_GS_TEX, ENABLE_ALL },
497 [PIPE_SHADER_FRAGMENT] = { FD6_GROUP_FS_TEX, ENABLE_DRAW },
498 };
499
500 debug_assert(s[type].state_id);
501
502 if (!v->image_mapping.num_tex && !v->fb_read) {
503 /* in the fast-path, when we don't have to mix in any image/SSBO
504 * related texture state, we can just lookup the stateobj and
505 * re-emit that:
506 *
507 * Also, framebuffer-read is a slow-path because an extra
508 * texture needs to be inserted.
509 *
510 * TODO we can probably simmplify things if we also treated
511 * border_color as a slow-path.. this way the tex state key
512 * wouldn't depend on bcolor_offset.. but fb_read might rather
513 * be *somehow* a fast-path if we eventually used it for PLS.
514 * I suppose there would be no harm in just *always* inserting
515 * an fb_read texture?
516 */
517 if ((ctx->dirty_shader[type] & FD_DIRTY_SHADER_TEX) &&
518 ctx->tex[type].num_textures > 0) {
519 struct fd6_texture_state *tex = fd6_texture_state(ctx,
520 type, &ctx->tex[type]);
521
522 needs_border |= tex->needs_border;
523
524 fd6_emit_add_group(emit, tex->stateobj, s[type].state_id,
525 s[type].enable_mask);
526 }
527 } else {
528 /* In the slow-path, create a one-shot texture state object
529 * if either TEX|PROG|SSBO|IMAGE state is dirty:
530 */
531 if ((ctx->dirty_shader[type] &
532 (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
533 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) ||
534 v->fb_read) {
535 struct fd_texture_stateobj *tex = &ctx->tex[type];
536 struct fd_ringbuffer *stateobj =
537 fd_submit_new_ringbuffer(ctx->batch->submit,
538 0x1000, FD_RINGBUFFER_STREAMING);
539 unsigned bcolor_offset =
540 fd6_border_color_offset(ctx, type, tex);
541
542 needs_border |= fd6_emit_textures(ctx->pipe, stateobj, type, tex,
543 bcolor_offset, v, ctx);
544
545 fd6_emit_take_group(emit, stateobj, s[type].state_id,
546 s[type].enable_mask);
547 }
548 }
549
550 return needs_border;
551 }
552
553 static struct fd_ringbuffer *
554 build_vbo_state(struct fd6_emit *emit, const struct ir3_shader_variant *vp)
555 {
556 const struct fd_vertex_state *vtx = emit->vtx;
557 int32_t i, j;
558
559 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
560 4 * (10 * vp->inputs_count + 2), FD_RINGBUFFER_STREAMING);
561
562 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
563 if (vp->inputs[i].sysval)
564 continue;
565 if (vp->inputs[i].compmask) {
566 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
567 const struct pipe_vertex_buffer *vb =
568 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
569 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
570 enum pipe_format pfmt = elem->src_format;
571 enum a6xx_format fmt = fd6_pipe2vtx(pfmt);
572 bool isint = util_format_is_pure_integer(pfmt);
573 uint32_t off = vb->buffer_offset + elem->src_offset;
574 uint32_t size = fd_bo_size(rsc->bo) - off;
575 debug_assert(fmt != ~0);
576
577 #ifdef DEBUG
578 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
579 */
580 if (off > fd_bo_size(rsc->bo))
581 continue;
582 #endif
583
584 OUT_PKT4(ring, REG_A6XX_VFD_FETCH(j), 4);
585 OUT_RELOC(ring, rsc->bo, off, 0, 0);
586 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
587 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
588
589 OUT_PKT4(ring, REG_A6XX_VFD_DECODE(j), 2);
590 OUT_RING(ring, A6XX_VFD_DECODE_INSTR_IDX(j) |
591 A6XX_VFD_DECODE_INSTR_FORMAT(fmt) |
592 COND(elem->instance_divisor, A6XX_VFD_DECODE_INSTR_INSTANCED) |
593 A6XX_VFD_DECODE_INSTR_SWAP(fd6_pipe2swap(pfmt)) |
594 A6XX_VFD_DECODE_INSTR_UNK30 |
595 COND(!isint, A6XX_VFD_DECODE_INSTR_FLOAT));
596 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
597
598 OUT_PKT4(ring, REG_A6XX_VFD_DEST_CNTL(j), 1);
599 OUT_RING(ring, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
600 A6XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
601
602 j++;
603 }
604 }
605
606 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_0, 1);
607 OUT_RING(ring, A6XX_VFD_CONTROL_0_FETCH_CNT(j) |
608 A6XX_VFD_CONTROL_0_DECODE_CNT(j));
609
610 return ring;
611 }
612
613 static struct fd_ringbuffer *
614 build_lrz(struct fd6_emit *emit, bool binning_pass)
615 {
616 struct fd_context *ctx = emit->ctx;
617 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
618 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
619 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
620 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
621 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
622 uint32_t rb_lrz_cntl = zsa->rb_lrz_cntl;
623
624 if (zsa->invalidate_lrz) {
625 rsc->lrz_valid = false;
626 gras_lrz_cntl = 0;
627 rb_lrz_cntl = 0;
628 } else if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid) {
629 gras_lrz_cntl = 0;
630 rb_lrz_cntl = 0;
631 } else if (binning_pass && blend->lrz_write && zsa->lrz_write) {
632 gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_LRZ_WRITE;
633 }
634
635 struct fd6_context *fd6_ctx = fd6_context(ctx);
636 if ((fd6_ctx->last.lrz[binning_pass].gras_lrz_cntl == gras_lrz_cntl) &&
637 (fd6_ctx->last.lrz[binning_pass].rb_lrz_cntl == rb_lrz_cntl) &&
638 !ctx->last.dirty)
639 return NULL;
640
641 fd6_ctx->last.lrz[binning_pass].gras_lrz_cntl = gras_lrz_cntl;
642 fd6_ctx->last.lrz[binning_pass].rb_lrz_cntl = rb_lrz_cntl;
643
644 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(ctx->batch->submit,
645 16, FD_RINGBUFFER_STREAMING);
646
647 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
648 OUT_RING(ring, gras_lrz_cntl);
649
650 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
651 OUT_RING(ring, rb_lrz_cntl);
652
653 return ring;
654 }
655
656 static void
657 fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3_stream_output_info *info)
658 {
659 struct fd_context *ctx = emit->ctx;
660 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
661 struct fd_streamout_stateobj *so = &ctx->streamout;
662
663 emit->streamout_mask = 0;
664
665 for (unsigned i = 0; i < so->num_targets; i++) {
666 struct pipe_stream_output_target *target = so->targets[i];
667
668 if (!target)
669 continue;
670
671 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(i), 3);
672 /* VPC_SO[i].BUFFER_BASE_LO: */
673 OUT_RELOCW(ring, fd_resource(target->buffer)->bo, target->buffer_offset, 0, 0);
674 OUT_RING(ring, target->buffer_size - target->buffer_offset);
675
676 if (so->reset & (1 << i)) {
677 unsigned offset = (so->offsets[i] * info->stride[i] * 4);
678 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(i), 1);
679 OUT_RING(ring, offset);
680 } else {
681 OUT_PKT7(ring, CP_MEM_TO_REG, 3);
682 OUT_RING(ring, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i)) |
683 CP_MEM_TO_REG_0_SHIFT_BY_2 | CP_MEM_TO_REG_0_UNK31 |
684 CP_MEM_TO_REG_0_CNT(0));
685 OUT_RELOC(ring, control_ptr(fd6_context(ctx), flush_base[i].offset));
686 }
687
688 OUT_PKT4(ring, REG_A6XX_VPC_SO_FLUSH_BASE_LO(i), 2);
689 OUT_RELOCW(ring, control_ptr(fd6_context(ctx), flush_base[i]));
690
691 so->reset &= ~(1 << i);
692
693 emit->streamout_mask |= (1 << i);
694 }
695
696 if (emit->streamout_mask) {
697 const struct fd6_streamout_state *tf = &prog->tf;
698
699 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * tf->prog_count));
700 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
701 OUT_RING(ring, tf->vpc_so_buf_cntl);
702 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0));
703 OUT_RING(ring, tf->ncomp[0]);
704 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1));
705 OUT_RING(ring, tf->ncomp[1]);
706 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(2));
707 OUT_RING(ring, tf->ncomp[2]);
708 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3));
709 OUT_RING(ring, tf->ncomp[3]);
710 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
711 OUT_RING(ring, A6XX_VPC_SO_CNTL_ENABLE);
712 for (unsigned i = 0; i < tf->prog_count; i++) {
713 OUT_RING(ring, REG_A6XX_VPC_SO_PROG);
714 OUT_RING(ring, tf->prog[i]);
715 }
716 } else {
717 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 4);
718 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
719 OUT_RING(ring, 0);
720 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
721 OUT_RING(ring, 0);
722 }
723 }
724
725 void
726 fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
727 {
728 struct fd_context *ctx = emit->ctx;
729 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
730 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
731 const struct ir3_shader_variant *vs = emit->vs;
732 const struct ir3_shader_variant *hs = emit->hs;
733 const struct ir3_shader_variant *ds = emit->ds;
734 const struct ir3_shader_variant *gs = emit->gs;
735 const struct ir3_shader_variant *fs = emit->fs;
736 const enum fd_dirty_3d_state dirty = emit->dirty;
737 bool needs_border = false;
738
739 emit_marker6(ring, 5);
740
741 /* NOTE: we track fb_read differently than _BLEND_ENABLED since
742 * we might at some point decide to do sysmem in some cases when
743 * blend is enabled:
744 */
745 if (fs->fb_read)
746 ctx->batch->gmem_reason |= FD_GMEM_FB_READ;
747
748 if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE)) {
749 struct fd_ringbuffer *state;
750
751 state = build_vbo_state(emit, emit->vs);
752 fd6_emit_take_group(emit, state, FD6_GROUP_VBO, ENABLE_ALL);
753 }
754
755 if (dirty & FD_DIRTY_ZSA) {
756 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
757
758 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
759 fd6_emit_add_group(emit, zsa->stateobj_no_alpha, FD6_GROUP_ZSA, ENABLE_ALL);
760 else
761 fd6_emit_add_group(emit, zsa->stateobj, FD6_GROUP_ZSA, ENABLE_ALL);
762 }
763
764 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG)) && pfb->zsbuf) {
765 struct fd_ringbuffer *state;
766
767 state = build_lrz(emit, false);
768 if (state) {
769 fd6_emit_take_group(emit, state, FD6_GROUP_LRZ, ENABLE_DRAW);
770 }
771
772 state = build_lrz(emit, true);
773 if (state) {
774 fd6_emit_take_group(emit, state,
775 FD6_GROUP_LRZ_BINNING, CP_SET_DRAW_STATE__0_BINNING);
776 }
777 }
778
779 if (dirty & FD_DIRTY_STENCIL_REF) {
780 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
781
782 OUT_PKT4(ring, REG_A6XX_RB_STENCILREF, 1);
783 OUT_RING(ring, A6XX_RB_STENCILREF_REF(sr->ref_value[0]) |
784 A6XX_RB_STENCILREF_BFREF(sr->ref_value[1]));
785 }
786
787 /* NOTE: scissor enabled bit is part of rasterizer state, but
788 * fd_rasterizer_state_bind() will mark scissor dirty if needed:
789 */
790 if (dirty & FD_DIRTY_SCISSOR) {
791 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
792 emit->ctx->batch->submit, 3*4, FD_RINGBUFFER_STREAMING);
793 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
794
795 OUT_PKT4(ring, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
796 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
797 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
798 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
799 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
800
801 fd6_emit_take_group(emit, ring, FD6_GROUP_SCISSOR, ENABLE_ALL);
802
803 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
804 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
805 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
806 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
807 }
808
809 if (dirty & FD_DIRTY_VIEWPORT) {
810 struct pipe_scissor_state *scissor = &ctx->viewport_scissor;
811
812 OUT_PKT4(ring, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
813 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
814 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
815 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
816 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
817 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
818 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
819
820 OUT_PKT4(ring, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
821 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
822 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
823 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
824 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
825
826 unsigned guardband_x = fd_calc_guardband(scissor->maxx - scissor->minx);
827 unsigned guardband_y = fd_calc_guardband(scissor->maxy - scissor->miny);
828
829 OUT_PKT4(ring, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
830 OUT_RING(ring, A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_x) |
831 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_y));
832 }
833
834 if (dirty & FD_DIRTY_PROG) {
835 fd6_emit_add_group(emit, prog->config_stateobj, FD6_GROUP_PROG_CONFIG, ENABLE_ALL);
836 fd6_emit_add_group(emit, prog->stateobj, FD6_GROUP_PROG, ENABLE_DRAW);
837 fd6_emit_add_group(emit, prog->binning_stateobj,
838 FD6_GROUP_PROG_BINNING, CP_SET_DRAW_STATE__0_BINNING);
839
840 /* emit remaining streaming program state, ie. what depends on
841 * other emit state, so cannot be pre-baked.
842 */
843 struct fd_ringbuffer *streaming = fd6_program_interp_state(emit);
844
845 fd6_emit_take_group(emit, streaming, FD6_GROUP_PROG_INTERP, ENABLE_DRAW);
846 }
847
848 if (dirty & FD_DIRTY_RASTERIZER) {
849 struct fd_ringbuffer *stateobj =
850 fd6_rasterizer_state(ctx, emit->primitive_restart);
851 fd6_emit_add_group(emit, stateobj,
852 FD6_GROUP_RASTERIZER, ENABLE_ALL);
853 }
854
855 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER_DISCARD | FD_DIRTY_PROG)) {
856 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
857 emit->ctx->batch->submit, 5 * 4, FD_RINGBUFFER_STREAMING);
858
859 unsigned nr = pfb->nr_cbufs;
860
861 if (ctx->rasterizer->rasterizer_discard)
862 nr = 0;
863
864 OUT_PKT4(ring, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
865 OUT_RING(ring, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
866 COND(fs->writes_smask && pfb->samples > 1,
867 A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
868 OUT_RING(ring, A6XX_RB_FS_OUTPUT_CNTL1_MRT(nr));
869
870 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL1, 1);
871 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL1_MRT(nr));
872
873 fd6_emit_take_group(emit, ring, FD6_GROUP_PROG_FB_RAST, ENABLE_DRAW);
874 }
875
876 fd6_emit_consts(emit);
877
878 struct ir3_stream_output_info *info = &fd6_last_shader(prog)->shader->stream_output;
879 if (info->num_outputs)
880 fd6_emit_streamout(ring, emit, info);
881
882 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK)) {
883 struct fd6_blend_variant *blend = fd6_blend_variant(ctx->blend,
884 pfb->samples, ctx->sample_mask);
885 fd6_emit_add_group(emit, blend->stateobj, FD6_GROUP_BLEND, ENABLE_DRAW);
886 }
887
888 if (dirty & FD_DIRTY_BLEND_COLOR) {
889 struct pipe_blend_color *bcolor = &ctx->blend_color;
890 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
891 emit->ctx->batch->submit, 5*4, FD_RINGBUFFER_STREAMING);
892
893 OUT_PKT4(ring, REG_A6XX_RB_BLEND_RED_F32, 4);
894 OUT_RING(ring, A6XX_RB_BLEND_RED_F32(bcolor->color[0]));
895 OUT_RING(ring, A6XX_RB_BLEND_GREEN_F32(bcolor->color[1]));
896 OUT_RING(ring, A6XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
897 OUT_RING(ring, A6XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
898
899 fd6_emit_take_group(emit, ring, FD6_GROUP_BLEND_COLOR, ENABLE_DRAW);
900 }
901
902 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_VERTEX, vs);
903 if (hs) {
904 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_TESS_CTRL, hs);
905 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_TESS_EVAL, ds);
906 }
907 if (gs) {
908 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_GEOMETRY, gs);
909 }
910 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_FRAGMENT, fs);
911
912 if (needs_border)
913 emit_border_color(ctx, ring);
914
915 if (hs) {
916 debug_assert(ir3_shader_nibo(hs) == 0);
917 debug_assert(ir3_shader_nibo(ds) == 0);
918 }
919 if (gs) {
920 debug_assert(ir3_shader_nibo(gs) == 0);
921 }
922
923 #define DIRTY_IBO (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE | \
924 FD_DIRTY_SHADER_PROG)
925 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & DIRTY_IBO) {
926 struct fd_ringbuffer *state =
927 fd6_build_ibo_state(ctx, fs, PIPE_SHADER_FRAGMENT);
928 struct fd_ringbuffer *obj = fd_submit_new_ringbuffer(
929 ctx->batch->submit, 0x100, FD_RINGBUFFER_STREAMING);
930
931 OUT_PKT7(obj, CP_LOAD_STATE6, 3);
932 OUT_RING(obj, CP_LOAD_STATE6_0_DST_OFF(0) |
933 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
934 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
935 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_IBO) |
936 CP_LOAD_STATE6_0_NUM_UNIT(ir3_shader_nibo(fs)));
937 OUT_RB(obj, state);
938
939 OUT_PKT4(obj, REG_A6XX_SP_IBO_LO, 2);
940 OUT_RB(obj, state);
941
942 /* TODO if we used CP_SET_DRAW_STATE for compute shaders, we could
943 * de-duplicate this from program->config_stateobj
944 */
945 OUT_PKT4(obj, REG_A6XX_SP_IBO_COUNT, 1);
946 OUT_RING(obj, ir3_shader_nibo(fs));
947
948 fd6_emit_ibo_consts(emit, fs, PIPE_SHADER_FRAGMENT, ring);
949
950 fd6_emit_take_group(emit, obj, FD6_GROUP_IBO, ENABLE_DRAW);
951 fd_ringbuffer_del(state);
952 }
953
954 if (emit->num_groups > 0) {
955 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3 * emit->num_groups);
956 for (unsigned i = 0; i < emit->num_groups; i++) {
957 struct fd6_state_group *g = &emit->groups[i];
958 unsigned n = g->stateobj ?
959 fd_ringbuffer_size(g->stateobj) / 4 : 0;
960
961 debug_assert((g->enable_mask & ~ENABLE_ALL) == 0);
962
963 if (n == 0) {
964 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
965 CP_SET_DRAW_STATE__0_DISABLE |
966 g->enable_mask |
967 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
968 OUT_RING(ring, 0x00000000);
969 OUT_RING(ring, 0x00000000);
970 } else {
971 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(n) |
972 g->enable_mask |
973 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
974 OUT_RB(ring, g->stateobj);
975 }
976
977 if (g->stateobj)
978 fd_ringbuffer_del(g->stateobj);
979 }
980 emit->num_groups = 0;
981 }
982 }
983
984 void
985 fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
986 struct ir3_shader_variant *cp)
987 {
988 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
989
990 if (dirty & (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
991 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) {
992 struct fd_texture_stateobj *tex = &ctx->tex[PIPE_SHADER_COMPUTE];
993 unsigned bcolor_offset = fd6_border_color_offset(ctx, PIPE_SHADER_COMPUTE, tex);
994
995 bool needs_border = fd6_emit_textures(ctx->pipe, ring, PIPE_SHADER_COMPUTE, tex,
996 bcolor_offset, cp, ctx);
997
998 if (needs_border)
999 emit_border_color(ctx, ring);
1000
1001 OUT_PKT4(ring, REG_A6XX_SP_VS_TEX_COUNT, 1);
1002 OUT_RING(ring, 0);
1003
1004 OUT_PKT4(ring, REG_A6XX_SP_HS_TEX_COUNT, 1);
1005 OUT_RING(ring, 0);
1006
1007 OUT_PKT4(ring, REG_A6XX_SP_DS_TEX_COUNT, 1);
1008 OUT_RING(ring, 0);
1009
1010 OUT_PKT4(ring, REG_A6XX_SP_GS_TEX_COUNT, 1);
1011 OUT_RING(ring, 0);
1012
1013 OUT_PKT4(ring, REG_A6XX_SP_FS_TEX_COUNT, 1);
1014 OUT_RING(ring, 0);
1015 }
1016
1017 if (dirty & (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)) {
1018 struct fd_ringbuffer *state =
1019 fd6_build_ibo_state(ctx, cp, PIPE_SHADER_COMPUTE);
1020
1021 OUT_PKT7(ring, CP_LOAD_STATE6_FRAG, 3);
1022 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
1023 CP_LOAD_STATE6_0_STATE_TYPE(ST6_IBO) |
1024 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1025 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_CS_SHADER) |
1026 CP_LOAD_STATE6_0_NUM_UNIT(ir3_shader_nibo(cp)));
1027 OUT_RB(ring, state);
1028
1029 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_LO, 2);
1030 OUT_RB(ring, state);
1031
1032 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_COUNT, 1);
1033 OUT_RING(ring, ir3_shader_nibo(cp));
1034
1035 fd_ringbuffer_del(state);
1036 }
1037 }
1038
1039
1040 /* emit setup at begin of new cmdstream buffer (don't rely on previous
1041 * state, there could have been a context switch between ioctls):
1042 */
1043 void
1044 fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
1045 {
1046 //struct fd_context *ctx = batch->ctx;
1047
1048 fd_log(batch, "START RESTORE");
1049
1050 fd6_cache_inv(batch, ring);
1051
1052 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1053 OUT_RING(ring, 0xfffff);
1054
1055 OUT_WFI5(ring);
1056
1057 WRITE(REG_A6XX_RB_UNKNOWN_8E04, 0x0);
1058 WRITE(REG_A6XX_SP_UNKNOWN_AE04, 0x8);
1059 WRITE(REG_A6XX_SP_UNKNOWN_AE00, 0);
1060 WRITE(REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
1061 WRITE(REG_A6XX_SP_UNKNOWN_B605, 0x44);
1062 WRITE(REG_A6XX_SP_UNKNOWN_B600, 0x100000);
1063 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
1064 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
1065
1066 WRITE(REG_A6XX_VPC_UNKNOWN_9600, 0);
1067 WRITE(REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
1068 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE04, 0x80000);
1069 WRITE(REG_A6XX_SP_UNKNOWN_AE03, 0x1430);
1070 WRITE(REG_A6XX_SP_IBO_COUNT, 0);
1071 WRITE(REG_A6XX_SP_UNKNOWN_B182, 0);
1072 WRITE(REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
1073 WRITE(REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
1074 WRITE(REG_A6XX_UCHE_CLIENT_PF, 4);
1075 WRITE(REG_A6XX_RB_UNKNOWN_8E01, 0x1);
1076 WRITE(REG_A6XX_SP_UNKNOWN_AB00, 0x5);
1077 WRITE(REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
1078 WRITE(REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
1079 WRITE(REG_A6XX_PC_MODE_CNTL, 0x1f);
1080
1081 OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
1082 OUT_RING(ring, 0);
1083
1084 WRITE(REG_A6XX_GRAS_UNKNOWN_8101, 0);
1085 WRITE(REG_A6XX_GRAS_SAMPLE_CNTL, 0);
1086 WRITE(REG_A6XX_GRAS_UNKNOWN_8110, 0x2);
1087
1088 WRITE(REG_A6XX_RB_UNKNOWN_8818, 0);
1089 WRITE(REG_A6XX_RB_UNKNOWN_8819, 0);
1090 WRITE(REG_A6XX_RB_UNKNOWN_881A, 0);
1091 WRITE(REG_A6XX_RB_UNKNOWN_881B, 0);
1092 WRITE(REG_A6XX_RB_UNKNOWN_881C, 0);
1093 WRITE(REG_A6XX_RB_UNKNOWN_881D, 0);
1094 WRITE(REG_A6XX_RB_UNKNOWN_881E, 0);
1095 WRITE(REG_A6XX_RB_UNKNOWN_88F0, 0);
1096
1097 WRITE(REG_A6XX_VPC_UNKNOWN_9236,
1098 A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(0));
1099 WRITE(REG_A6XX_VPC_UNKNOWN_9300, 0);
1100
1101 WRITE(REG_A6XX_VPC_SO_OVERRIDE, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
1102
1103 WRITE(REG_A6XX_PC_UNKNOWN_9990, 0);
1104 WRITE(REG_A6XX_PC_UNKNOWN_9980, 0);
1105
1106 WRITE(REG_A6XX_PC_UNKNOWN_9B07, 0);
1107
1108 WRITE(REG_A6XX_SP_UNKNOWN_A81B, 0);
1109
1110 WRITE(REG_A6XX_SP_UNKNOWN_B183, 0);
1111
1112 WRITE(REG_A6XX_GRAS_UNKNOWN_8099, 0);
1113 WRITE(REG_A6XX_GRAS_UNKNOWN_809B, 0);
1114 WRITE(REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1115 WRITE(REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1116 WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
1117 WRITE(REG_A6XX_VPC_UNKNOWN_9211, 0);
1118 WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
1119 WRITE(REG_A6XX_PC_UNKNOWN_9981, 0x3);
1120 WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
1121 WRITE(REG_A6XX_VPC_UNKNOWN_9108, 0x3);
1122 WRITE(REG_A6XX_SP_TP_SAMPLE_CONFIG, 0);
1123 /* NOTE blob seems to (mostly?) use 0xb2 for SP_TP_UNKNOWN_B309
1124 * but this seems to kill texture gather offsets.
1125 */
1126 WRITE(REG_A6XX_SP_TP_UNKNOWN_B309, 0xa2);
1127 WRITE(REG_A6XX_RB_SAMPLE_CONFIG, 0);
1128 WRITE(REG_A6XX_GRAS_SAMPLE_CONFIG, 0);
1129 WRITE(REG_A6XX_RB_UNKNOWN_8878, 0);
1130 WRITE(REG_A6XX_RB_UNKNOWN_8879, 0);
1131 WRITE(REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1132
1133 emit_marker6(ring, 7);
1134
1135 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
1136 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
1137
1138 WRITE(REG_A6XX_VFD_UNKNOWN_A008, 0);
1139
1140 OUT_PKT4(ring, REG_A6XX_PC_MODE_CNTL, 1);
1141 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
1142
1143 /* we don't use this yet.. probably best to disable.. */
1144 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1145 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1146 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1147 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1148 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1149 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1150
1151 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1152 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
1153
1154 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1155 OUT_RING(ring, 0x00000000);
1156
1157 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
1158 OUT_RING(ring, 0x00000000);
1159
1160 fd_log(batch, "END RESTORE");
1161 }
1162
1163 static void
1164 fd6_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
1165 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
1166 unsigned sizedwords)
1167 {
1168 struct fd_bo *src_bo = fd_resource(src)->bo;
1169 struct fd_bo *dst_bo = fd_resource(dst)->bo;
1170 unsigned i;
1171
1172 for (i = 0; i < sizedwords; i++) {
1173 OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
1174 OUT_RING(ring, 0x00000000);
1175 OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
1176 OUT_RELOC (ring, src_bo, src_off, 0, 0);
1177
1178 dst_off += 4;
1179 src_off += 4;
1180 }
1181 }
1182
1183 /* this is *almost* the same as fd6_cache_flush().. which I guess
1184 * could be re-worked to be something a bit more generic w/ param
1185 * indicating what needs to be flushed.. although that would mean
1186 * figuring out which events trigger what state to flush..
1187 */
1188 static void
1189 fd6_framebuffer_barrier(struct fd_context *ctx)
1190 {
1191 struct fd6_context *fd6_ctx = fd6_context(ctx);
1192 struct fd_batch *batch = ctx->batch;
1193 struct fd_ringbuffer *ring = batch->draw;
1194 unsigned seqno;
1195
1196 seqno = fd6_event_write(batch, ring, RB_DONE_TS, true);
1197
1198 OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);
1199 OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
1200 CP_WAIT_REG_MEM_0_POLL_MEMORY);
1201 OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
1202 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(seqno));
1203 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(~0));
1204 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
1205
1206 fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
1207 fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
1208
1209 seqno = fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
1210
1211 fd6_event_write(batch, ring, 0x31, false);
1212
1213 OUT_PKT7(ring, CP_WAIT_MEM_GTE, 4);
1214 OUT_RING(ring, CP_WAIT_MEM_GTE_0_RESERVED(0));
1215 OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
1216 OUT_RING(ring, CP_WAIT_MEM_GTE_3_REF(seqno));
1217 }
1218
1219 void
1220 fd6_emit_init_screen(struct pipe_screen *pscreen)
1221 {
1222 struct fd_screen *screen = fd_screen(pscreen);
1223 screen->emit_const = fd6_emit_const;
1224 screen->emit_const_bo = fd6_emit_const_bo;
1225 screen->emit_ib = fd6_emit_ib;
1226 screen->mem_to_mem = fd6_mem_to_mem;
1227 }
1228
1229 void
1230 fd6_emit_init(struct pipe_context *pctx)
1231 {
1232 struct fd_context *ctx = fd_context(pctx);
1233 ctx->framebuffer_barrier = fd6_framebuffer_barrier;
1234 }