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freedreno: update generated headers
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_helpers.h"
32 #include "util/u_format.h"
33 #include "util/u_viewport.h"
34
35 #include "freedreno_resource.h"
36 #include "freedreno_query_hw.h"
37
38 #include "fd6_emit.h"
39 #include "fd6_blend.h"
40 #include "fd6_context.h"
41 #include "fd6_image.h"
42 #include "fd6_program.h"
43 #include "fd6_rasterizer.h"
44 #include "fd6_texture.h"
45 #include "fd6_format.h"
46 #include "fd6_zsa.h"
47
48 static uint32_t
49 shader_t_to_opcode(enum shader_t type)
50 {
51 switch (type) {
52 case SHADER_VERTEX:
53 case SHADER_TCS:
54 case SHADER_TES:
55 case SHADER_GEOM:
56 return CP_LOAD_STATE6_GEOM;
57 case SHADER_FRAGMENT:
58 case SHADER_COMPUTE:
59 return CP_LOAD_STATE6_FRAG;
60 default:
61 unreachable("bad shader type");
62 }
63 }
64
65 /* regid: base const register
66 * prsc or dwords: buffer containing constant values
67 * sizedwords: size of const value buffer
68 */
69 static void
70 fd6_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
71 uint32_t regid, uint32_t offset, uint32_t sizedwords,
72 const uint32_t *dwords, struct pipe_resource *prsc)
73 {
74 uint32_t i, sz;
75 enum a6xx_state_src src;
76
77 debug_assert((regid % 4) == 0);
78 debug_assert((sizedwords % 4) == 0);
79
80 if (prsc) {
81 sz = 0;
82 src = SS6_INDIRECT;
83 } else {
84 sz = sizedwords;
85 src = SS6_DIRECT;
86 }
87
88 OUT_PKT7(ring, shader_t_to_opcode(type), 3 + sz);
89 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
90 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
91 CP_LOAD_STATE6_0_STATE_SRC(src) |
92 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
93 CP_LOAD_STATE6_0_NUM_UNIT(sizedwords/4));
94 if (prsc) {
95 struct fd_bo *bo = fd_resource(prsc)->bo;
96 OUT_RELOC(ring, bo, offset, 0, 0);
97 } else {
98 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
99 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
100 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
101 }
102 for (i = 0; i < sz; i++) {
103 OUT_RING(ring, dwords[i]);
104 }
105 }
106
107 static void
108 fd6_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
109 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
110 {
111 uint32_t anum = align(num, 2);
112 uint32_t i;
113
114 debug_assert((regid % 4) == 0);
115
116 OUT_PKT7(ring, shader_t_to_opcode(type), 3 + (2 * anum));
117 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
118 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS)|
119 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
120 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
121 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
122 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
123 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
124
125 for (i = 0; i < num; i++) {
126 if (prscs[i]) {
127 if (write) {
128 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
129 } else {
130 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
131 }
132 } else {
133 OUT_RING(ring, 0xbad00000 | (i << 16));
134 OUT_RING(ring, 0xbad00000 | (i << 16));
135 }
136 }
137
138 for (; i < anum; i++) {
139 OUT_RING(ring, 0xffffffff);
140 OUT_RING(ring, 0xffffffff);
141 }
142 }
143
144 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
145 * the same as a6xx then move this somewhere common ;-)
146 *
147 * Entry layout looks like (total size, 0x60 bytes):
148 */
149
150 struct PACKED bcolor_entry {
151 uint32_t fp32[4];
152 uint16_t ui16[4];
153 int16_t si16[4];
154 uint16_t fp16[4];
155 uint16_t rgb565;
156 uint16_t rgb5a1;
157 uint16_t rgba4;
158 uint8_t __pad0[2];
159 uint8_t ui8[4];
160 int8_t si8[4];
161 uint32_t rgb10a2;
162 uint32_t z24; /* also s8? */
163 uint8_t __pad1[32];
164 };
165
166 #define FD6_BORDER_COLOR_SIZE 0x60
167 #define FD6_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD6_BORDER_COLOR_SIZE)
168
169 static void
170 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
171 {
172 unsigned i, j;
173 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
174
175 for (i = 0; i < tex->num_samplers; i++) {
176 struct bcolor_entry *e = &entries[i];
177 struct pipe_sampler_state *sampler = tex->samplers[i];
178 union pipe_color_union *bc;
179
180 if (!sampler)
181 continue;
182
183 bc = &sampler->border_color;
184
185 /*
186 * XXX HACK ALERT XXX
187 *
188 * The border colors need to be swizzled in a particular
189 * format-dependent order. Even though samplers don't know about
190 * formats, we can assume that with a GL state tracker, there's a
191 * 1:1 correspondence between sampler and texture. Take advantage
192 * of that knowledge.
193 */
194 if ((i >= tex->num_textures) || !tex->textures[i])
195 continue;
196
197 const struct util_format_description *desc =
198 util_format_description(tex->textures[i]->format);
199
200 e->rgb565 = 0;
201 e->rgb5a1 = 0;
202 e->rgba4 = 0;
203 e->rgb10a2 = 0;
204 e->z24 = 0;
205
206 for (j = 0; j < 4; j++) {
207 int c = desc->swizzle[j];
208
209 if (c >= 4)
210 continue;
211
212 if (desc->channel[c].pure_integer) {
213 uint16_t clamped;
214 switch (desc->channel[c].size) {
215 case 2:
216 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
217 clamped = CLAMP(bc->ui[j], 0, 0x3);
218 break;
219 case 8:
220 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
221 clamped = CLAMP(bc->i[j], -128, 127);
222 else
223 clamped = CLAMP(bc->ui[j], 0, 255);
224 break;
225 case 10:
226 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
227 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
228 break;
229 case 16:
230 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
231 clamped = CLAMP(bc->i[j], -32768, 32767);
232 else
233 clamped = CLAMP(bc->ui[j], 0, 65535);
234 break;
235 default:
236 assert(!"Unexpected bit size");
237 case 32:
238 clamped = 0;
239 break;
240 }
241 e->fp32[c] = bc->ui[j];
242 e->fp16[c] = clamped;
243 } else {
244 float f = bc->f[j];
245 float f_u = CLAMP(f, 0, 1);
246 float f_s = CLAMP(f, -1, 1);
247
248 e->fp32[c] = fui(f);
249 e->fp16[c] = util_float_to_half(f);
250 e->ui16[c] = f_u * 0xffff;
251 e->si16[c] = f_s * 0x7fff;
252 e->ui8[c] = f_u * 0xff;
253 e->si8[c] = f_s * 0x7f;
254 if (c == 1)
255 e->rgb565 |= (int)(f_u * 0x3f) << 5;
256 else if (c < 3)
257 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
258 if (c == 3)
259 e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
260 else
261 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
262 if (c == 3)
263 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
264 else
265 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
266 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
267 if (c == 0)
268 e->z24 = f_u * 0xffffff;
269 }
270 }
271
272 #ifdef DEBUG
273 memset(&e->__pad0, 0, sizeof(e->__pad0));
274 memset(&e->__pad1, 0, sizeof(e->__pad1));
275 #endif
276 }
277 }
278
279 static void
280 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
281 {
282 struct fd6_context *fd6_ctx = fd6_context(ctx);
283 struct bcolor_entry *entries;
284 unsigned off;
285 void *ptr;
286
287 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
288
289 u_upload_alloc(fd6_ctx->border_color_uploader,
290 0, FD6_BORDER_COLOR_UPLOAD_SIZE,
291 FD6_BORDER_COLOR_UPLOAD_SIZE, &off,
292 &fd6_ctx->border_color_buf,
293 &ptr);
294
295 entries = ptr;
296
297 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
298 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
299 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
300
301 OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
302 OUT_RELOC(ring, fd_resource(fd6_ctx->border_color_buf)->bo, off, 0, 0);
303
304 u_upload_unmap(fd6_ctx->border_color_uploader);
305 }
306
307 static bool
308 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
309 enum a6xx_state_block sb, struct fd_texture_stateobj *tex)
310 {
311 bool needs_border = false;
312 unsigned bcolor_offset;
313 unsigned opcode, tex_samp_reg, tex_const_reg;
314
315 switch (sb) {
316 case SB6_VS_TEX:
317 opcode = CP_LOAD_STATE6_GEOM;
318 bcolor_offset = 0;
319 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
320 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
321 break;
322 case SB6_FS_TEX:
323 opcode = CP_LOAD_STATE6_FRAG;
324 bcolor_offset = ctx->tex[PIPE_SHADER_VERTEX].num_samplers;
325 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
326 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
327 break;
328 case SB6_CS_TEX:
329 opcode = CP_LOAD_STATE6_FRAG;
330 bcolor_offset = 0;
331 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
332 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
333 break;
334 default:
335 unreachable("bad state block");
336 }
337
338
339 if (tex->num_samplers > 0) {
340 struct fd_ringbuffer *state =
341 fd_ringbuffer_new_object(ctx->pipe, tex->num_samplers * 4);
342 for (unsigned i = 0; i < tex->num_samplers; i++) {
343 static const struct fd6_sampler_stateobj dummy_sampler = {};
344 const struct fd6_sampler_stateobj *sampler = tex->samplers[i] ?
345 fd6_sampler_stateobj(tex->samplers[i]) : &dummy_sampler;
346 OUT_RING(state, sampler->texsamp0);
347 OUT_RING(state, sampler->texsamp1);
348 OUT_RING(state, sampler->texsamp2 |
349 A6XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset));
350 OUT_RING(state, sampler->texsamp3);
351 needs_border |= sampler->needs_border;
352 }
353
354 /* output sampler state: */
355 OUT_PKT7(ring, opcode, 3);
356 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
357 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
358 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
359 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
360 CP_LOAD_STATE6_0_NUM_UNIT(tex->num_samplers));
361 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
362
363 OUT_PKT4(ring, tex_samp_reg, 2);
364 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
365
366 fd_ringbuffer_del(state);
367 }
368
369 if (tex->num_textures > 0) {
370 struct fd_ringbuffer *state =
371 fd_ringbuffer_new_object(ctx->pipe, tex->num_textures * 16);
372 for (unsigned i = 0; i < tex->num_textures; i++) {
373 static const struct fd6_pipe_sampler_view dummy_view = {};
374 const struct fd6_pipe_sampler_view *view = tex->textures[i] ?
375 fd6_pipe_sampler_view(tex->textures[i]) : &dummy_view;
376 enum a6xx_tile_mode tile_mode = TILE6_LINEAR;
377
378 if (view->base.texture)
379 tile_mode = fd_resource(view->base.texture)->tile_mode;
380
381 OUT_RING(state, view->texconst0 |
382 A6XX_TEX_CONST_0_TILE_MODE(tile_mode));
383 OUT_RING(state, view->texconst1);
384 OUT_RING(state, view->texconst2);
385 OUT_RING(state, view->texconst3);
386
387 if (view->base.texture) {
388 struct fd_resource *rsc = fd_resource(view->base.texture);
389 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
390 rsc = rsc->stencil;
391 OUT_RELOC(state, rsc->bo, view->offset,
392 (uint64_t)view->texconst5 << 32, 0);
393 } else {
394 OUT_RING(state, 0x00000000);
395 OUT_RING(state, view->texconst5);
396 }
397
398 OUT_RING(state, view->texconst6);
399 OUT_RING(state, view->texconst7);
400 OUT_RING(state, view->texconst8);
401 OUT_RING(state, view->texconst9);
402 OUT_RING(state, view->texconst10);
403 OUT_RING(state, view->texconst11);
404 OUT_RING(state, 0);
405 OUT_RING(state, 0);
406 OUT_RING(state, 0);
407 OUT_RING(state, 0);
408 }
409
410 /* emit texture state: */
411 OUT_PKT7(ring, opcode, 3);
412 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
413 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
414 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
415 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
416 CP_LOAD_STATE6_0_NUM_UNIT(tex->num_textures));
417 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
418
419 OUT_PKT4(ring, tex_const_reg, 2);
420 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
421
422 fd_ringbuffer_del(state);
423 }
424
425 return needs_border;
426 }
427
428 static void
429 emit_ssbos(struct fd_context *ctx, struct fd_ringbuffer *ring,
430 enum a6xx_state_block sb, struct fd_shaderbuf_stateobj *so)
431 {
432 unsigned count = util_last_bit(so->enabled_mask);
433 unsigned opcode;
434
435 if (count == 0)
436 return;
437
438 switch (sb) {
439 case SB6_SSBO:
440 case SB6_CS_SSBO:
441 opcode = CP_LOAD_STATE6_GEOM;
442 break;
443 default:
444 unreachable("bad state block");
445 }
446
447 OUT_PKT7(ring, opcode, 3 + (4 * count));
448 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
449 CP_LOAD_STATE6_0_STATE_TYPE(0) |
450 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
451 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
452 CP_LOAD_STATE6_0_NUM_UNIT(count));
453 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
454 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
455 for (unsigned i = 0; i < count; i++) {
456 OUT_RING(ring, 0x00000000);
457 OUT_RING(ring, 0x00000000);
458 OUT_RING(ring, 0x00000000);
459 OUT_RING(ring, 0x00000000);
460 }
461
462 #if 0
463 OUT_PKT7(ring, opcode, 3 + (2 * count));
464 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
465 CP_LOAD_STATE6_0_STATE_TYPE(1) |
466 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
467 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
468 CP_LOAD_STATE6_0_NUM_UNIT(count));
469 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
470 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
471 for (unsigned i = 0; i < count; i++) {
472 struct pipe_shader_buffer *buf = &so->sb[i];
473 unsigned sz = buf->buffer_size;
474
475 /* width is in dwords, overflows into height: */
476 sz /= 4;
477
478 OUT_RING(ring, A6XX_SSBO_1_0_WIDTH(sz));
479 OUT_RING(ring, A6XX_SSBO_1_1_HEIGHT(sz >> 16));
480 }
481 #endif
482
483 OUT_PKT7(ring, opcode, 3 + (2 * count));
484 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
485 CP_LOAD_STATE6_0_STATE_TYPE(2) |
486 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
487 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
488 CP_LOAD_STATE6_0_NUM_UNIT(count));
489 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
490 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
491 for (unsigned i = 0; i < count; i++) {
492 struct pipe_shader_buffer *buf = &so->sb[i];
493 if (buf->buffer) {
494 struct fd_resource *rsc = fd_resource(buf->buffer);
495 OUT_RELOCW(ring, rsc->bo, buf->buffer_offset, 0, 0);
496 } else {
497 OUT_RING(ring, 0x00000000);
498 OUT_RING(ring, 0x00000000);
499 }
500 }
501 }
502
503 void
504 fd6_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd6_emit *emit)
505 {
506 int32_t i, j;
507 const struct fd_vertex_state *vtx = emit->vtx;
508 const struct ir3_shader_variant *vp = fd6_emit_get_vp(emit);
509
510 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
511 if (vp->inputs[i].sysval)
512 continue;
513 if (vp->inputs[i].compmask) {
514 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
515 const struct pipe_vertex_buffer *vb =
516 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
517 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
518 enum pipe_format pfmt = elem->src_format;
519 enum a6xx_vtx_fmt fmt = fd6_pipe2vtx(pfmt);
520 bool isint = util_format_is_pure_integer(pfmt);
521 uint32_t off = vb->buffer_offset + elem->src_offset;
522 uint32_t size = fd_bo_size(rsc->bo) - off;
523 debug_assert(fmt != ~0);
524
525 OUT_PKT4(ring, REG_A6XX_VFD_FETCH(j), 4);
526 OUT_RELOC(ring, rsc->bo, off, 0, 0);
527 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
528 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
529
530 OUT_PKT4(ring, REG_A6XX_VFD_DECODE(j), 2);
531 OUT_RING(ring, A6XX_VFD_DECODE_INSTR_IDX(j) |
532 A6XX_VFD_DECODE_INSTR_FORMAT(fmt) |
533 COND(elem->instance_divisor, A6XX_VFD_DECODE_INSTR_INSTANCED) |
534 A6XX_VFD_DECODE_INSTR_SWAP(fd6_pipe2swap(pfmt)) |
535 A6XX_VFD_DECODE_INSTR_UNK30 |
536 COND(!isint, A6XX_VFD_DECODE_INSTR_FLOAT));
537 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
538
539 OUT_PKT4(ring, REG_A6XX_VFD_DEST_CNTL(j), 1);
540 OUT_RING(ring, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
541 A6XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
542
543 j++;
544 }
545 }
546
547 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_0, 1);
548 OUT_RING(ring, A6XX_VFD_CONTROL_0_VTXCNT(j) | (j << 8));
549 }
550
551 void
552 fd6_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
553 struct fd6_emit *emit)
554 {
555 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
556 const struct ir3_shader_variant *vp = fd6_emit_get_vp(emit);
557 const struct ir3_shader_variant *fp = fd6_emit_get_fp(emit);
558 const enum fd_dirty_3d_state dirty = emit->dirty;
559 bool needs_border = false;
560
561 emit_marker6(ring, 5);
562
563 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
564 unsigned char mrt_comp[A6XX_MAX_RENDER_TARGETS] = {0};
565
566 for (unsigned i = 0; i < pfb->nr_cbufs; i++) {
567 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
568 }
569
570 OUT_PKT4(ring, REG_A6XX_RB_RENDER_COMPONENTS, 1);
571 OUT_RING(ring, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
572 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
573 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
574 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
575 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
576 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
577 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
578 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
579
580 OUT_PKT4(ring, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
581 OUT_RING(ring,
582 A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
583 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[0]) |
584 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[0]) |
585 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[0]) |
586 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[0]) |
587 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[0]) |
588 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[0]) |
589 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[0]));
590 }
591
592 if (dirty & FD_DIRTY_ZSA) {
593 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
594 uint32_t rb_alpha_control = zsa->rb_alpha_control;
595
596 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
597 rb_alpha_control &= ~A6XX_RB_ALPHA_CONTROL_ALPHA_TEST;
598
599 OUT_PKT4(ring, REG_A6XX_RB_ALPHA_CONTROL, 1);
600 OUT_RING(ring, rb_alpha_control);
601
602 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_CONTROL, 1);
603 OUT_RING(ring, zsa->rb_stencil_control);
604 }
605
606 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG)) {
607 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
608 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
609
610 if (pfb->zsbuf) {
611 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
612 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
613
614 if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid)
615 gras_lrz_cntl = 0;
616 else if (emit->key.binning_pass && blend->lrz_write && zsa->lrz_write)
617 gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_LRZ_WRITE;
618
619 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
620 OUT_RING(ring, gras_lrz_cntl);
621 }
622 }
623
624 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
625 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
626 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
627
628 OUT_PKT4(ring, REG_A6XX_RB_STENCILREF, 3);
629 OUT_RING(ring, A6XX_RB_STENCILREF_REF(sr->ref_value[0])); // TODO bf?
630 OUT_RING(ring, zsa->rb_stencilmask);
631 OUT_RING(ring, zsa->rb_stencilwrmask);
632 }
633
634 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
635 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
636 //bool fragz = fp->has_kill | fp->writes_pos;
637
638 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_CNTL, 1);
639 OUT_RING(ring, zsa->rb_depth_cntl);
640
641 #if 0
642 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
643 OUT_RING(ring, COND(fragz, A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
644 COND(fragz && fp->frag_coord, A6XX_RB_DEPTH_PLANE_CNTL_UNK1));
645
646 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
647 OUT_RING(ring, COND(fragz, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
648 COND(fragz && fp->frag_coord, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1));
649 #endif
650 }
651
652 if (dirty & FD_DIRTY_SCISSOR) {
653 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
654
655 OUT_PKT4(ring, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
656 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
657 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
658 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
659 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
660
661 OUT_PKT4(ring, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
662 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
663 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
664 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
665 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
666
667 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
668 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
669 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
670 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
671 }
672
673 if (dirty & FD_DIRTY_VIEWPORT) {
674 fd_wfi(ctx->batch, ring);
675 OUT_PKT4(ring, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
676 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
677 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
678 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
679 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
680 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
681 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
682 }
683
684 if (dirty & FD_DIRTY_PROG)
685 fd6_program_emit(ctx, ring, emit);
686
687 if (dirty & FD_DIRTY_RASTERIZER) {
688 struct fd6_rasterizer_stateobj *rasterizer =
689 fd6_rasterizer_stateobj(ctx->rasterizer);
690
691 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8000, 1);
692 OUT_RING(ring, 0x80);
693 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8001, 1);
694 OUT_RING(ring, 0x0);
695 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8004, 1);
696 OUT_RING(ring, 0x0);
697
698 OUT_PKT4(ring, REG_A6XX_GRAS_SU_CNTL, 1);
699 OUT_RING(ring, rasterizer->gras_su_cntl);
700
701 OUT_PKT4(ring, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
702 OUT_RING(ring, rasterizer->gras_su_point_minmax);
703 OUT_RING(ring, rasterizer->gras_su_point_size);
704
705 OUT_PKT4(ring, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
706 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
707 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
708 OUT_RING(ring, rasterizer->gras_su_poly_offset_clamp);
709
710 #if 0
711 OUT_PKT4(ring, REG_A6XX_PC_RASTER_CNTL, 1);
712 OUT_RING(ring, rasterizer->pc_raster_cntl);
713
714 OUT_PKT4(ring, REG_A6XX_GRAS_CL_CNTL, 1);
715 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
716 #endif
717 }
718
719 /* note: must come after program emit.. because there is some overlap
720 * in registers, ex. PC_PRIMITIVE_CNTL and we rely on some cached
721 * values from fd6_program_emit() to avoid having to re-emit the prog
722 * every time rast state changes.
723 *
724 * Since the primitive restart state is not part of a tracked object, we
725 * re-emit this register every time.
726 */
727 if (emit->info && ctx->rasterizer) {
728 struct fd6_rasterizer_stateobj *rasterizer =
729 fd6_rasterizer_stateobj(ctx->rasterizer);
730 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9806, 1);
731 OUT_RING(ring, 0);
732 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9990, 1);
733 OUT_RING(ring, 0);
734 OUT_PKT4(ring, REG_A6XX_VFD_UNKNOWN_A008, 1);
735 OUT_RING(ring, 0);
736
737
738 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
739 OUT_RING(ring, rasterizer->pc_primitive_cntl |
740 COND(emit->info->primitive_restart && emit->info->index_size,
741 A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART));
742 }
743
744 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
745 uint32_t posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
746 unsigned nr = pfb->nr_cbufs;
747
748 if (emit->key.binning_pass)
749 nr = 0;
750 else if (ctx->rasterizer->rasterizer_discard)
751 nr = 0;
752
753 OUT_PKT4(ring, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
754 OUT_RING(ring, COND(fp->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z));
755 OUT_RING(ring, A6XX_RB_FS_OUTPUT_CNTL1_MRT(nr));
756
757 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
758 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
759 0xfcfc0000);
760 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL1_MRT(nr));
761 }
762
763 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
764 if (!emit->key.binning_pass)
765 ir3_emit_fs_consts(fp, ring, ctx);
766
767 struct pipe_stream_output_info *info = &vp->shader->stream_output;
768 if (info->num_outputs) {
769 struct fd_streamout_stateobj *so = &ctx->streamout;
770
771 for (unsigned i = 0; i < so->num_targets; i++) {
772 struct pipe_stream_output_target *target = so->targets[i];
773
774 if (!target)
775 continue;
776
777 unsigned offset = (so->offsets[i] * info->stride[i] * 4) +
778 target->buffer_offset;
779
780 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(i), 3);
781 /* VPC_SO[i].BUFFER_BASE_LO: */
782 OUT_RELOCW(ring, fd_resource(target->buffer)->bo, 0, 0, 0);
783 OUT_RING(ring, target->buffer_size + offset);
784
785 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(i), 3);
786 OUT_RING(ring, offset);
787 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
788 // TODO just give hw a dummy addr for now.. we should
789 // be using this an then CP_MEM_TO_REG to set the
790 // VPC_SO[i].BUFFER_OFFSET for the next draw..
791 OUT_RELOCW(ring, fd6_context(ctx)->blit_mem, 0x100, 0, 0);
792
793 emit->streamout_mask |= (1 << i);
794 }
795 }
796
797 if ((dirty & FD_DIRTY_BLEND)) {
798 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
799 uint32_t i;
800
801 for (i = 0; i < A6XX_MAX_RENDER_TARGETS; i++) {
802 enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
803 bool is_int = util_format_is_pure_integer(format);
804 bool has_alpha = util_format_has_alpha(format);
805 uint32_t control = blend->rb_mrt[i].control;
806 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
807
808 if (is_int) {
809 control &= A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
810 control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
811 }
812
813 if (has_alpha) {
814 blend_control |= blend->rb_mrt[i].blend_control_rgb;
815 } else {
816 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
817 control &= ~A6XX_RB_MRT_CONTROL_BLEND2;
818 }
819
820 OUT_PKT4(ring, REG_A6XX_RB_MRT_CONTROL(i), 1);
821 OUT_RING(ring, control);
822
823 OUT_PKT4(ring, REG_A6XX_RB_MRT_BLEND_CONTROL(i), 1);
824 OUT_RING(ring, blend_control);
825 }
826
827 OUT_PKT4(ring, REG_A6XX_RB_BLEND_CNTL, 1);
828 OUT_RING(ring, blend->rb_blend_cntl |
829 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(0xffff));
830
831 OUT_PKT4(ring, REG_A6XX_SP_BLEND_CNTL, 1);
832 OUT_RING(ring, blend->sp_blend_cntl);
833 }
834
835 if (dirty & FD_DIRTY_BLEND_COLOR) {
836 struct pipe_blend_color *bcolor = &ctx->blend_color;
837
838 OUT_PKT4(ring, REG_A6XX_RB_BLEND_RED_F32, 4);
839 OUT_RING(ring, A6XX_RB_BLEND_RED_F32(bcolor->color[0]));
840 OUT_RING(ring, A6XX_RB_BLEND_GREEN_F32(bcolor->color[1]));
841 OUT_RING(ring, A6XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
842 OUT_RING(ring, A6XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
843 }
844
845 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX) {
846 needs_border |= emit_textures(ctx, ring, SB6_VS_TEX,
847 &ctx->tex[PIPE_SHADER_VERTEX]);
848 OUT_PKT4(ring, REG_A6XX_SP_VS_TEX_COUNT, 1);
849 OUT_RING(ring, ctx->tex[PIPE_SHADER_VERTEX].num_textures);
850 }
851
852 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX) {
853 needs_border |= emit_textures(ctx, ring, SB6_FS_TEX,
854 &ctx->tex[PIPE_SHADER_FRAGMENT]);
855 OUT_PKT4(ring, REG_A6XX_SP_FS_TEX_COUNT, 1);
856 OUT_RING(ring, ctx->tex[PIPE_SHADER_FRAGMENT].num_textures);
857 }
858
859 #if 0
860 OUT_PKT4(ring, REG_A6XX_TPL1_FS_TEX_COUNT, 1);
861 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_FRAGMENT].enabled_mask ?
862 ~0 : ctx->tex[PIPE_SHADER_FRAGMENT].num_textures);
863
864 OUT_PKT4(ring, REG_A6XX_TPL1_CS_TEX_COUNT, 1);
865 OUT_RING(ring, 0);
866 #endif
867
868 if (needs_border)
869 emit_border_color(ctx, ring);
870
871 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_SSBO)
872 emit_ssbos(ctx, ring, SB6_SSBO, &ctx->shaderbuf[PIPE_SHADER_FRAGMENT]);
873
874 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_IMAGE)
875 fd6_emit_images(ctx, ring, PIPE_SHADER_FRAGMENT);
876 }
877
878 void
879 fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
880 struct ir3_shader_variant *cp)
881 {
882 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
883
884 if (dirty & FD_DIRTY_SHADER_TEX) {
885 bool needs_border = false;
886 needs_border |= emit_textures(ctx, ring, SB6_CS_TEX,
887 &ctx->tex[PIPE_SHADER_COMPUTE]);
888
889 if (needs_border)
890 emit_border_color(ctx, ring);
891
892 #if 0
893 OUT_PKT4(ring, REG_A6XX_TPL1_VS_TEX_COUNT, 1);
894 OUT_RING(ring, 0);
895
896 OUT_PKT4(ring, REG_A6XX_TPL1_HS_TEX_COUNT, 1);
897 OUT_RING(ring, 0);
898
899 OUT_PKT4(ring, REG_A6XX_TPL1_DS_TEX_COUNT, 1);
900 OUT_RING(ring, 0);
901
902 OUT_PKT4(ring, REG_A6XX_TPL1_GS_TEX_COUNT, 1);
903 OUT_RING(ring, 0);
904
905 OUT_PKT4(ring, REG_A6XX_TPL1_FS_TEX_COUNT, 1);
906 OUT_RING(ring, 0);
907 #endif
908 }
909
910 #if 0
911 OUT_PKT4(ring, REG_A6XX_TPL1_CS_TEX_COUNT, 1);
912 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_COMPUTE].enabled_mask ?
913 ~0 : ctx->tex[PIPE_SHADER_COMPUTE].num_textures);
914 #endif
915
916 if (dirty & FD_DIRTY_SHADER_SSBO)
917 emit_ssbos(ctx, ring, SB6_CS_SSBO, &ctx->shaderbuf[PIPE_SHADER_COMPUTE]);
918
919 if (dirty & FD_DIRTY_SHADER_IMAGE)
920 fd6_emit_images(ctx, ring, PIPE_SHADER_COMPUTE);
921 }
922
923
924 /* emit setup at begin of new cmdstream buffer (don't rely on previous
925 * state, there could have been a context switch between ioctls):
926 */
927 void
928 fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
929 {
930 //struct fd_context *ctx = batch->ctx;
931
932 fd6_cache_flush(batch, ring);
933
934 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
935 OUT_RING(ring, 0xfffff);
936
937 /*
938 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
939 0000000500024048: 70d08003 00000000 001c5000 00000005
940 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
941 0000000500024058: 70d08003 00000010 001c7000 00000005
942
943 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
944 0000000500024068: 70268000
945 */
946
947 WRITE(REG_A6XX_RB_CCU_CNTL, 0x7c400004);
948 WRITE(REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
949 WRITE(REG_A6XX_SP_UNKNOWN_AE04, 0x8);
950 WRITE(REG_A6XX_SP_UNKNOWN_AE00, 0);
951 WRITE(REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
952 WRITE(REG_A6XX_SP_UNKNOWN_B605, 0x44);
953 WRITE(REG_A6XX_SP_UNKNOWN_B600, 0x100000);
954 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
955 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
956
957 WRITE(REG_A6XX_VPC_UNKNOWN_9600, 0);
958 WRITE(REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
959 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
960 WRITE(REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
961 WRITE(REG_A6XX_SP_UNKNOWN_AB20, 0);
962 WRITE(REG_A6XX_SP_UNKNOWN_B182, 0);
963 WRITE(REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
964 WRITE(REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
965 WRITE(REG_A6XX_UCHE_CLIENT_PF, 4);
966 WRITE(REG_A6XX_RB_UNKNOWN_8E01, 0x0);
967 WRITE(REG_A6XX_SP_UNKNOWN_AB00, 0x5);
968 WRITE(REG_A6XX_VFD_UNKNOWN_A009, 0x00000001);
969 WRITE(REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
970 WRITE(REG_A6XX_PC_MODE_CNTL, 0x1f);
971
972 OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
973 OUT_RING(ring, 0);
974
975 WRITE(REG_A6XX_GRAS_UNKNOWN_8101, 0);
976 WRITE(REG_A6XX_GRAS_2D_BLIT_INFO,
977 A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(RB6_R8G8B8_UNORM));
978 WRITE(REG_A6XX_GRAS_UNKNOWN_8109, 0);
979 WRITE(REG_A6XX_GRAS_UNKNOWN_8110, 0);
980
981 WRITE(REG_A6XX_RB_RENDER_CONTROL0, 0x401);
982 WRITE(REG_A6XX_RB_RENDER_CONTROL1, 0);
983 WRITE(REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
984 WRITE(REG_A6XX_RB_UNKNOWN_8810, 0);
985 WRITE(REG_A6XX_RB_UNKNOWN_8818, 0);
986 WRITE(REG_A6XX_RB_UNKNOWN_8819, 0);
987 WRITE(REG_A6XX_RB_UNKNOWN_881A, 0);
988 WRITE(REG_A6XX_RB_UNKNOWN_881B, 0);
989 WRITE(REG_A6XX_RB_UNKNOWN_881C, 0);
990 WRITE(REG_A6XX_RB_UNKNOWN_881D, 0);
991 WRITE(REG_A6XX_RB_UNKNOWN_881E, 0);
992 WRITE(REG_A6XX_RB_UNKNOWN_88F0, 0);
993
994 WRITE(REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
995 WRITE(REG_A6XX_VPC_UNKNOWN_9107, 0);
996
997 WRITE(REG_A6XX_VPC_UNKNOWN_9236, 1);
998 WRITE(REG_A6XX_VPC_UNKNOWN_9300, 0);
999
1000 WRITE(REG_A6XX_VPC_SO_OVERRIDE, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
1001
1002 WRITE(REG_A6XX_PC_UNKNOWN_9801, 0);
1003 WRITE(REG_A6XX_PC_UNKNOWN_9806, 0);
1004 WRITE(REG_A6XX_PC_UNKNOWN_9980, 0);
1005
1006 WRITE(REG_A6XX_PC_UNKNOWN_9B06, 0);
1007 WRITE(REG_A6XX_PC_UNKNOWN_9B06, 0);
1008
1009 WRITE(REG_A6XX_SP_UNKNOWN_A81B, 0);
1010
1011 WRITE(REG_A6XX_SP_UNKNOWN_B183, 0);
1012
1013 WRITE(REG_A6XX_GRAS_UNKNOWN_8099, 0);
1014 WRITE(REG_A6XX_GRAS_UNKNOWN_809B, 0);
1015 WRITE(REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1016 WRITE(REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1017 WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
1018 WRITE(REG_A6XX_VPC_UNKNOWN_9211, 0);
1019 WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
1020 WRITE(REG_A6XX_PC_UNKNOWN_9981, 0x3);
1021 WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
1022 WRITE(REG_A6XX_VPC_UNKNOWN_9108, 0x3);
1023 WRITE(REG_A6XX_SP_TP_UNKNOWN_B304, 0);
1024 WRITE(REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
1025 WRITE(REG_A6XX_RB_UNKNOWN_8804, 0);
1026 WRITE(REG_A6XX_GRAS_UNKNOWN_80A4, 0);
1027 WRITE(REG_A6XX_GRAS_UNKNOWN_80A5, 0);
1028 WRITE(REG_A6XX_GRAS_UNKNOWN_80A6, 0);
1029 WRITE(REG_A6XX_RB_UNKNOWN_8805, 0);
1030 WRITE(REG_A6XX_RB_UNKNOWN_8806, 0);
1031 WRITE(REG_A6XX_RB_UNKNOWN_8878, 0);
1032 WRITE(REG_A6XX_RB_UNKNOWN_8879, 0);
1033 WRITE(REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1034
1035 emit_marker6(ring, 7);
1036
1037 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
1038 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
1039
1040 WRITE(REG_A6XX_VFD_UNKNOWN_A008, 0);
1041
1042 OUT_PKT4(ring, REG_A6XX_PC_MODE_CNTL, 1);
1043 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
1044
1045 /* we don't use this yet.. probably best to disable.. */
1046 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1047 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1048 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1049 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1050 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1051 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1052
1053 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
1054 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
1055 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
1056 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
1057
1058 OUT_PKT4(ring, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
1059 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
1060 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1061
1062 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1063 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
1064
1065 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
1066 OUT_RING(ring, 0x00000000); /* UNKNOWN_E2AB */
1067
1068 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1069 OUT_RING(ring, 0x00000000);
1070 OUT_RING(ring, 0x00000000);
1071 OUT_RING(ring, 0x00000000);
1072
1073 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
1074 OUT_RING(ring, 0x00000000);
1075 OUT_RING(ring, 0x00000000);
1076 OUT_RING(ring, 0x00000000);
1077 OUT_RING(ring, 0x00000000);
1078 OUT_RING(ring, 0x00000000);
1079 OUT_RING(ring, 0x00000000);
1080
1081 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
1082 OUT_RING(ring, 0x00000000);
1083 OUT_RING(ring, 0x00000000);
1084 OUT_RING(ring, 0x00000000);
1085 OUT_RING(ring, 0x00000000);
1086 OUT_RING(ring, 0x00000000);
1087 OUT_RING(ring, 0x00000000);
1088
1089 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
1090 OUT_RING(ring, 0x00000000);
1091 OUT_RING(ring, 0x00000000);
1092 OUT_RING(ring, 0x00000000);
1093
1094 OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1);
1095 OUT_RING(ring, 0x00000000);
1096
1097 OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
1098 OUT_RING(ring, 0x00000000);
1099 }
1100
1101 static void
1102 fd6_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
1103 {
1104 emit_marker6(ring, 6);
1105 __OUT_IB5(ring, target);
1106 emit_marker6(ring, 6);
1107 }
1108
1109 static void
1110 fd6_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
1111 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
1112 unsigned sizedwords)
1113 {
1114 struct fd_bo *src_bo = fd_resource(src)->bo;
1115 struct fd_bo *dst_bo = fd_resource(dst)->bo;
1116 unsigned i;
1117
1118 for (i = 0; i < sizedwords; i++) {
1119 OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
1120 OUT_RING(ring, 0x00000000);
1121 OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
1122 OUT_RELOC (ring, src_bo, src_off, 0, 0);
1123
1124 dst_off += 4;
1125 src_off += 4;
1126 }
1127 }
1128
1129 void
1130 fd6_emit_init(struct pipe_context *pctx)
1131 {
1132 struct fd_context *ctx = fd_context(pctx);
1133 ctx->emit_const = fd6_emit_const;
1134 ctx->emit_const_bo = fd6_emit_const_bo;
1135 ctx->emit_ib = fd6_emit_ib;
1136 ctx->mem_to_mem = fd6_mem_to_mem;
1137 }