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freedreno/a6xx: move tile_mode to sampler-view CSO
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_helpers.h"
32 #include "util/u_format.h"
33 #include "util/u_viewport.h"
34
35 #include "freedreno_resource.h"
36 #include "freedreno_query_hw.h"
37
38 #include "fd6_emit.h"
39 #include "fd6_blend.h"
40 #include "fd6_context.h"
41 #include "fd6_image.h"
42 #include "fd6_program.h"
43 #include "fd6_rasterizer.h"
44 #include "fd6_texture.h"
45 #include "fd6_format.h"
46 #include "fd6_zsa.h"
47
48 static uint32_t
49 shader_t_to_opcode(gl_shader_stage type)
50 {
51 switch (type) {
52 case MESA_SHADER_VERTEX:
53 case MESA_SHADER_TESS_CTRL:
54 case MESA_SHADER_TESS_EVAL:
55 case MESA_SHADER_GEOMETRY:
56 return CP_LOAD_STATE6_GEOM;
57 case MESA_SHADER_FRAGMENT:
58 case MESA_SHADER_COMPUTE:
59 return CP_LOAD_STATE6_FRAG;
60 default:
61 unreachable("bad shader type");
62 }
63 }
64
65 /* regid: base const register
66 * prsc or dwords: buffer containing constant values
67 * sizedwords: size of const value buffer
68 */
69 static void
70 fd6_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
71 uint32_t regid, uint32_t offset, uint32_t sizedwords,
72 const uint32_t *dwords, struct pipe_resource *prsc)
73 {
74 uint32_t i, sz;
75 enum a6xx_state_src src;
76
77 debug_assert((regid % 4) == 0);
78 debug_assert((sizedwords % 4) == 0);
79
80 if (prsc) {
81 sz = 0;
82 src = SS6_INDIRECT;
83 } else {
84 sz = sizedwords;
85 src = SS6_DIRECT;
86 }
87
88 OUT_PKT7(ring, shader_t_to_opcode(type), 3 + sz);
89 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
90 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
91 CP_LOAD_STATE6_0_STATE_SRC(src) |
92 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
93 CP_LOAD_STATE6_0_NUM_UNIT(sizedwords/4));
94 if (prsc) {
95 struct fd_bo *bo = fd_resource(prsc)->bo;
96 OUT_RELOC(ring, bo, offset, 0, 0);
97 } else {
98 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
99 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
100 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
101 }
102 for (i = 0; i < sz; i++) {
103 OUT_RING(ring, dwords[i]);
104 }
105 }
106
107 static void
108 fd6_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
109 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
110 {
111 uint32_t anum = align(num, 2);
112 uint32_t i;
113
114 debug_assert((regid % 4) == 0);
115
116 OUT_PKT7(ring, shader_t_to_opcode(type), 3 + (2 * anum));
117 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
118 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS)|
119 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
120 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
121 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
122 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
123 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
124
125 for (i = 0; i < num; i++) {
126 if (prscs[i]) {
127 if (write) {
128 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
129 } else {
130 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
131 }
132 } else {
133 OUT_RING(ring, 0xbad00000 | (i << 16));
134 OUT_RING(ring, 0xbad00000 | (i << 16));
135 }
136 }
137
138 for (; i < anum; i++) {
139 OUT_RING(ring, 0xffffffff);
140 OUT_RING(ring, 0xffffffff);
141 }
142 }
143
144 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
145 * the same as a6xx then move this somewhere common ;-)
146 *
147 * Entry layout looks like (total size, 0x60 bytes):
148 */
149
150 struct PACKED bcolor_entry {
151 uint32_t fp32[4];
152 uint16_t ui16[4];
153 int16_t si16[4];
154 uint16_t fp16[4];
155 uint16_t rgb565;
156 uint16_t rgb5a1;
157 uint16_t rgba4;
158 uint8_t __pad0[2];
159 uint8_t ui8[4];
160 int8_t si8[4];
161 uint32_t rgb10a2;
162 uint32_t z24; /* also s8? */
163 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
164 uint8_t __pad1[24];
165 };
166
167 #define FD6_BORDER_COLOR_SIZE 0x60
168 #define FD6_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD6_BORDER_COLOR_SIZE)
169
170 static void
171 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
172 {
173 unsigned i, j;
174 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
175
176 for (i = 0; i < tex->num_samplers; i++) {
177 struct bcolor_entry *e = &entries[i];
178 struct pipe_sampler_state *sampler = tex->samplers[i];
179 union pipe_color_union *bc;
180
181 if (!sampler)
182 continue;
183
184 bc = &sampler->border_color;
185
186 /*
187 * XXX HACK ALERT XXX
188 *
189 * The border colors need to be swizzled in a particular
190 * format-dependent order. Even though samplers don't know about
191 * formats, we can assume that with a GL state tracker, there's a
192 * 1:1 correspondence between sampler and texture. Take advantage
193 * of that knowledge.
194 */
195 if ((i >= tex->num_textures) || !tex->textures[i])
196 continue;
197
198 enum pipe_format format = tex->textures[i]->format;
199 const struct util_format_description *desc =
200 util_format_description(format);
201
202 e->rgb565 = 0;
203 e->rgb5a1 = 0;
204 e->rgba4 = 0;
205 e->rgb10a2 = 0;
206 e->z24 = 0;
207
208 for (j = 0; j < 4; j++) {
209 int c = desc->swizzle[j];
210 int cd = c;
211
212 /*
213 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the
214 * stencil border color value in bc->ui[0] but according
215 * to desc->swizzle and desc->channel, the .x component
216 * is NONE and the stencil value is in the y component.
217 * Meanwhile the hardware wants this in the .x componetn.
218 */
219 if ((format == PIPE_FORMAT_X24S8_UINT) ||
220 (format == PIPE_FORMAT_X32_S8X24_UINT)) {
221 if (j == 0) {
222 c = 1;
223 cd = 0;
224 } else {
225 continue;
226 }
227 }
228
229 if (c >= 4)
230 continue;
231
232 if (desc->channel[c].pure_integer) {
233 uint16_t clamped;
234 switch (desc->channel[c].size) {
235 case 2:
236 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
237 clamped = CLAMP(bc->ui[j], 0, 0x3);
238 break;
239 case 8:
240 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
241 clamped = CLAMP(bc->i[j], -128, 127);
242 else
243 clamped = CLAMP(bc->ui[j], 0, 255);
244 break;
245 case 10:
246 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
247 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
248 break;
249 case 16:
250 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
251 clamped = CLAMP(bc->i[j], -32768, 32767);
252 else
253 clamped = CLAMP(bc->ui[j], 0, 65535);
254 break;
255 default:
256 assert(!"Unexpected bit size");
257 case 32:
258 clamped = 0;
259 break;
260 }
261 e->fp32[cd] = bc->ui[j];
262 e->fp16[cd] = clamped;
263 } else {
264 float f = bc->f[j];
265 float f_u = CLAMP(f, 0, 1);
266 float f_s = CLAMP(f, -1, 1);
267
268 e->fp32[c] = fui(f);
269 e->fp16[c] = util_float_to_half(f);
270 e->srgb[c] = util_float_to_half(f_u);
271 e->ui16[c] = f_u * 0xffff;
272 e->si16[c] = f_s * 0x7fff;
273 e->ui8[c] = f_u * 0xff;
274 e->si8[c] = f_s * 0x7f;
275 if (c == 1)
276 e->rgb565 |= (int)(f_u * 0x3f) << 5;
277 else if (c < 3)
278 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
279 if (c == 3)
280 e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
281 else
282 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
283 if (c == 3)
284 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
285 else
286 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
287 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
288 if (c == 0)
289 e->z24 = f_u * 0xffffff;
290 }
291 }
292
293 #ifdef DEBUG
294 memset(&e->__pad0, 0, sizeof(e->__pad0));
295 memset(&e->__pad1, 0, sizeof(e->__pad1));
296 #endif
297 }
298 }
299
300 static void
301 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
302 {
303 struct fd6_context *fd6_ctx = fd6_context(ctx);
304 struct bcolor_entry *entries;
305 unsigned off;
306 void *ptr;
307
308 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
309
310 u_upload_alloc(fd6_ctx->border_color_uploader,
311 0, FD6_BORDER_COLOR_UPLOAD_SIZE,
312 FD6_BORDER_COLOR_UPLOAD_SIZE, &off,
313 &fd6_ctx->border_color_buf,
314 &ptr);
315
316 entries = ptr;
317
318 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
319 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
320 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
321
322 OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
323 OUT_RELOC(ring, fd_resource(fd6_ctx->border_color_buf)->bo, off, 0, 0);
324
325 u_upload_unmap(fd6_ctx->border_color_uploader);
326 }
327
328 bool
329 fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
330 enum a6xx_state_block sb, struct fd_texture_stateobj *tex,
331 unsigned bcolor_offset)
332 {
333 bool needs_border = false;
334 unsigned opcode, tex_samp_reg, tex_const_reg, tex_count_reg;
335
336 switch (sb) {
337 case SB6_VS_TEX:
338 opcode = CP_LOAD_STATE6_GEOM;
339 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
340 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
341 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
342 break;
343 case SB6_FS_TEX:
344 opcode = CP_LOAD_STATE6_FRAG;
345 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
346 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
347 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
348 break;
349 case SB6_CS_TEX:
350 opcode = CP_LOAD_STATE6_FRAG;
351 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
352 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
353 tex_count_reg = 0; //REG_A6XX_SP_CS_TEX_COUNT;
354 break;
355 default:
356 unreachable("bad state block");
357 }
358
359
360 if (tex->num_samplers > 0) {
361 struct fd_ringbuffer *state =
362 fd_ringbuffer_new_object(pipe, tex->num_samplers * 4 * 4);
363 for (unsigned i = 0; i < tex->num_samplers; i++) {
364 static const struct fd6_sampler_stateobj dummy_sampler = {};
365 const struct fd6_sampler_stateobj *sampler = tex->samplers[i] ?
366 fd6_sampler_stateobj(tex->samplers[i]) : &dummy_sampler;
367 OUT_RING(state, sampler->texsamp0);
368 OUT_RING(state, sampler->texsamp1);
369 OUT_RING(state, sampler->texsamp2 |
370 A6XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset));
371 OUT_RING(state, sampler->texsamp3);
372 needs_border |= sampler->needs_border;
373 }
374
375 /* output sampler state: */
376 OUT_PKT7(ring, opcode, 3);
377 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
378 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
379 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
380 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
381 CP_LOAD_STATE6_0_NUM_UNIT(tex->num_samplers));
382 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
383
384 OUT_PKT4(ring, tex_samp_reg, 2);
385 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
386
387 fd_ringbuffer_del(state);
388 }
389
390 if (tex->num_textures > 0) {
391 struct fd_ringbuffer *state =
392 fd_ringbuffer_new_object(pipe, tex->num_textures * 16 * 4);
393 for (unsigned i = 0; i < tex->num_textures; i++) {
394 static const struct fd6_pipe_sampler_view dummy_view = {};
395 const struct fd6_pipe_sampler_view *view = tex->textures[i] ?
396 fd6_pipe_sampler_view(tex->textures[i]) : &dummy_view;
397
398 OUT_RING(state, view->texconst0);
399 OUT_RING(state, view->texconst1);
400 OUT_RING(state, view->texconst2);
401 OUT_RING(state, view->texconst3);
402
403 if (view->base.texture) {
404 struct fd_resource *rsc = fd_resource(view->base.texture);
405 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
406 rsc = rsc->stencil;
407 OUT_RELOC(state, rsc->bo, view->offset,
408 (uint64_t)view->texconst5 << 32, 0);
409 } else {
410 OUT_RING(state, 0x00000000);
411 OUT_RING(state, view->texconst5);
412 }
413
414 OUT_RING(state, view->texconst6);
415 OUT_RING(state, view->texconst7);
416 OUT_RING(state, view->texconst8);
417 OUT_RING(state, view->texconst9);
418 OUT_RING(state, view->texconst10);
419 OUT_RING(state, view->texconst11);
420 OUT_RING(state, 0);
421 OUT_RING(state, 0);
422 OUT_RING(state, 0);
423 OUT_RING(state, 0);
424 }
425
426 /* emit texture state: */
427 OUT_PKT7(ring, opcode, 3);
428 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
429 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
430 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
431 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
432 CP_LOAD_STATE6_0_NUM_UNIT(tex->num_textures));
433 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
434
435 OUT_PKT4(ring, tex_const_reg, 2);
436 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
437
438 fd_ringbuffer_del(state);
439 }
440
441 if (tex_count_reg) {
442 OUT_PKT4(ring, tex_count_reg, 1);
443 OUT_RING(ring, tex->num_textures);
444 }
445
446 return needs_border;
447 }
448
449 static void
450 emit_ssbos(struct fd_context *ctx, struct fd_ringbuffer *ring,
451 enum a6xx_state_block sb, struct fd_shaderbuf_stateobj *so)
452 {
453 unsigned count = util_last_bit(so->enabled_mask);
454 unsigned opcode;
455
456 if (count == 0)
457 return;
458
459 switch (sb) {
460 case SB6_SSBO:
461 case SB6_CS_SSBO:
462 opcode = CP_LOAD_STATE6_GEOM;
463 break;
464 default:
465 unreachable("bad state block");
466 }
467
468 OUT_PKT7(ring, opcode, 3 + (4 * count));
469 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
470 CP_LOAD_STATE6_0_STATE_TYPE(0) |
471 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
472 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
473 CP_LOAD_STATE6_0_NUM_UNIT(count));
474 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
475 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
476 for (unsigned i = 0; i < count; i++) {
477 OUT_RING(ring, 0x00000000);
478 OUT_RING(ring, 0x00000000);
479 OUT_RING(ring, 0x00000000);
480 OUT_RING(ring, 0x00000000);
481 }
482
483 #if 0
484 OUT_PKT7(ring, opcode, 3 + (2 * count));
485 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
486 CP_LOAD_STATE6_0_STATE_TYPE(1) |
487 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
488 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
489 CP_LOAD_STATE6_0_NUM_UNIT(count));
490 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
491 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
492 for (unsigned i = 0; i < count; i++) {
493 struct pipe_shader_buffer *buf = &so->sb[i];
494 unsigned sz = buf->buffer_size;
495
496 /* width is in dwords, overflows into height: */
497 sz /= 4;
498
499 OUT_RING(ring, A6XX_SSBO_1_0_WIDTH(sz));
500 OUT_RING(ring, A6XX_SSBO_1_1_HEIGHT(sz >> 16));
501 }
502 #endif
503
504 OUT_PKT7(ring, opcode, 3 + (2 * count));
505 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
506 CP_LOAD_STATE6_0_STATE_TYPE(2) |
507 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
508 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
509 CP_LOAD_STATE6_0_NUM_UNIT(count));
510 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
511 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
512 for (unsigned i = 0; i < count; i++) {
513 struct pipe_shader_buffer *buf = &so->sb[i];
514 if (buf->buffer) {
515 struct fd_resource *rsc = fd_resource(buf->buffer);
516 OUT_RELOCW(ring, rsc->bo, buf->buffer_offset, 0, 0);
517 } else {
518 OUT_RING(ring, 0x00000000);
519 OUT_RING(ring, 0x00000000);
520 }
521 }
522 }
523
524 static struct fd_ringbuffer *
525 build_vbo_state(struct fd6_emit *emit, const struct ir3_shader_variant *vp)
526 {
527 const struct fd_vertex_state *vtx = emit->vtx;
528 int32_t i, j;
529
530 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
531 4 * (10 * vp->inputs_count + 2), FD_RINGBUFFER_STREAMING);
532
533 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
534 if (vp->inputs[i].sysval)
535 continue;
536 if (vp->inputs[i].compmask) {
537 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
538 const struct pipe_vertex_buffer *vb =
539 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
540 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
541 enum pipe_format pfmt = elem->src_format;
542 enum a6xx_vtx_fmt fmt = fd6_pipe2vtx(pfmt);
543 bool isint = util_format_is_pure_integer(pfmt);
544 uint32_t off = vb->buffer_offset + elem->src_offset;
545 uint32_t size = fd_bo_size(rsc->bo) - off;
546 debug_assert(fmt != ~0);
547
548 #ifdef DEBUG
549 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
550 */
551 if (off > fd_bo_size(rsc->bo))
552 continue;
553 #endif
554
555 OUT_PKT4(ring, REG_A6XX_VFD_FETCH(j), 4);
556 OUT_RELOC(ring, rsc->bo, off, 0, 0);
557 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
558 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
559
560 OUT_PKT4(ring, REG_A6XX_VFD_DECODE(j), 2);
561 OUT_RING(ring, A6XX_VFD_DECODE_INSTR_IDX(j) |
562 A6XX_VFD_DECODE_INSTR_FORMAT(fmt) |
563 COND(elem->instance_divisor, A6XX_VFD_DECODE_INSTR_INSTANCED) |
564 A6XX_VFD_DECODE_INSTR_SWAP(fd6_pipe2swap(pfmt)) |
565 A6XX_VFD_DECODE_INSTR_UNK30 |
566 COND(!isint, A6XX_VFD_DECODE_INSTR_FLOAT));
567 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
568
569 OUT_PKT4(ring, REG_A6XX_VFD_DEST_CNTL(j), 1);
570 OUT_RING(ring, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
571 A6XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
572
573 j++;
574 }
575 }
576
577 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_0, 1);
578 OUT_RING(ring, A6XX_VFD_CONTROL_0_VTXCNT(j) | (j << 8));
579
580 return ring;
581 }
582
583 static struct fd_ringbuffer *
584 build_lrz(struct fd6_emit *emit, bool binning_pass)
585 {
586 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(emit->ctx->zsa);
587 struct pipe_framebuffer_state *pfb = &emit->ctx->batch->framebuffer;
588 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
589 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
590 uint32_t rb_lrz_cntl = zsa->rb_lrz_cntl;
591
592 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
593 16, FD_RINGBUFFER_STREAMING);
594
595 if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid) {
596 gras_lrz_cntl = 0;
597 rb_lrz_cntl = 0;
598 } else if (binning_pass && zsa->lrz_write) {
599 gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_LRZ_WRITE;
600 }
601
602 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
603 OUT_RING(ring, gras_lrz_cntl);
604
605 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
606 OUT_RING(ring, rb_lrz_cntl);
607
608 return ring;
609 }
610
611 void
612 fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
613 {
614 struct fd_context *ctx = emit->ctx;
615 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
616 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
617 const struct ir3_shader_variant *vp = emit->vs;
618 const struct ir3_shader_variant *fp = emit->fs;
619 const enum fd_dirty_3d_state dirty = emit->dirty;
620 bool needs_border = false;
621
622 emit_marker6(ring, 5);
623
624 if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE)) {
625 struct fd_ringbuffer *state;
626
627 state = build_vbo_state(emit, emit->vs);
628 fd6_emit_add_group(emit, state, FD6_GROUP_VBO, 0x6);
629 fd_ringbuffer_del(state);
630
631 state = build_vbo_state(emit, emit->bs);
632 fd6_emit_add_group(emit, state, FD6_GROUP_VBO_BINNING, 0x1);
633 fd_ringbuffer_del(state);
634 }
635
636 if (dirty & FD_DIRTY_ZSA) {
637 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
638
639 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
640 fd6_emit_add_group(emit, zsa->stateobj_no_alpha, FD6_GROUP_ZSA, 0x7);
641 else
642 fd6_emit_add_group(emit, zsa->stateobj, FD6_GROUP_ZSA, 0x7);
643 }
644
645 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && pfb->zsbuf) {
646 struct fd_ringbuffer *state;
647
648 state = build_lrz(emit, false);
649 fd6_emit_add_group(emit, state, FD6_GROUP_LRZ, 0x6);
650 fd_ringbuffer_del(state);
651
652 state = build_lrz(emit, true);
653 fd6_emit_add_group(emit, state, FD6_GROUP_LRZ_BINNING, 0x1);
654 fd_ringbuffer_del(state);
655 }
656
657 if (dirty & FD_DIRTY_STENCIL_REF) {
658 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
659
660 OUT_PKT4(ring, REG_A6XX_RB_STENCILREF, 1);
661 OUT_RING(ring, A6XX_RB_STENCILREF_REF(sr->ref_value[0]) |
662 A6XX_RB_STENCILREF_BFREF(sr->ref_value[1]));
663 }
664
665 /* NOTE: scissor enabled bit is part of rasterizer state: */
666 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
667 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
668
669 OUT_PKT4(ring, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
670 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
671 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
672 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
673 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
674
675 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
676 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
677 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
678 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
679 }
680
681 if (dirty & FD_DIRTY_VIEWPORT) {
682 struct pipe_scissor_state *scissor = &ctx->viewport_scissor;
683
684 OUT_PKT4(ring, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
685 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
686 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
687 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
688 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
689 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
690 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
691
692 OUT_PKT4(ring, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
693 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
694 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
695 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
696 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
697
698 unsigned guardband_x = fd_calc_guardband(scissor->maxx - scissor->minx);
699 unsigned guardband_y = fd_calc_guardband(scissor->maxy - scissor->miny);
700
701 OUT_PKT4(ring, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
702 OUT_RING(ring, A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_x) |
703 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_y));
704 }
705
706 if (dirty & FD_DIRTY_PROG) {
707 fd6_emit_add_group(emit, prog->stateobj, FD6_GROUP_PROG, 0x6);
708 fd6_emit_add_group(emit, prog->binning_stateobj,
709 FD6_GROUP_PROG_BINNING, 0x1);
710
711 /* emit remaining non-stateobj program state, ie. what depends
712 * on other emit state, so cannot be pre-baked. This could
713 * be moved to a separate stateobj which is dynamically
714 * created.
715 */
716 fd6_program_emit(ring, emit);
717 }
718
719 if (dirty & FD_DIRTY_RASTERIZER) {
720 struct fd6_rasterizer_stateobj *rasterizer =
721 fd6_rasterizer_stateobj(ctx->rasterizer);
722 fd6_emit_add_group(emit, rasterizer->stateobj,
723 FD6_GROUP_RASTERIZER, 0x7);
724 }
725
726 /* Since the primitive restart state is not part of a tracked object, we
727 * re-emit this register every time.
728 */
729 if (emit->info && ctx->rasterizer) {
730 struct fd6_rasterizer_stateobj *rasterizer =
731 fd6_rasterizer_stateobj(ctx->rasterizer);
732 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9806, 1);
733 OUT_RING(ring, 0);
734 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9990, 1);
735 OUT_RING(ring, 0);
736 OUT_PKT4(ring, REG_A6XX_VFD_UNKNOWN_A008, 1);
737 OUT_RING(ring, 0);
738
739 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
740 OUT_RING(ring, rasterizer->pc_primitive_cntl |
741 COND(emit->info->primitive_restart && emit->info->index_size,
742 A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART));
743 }
744
745 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
746 unsigned nr = pfb->nr_cbufs;
747
748 if (ctx->rasterizer->rasterizer_discard)
749 nr = 0;
750
751 OUT_PKT4(ring, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
752 OUT_RING(ring, COND(fp->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z));
753 OUT_RING(ring, A6XX_RB_FS_OUTPUT_CNTL1_MRT(nr));
754
755 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL1, 1);
756 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL1_MRT(nr));
757 }
758
759 #define DIRTY_CONST (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST | \
760 FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)
761
762 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & DIRTY_CONST) {
763 struct fd_ringbuffer *vsconstobj = fd_submit_new_ringbuffer(
764 ctx->batch->submit, 0x1000, FD_RINGBUFFER_STREAMING);
765
766 OUT_WFI5(vsconstobj);
767 ir3_emit_vs_consts(vp, vsconstobj, ctx, emit->info);
768 fd6_emit_add_group(emit, vsconstobj, FD6_GROUP_VS_CONST, 0x7);
769 fd_ringbuffer_del(vsconstobj);
770 }
771
772 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & DIRTY_CONST) {
773 struct fd_ringbuffer *fsconstobj = fd_submit_new_ringbuffer(
774 ctx->batch->submit, 0x1000, FD_RINGBUFFER_STREAMING);
775
776 OUT_WFI5(fsconstobj);
777 ir3_emit_fs_consts(fp, fsconstobj, ctx);
778 fd6_emit_add_group(emit, fsconstobj, FD6_GROUP_FS_CONST, 0x6);
779 fd_ringbuffer_del(fsconstobj);
780 }
781
782 struct ir3_stream_output_info *info = &vp->shader->stream_output;
783 if (info->num_outputs) {
784 struct fd_streamout_stateobj *so = &ctx->streamout;
785
786 emit->streamout_mask = 0;
787
788 for (unsigned i = 0; i < so->num_targets; i++) {
789 struct pipe_stream_output_target *target = so->targets[i];
790
791 if (!target)
792 continue;
793
794 unsigned offset = (so->offsets[i] * info->stride[i] * 4) +
795 target->buffer_offset;
796
797 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(i), 3);
798 /* VPC_SO[i].BUFFER_BASE_LO: */
799 OUT_RELOCW(ring, fd_resource(target->buffer)->bo, 0, 0, 0);
800 OUT_RING(ring, target->buffer_size + offset);
801
802 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(i), 3);
803 OUT_RING(ring, offset);
804 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
805 // TODO just give hw a dummy addr for now.. we should
806 // be using this an then CP_MEM_TO_REG to set the
807 // VPC_SO[i].BUFFER_OFFSET for the next draw..
808 OUT_RELOCW(ring, fd6_context(ctx)->blit_mem, 0x100, 0, 0);
809
810 emit->streamout_mask |= (1 << i);
811 }
812
813 if (emit->streamout_mask) {
814 const struct fd6_streamout_state *tf = &prog->tf;
815
816 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * tf->prog_count));
817 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
818 OUT_RING(ring, tf->vpc_so_buf_cntl);
819 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0));
820 OUT_RING(ring, tf->ncomp[0]);
821 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1));
822 OUT_RING(ring, tf->ncomp[1]);
823 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(2));
824 OUT_RING(ring, tf->ncomp[2]);
825 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3));
826 OUT_RING(ring, tf->ncomp[3]);
827 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
828 OUT_RING(ring, A6XX_VPC_SO_CNTL_ENABLE);
829 for (unsigned i = 0; i < tf->prog_count; i++) {
830 OUT_RING(ring, REG_A6XX_VPC_SO_PROG);
831 OUT_RING(ring, tf->prog[i]);
832 }
833
834 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
835 OUT_RING(ring, 0x0);
836 } else {
837 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 4);
838 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
839 OUT_RING(ring, 0);
840 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
841 OUT_RING(ring, 0);
842
843 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
844 OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
845 }
846 }
847
848 if (dirty & FD_DIRTY_BLEND) {
849 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
850 uint32_t i;
851
852 for (i = 0; i < A6XX_MAX_RENDER_TARGETS; i++) {
853 enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
854 bool is_int = util_format_is_pure_integer(format);
855 bool has_alpha = util_format_has_alpha(format);
856 uint32_t control = blend->rb_mrt[i].control;
857 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
858
859 if (is_int) {
860 control &= A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
861 control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
862 }
863
864 if (has_alpha) {
865 blend_control |= blend->rb_mrt[i].blend_control_rgb;
866 } else {
867 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
868 control &= ~A6XX_RB_MRT_CONTROL_BLEND2;
869 }
870
871 OUT_PKT4(ring, REG_A6XX_RB_MRT_CONTROL(i), 1);
872 OUT_RING(ring, control);
873
874 OUT_PKT4(ring, REG_A6XX_RB_MRT_BLEND_CONTROL(i), 1);
875 OUT_RING(ring, blend_control);
876 }
877
878 OUT_PKT4(ring, REG_A6XX_SP_BLEND_CNTL, 1);
879 OUT_RING(ring, blend->sp_blend_cntl);
880 }
881
882 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK)) {
883 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
884
885 OUT_PKT4(ring, REG_A6XX_RB_BLEND_CNTL, 1);
886 OUT_RING(ring, blend->rb_blend_cntl |
887 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(ctx->sample_mask));
888 }
889
890 if (dirty & FD_DIRTY_BLEND_COLOR) {
891 struct pipe_blend_color *bcolor = &ctx->blend_color;
892
893 OUT_PKT4(ring, REG_A6XX_RB_BLEND_RED_F32, 4);
894 OUT_RING(ring, A6XX_RB_BLEND_RED_F32(bcolor->color[0]));
895 OUT_RING(ring, A6XX_RB_BLEND_GREEN_F32(bcolor->color[1]));
896 OUT_RING(ring, A6XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
897 OUT_RING(ring, A6XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
898 }
899
900 if ((ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX) &&
901 ctx->tex[PIPE_SHADER_VERTEX].num_textures > 0) {
902 struct fd6_texture_state *tex = fd6_texture_state(ctx,
903 SB6_VS_TEX, &ctx->tex[PIPE_SHADER_VERTEX]);
904
905 needs_border |= tex->needs_border;
906
907 fd6_emit_add_group(emit, tex->stateobj, FD6_GROUP_VS_TEX, 0x7);
908 }
909
910 if ((ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX) &&
911 ctx->tex[PIPE_SHADER_FRAGMENT].num_textures > 0) {
912 struct fd6_texture_state *tex = fd6_texture_state(ctx,
913 SB6_FS_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT]);
914
915 needs_border |= tex->needs_border;
916
917 fd6_emit_add_group(emit, tex->stateobj, FD6_GROUP_FS_TEX, 0x7);
918 }
919
920 if (needs_border)
921 emit_border_color(ctx, ring);
922
923 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_SSBO)
924 emit_ssbos(ctx, ring, SB6_SSBO, &ctx->shaderbuf[PIPE_SHADER_FRAGMENT]);
925
926 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_IMAGE)
927 fd6_emit_images(ctx, ring, PIPE_SHADER_FRAGMENT);
928
929 if (emit->num_groups > 0) {
930 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3 * emit->num_groups);
931 for (unsigned i = 0; i < emit->num_groups; i++) {
932 struct fd6_state_group *g = &emit->groups[i];
933 unsigned n = fd_ringbuffer_size(g->stateobj) / 4;
934
935 if (n == 0) {
936 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
937 CP_SET_DRAW_STATE__0_DISABLE |
938 CP_SET_DRAW_STATE__0_ENABLE_MASK(g->enable_mask) |
939 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
940 OUT_RING(ring, 0x00000000);
941 OUT_RING(ring, 0x00000000);
942 } else {
943 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(n) |
944 CP_SET_DRAW_STATE__0_ENABLE_MASK(g->enable_mask) |
945 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
946 OUT_RB(ring, g->stateobj);
947 }
948
949 fd_ringbuffer_del(g->stateobj);
950 }
951 emit->num_groups = 0;
952 }
953 }
954
955 void
956 fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
957 struct ir3_shader_variant *cp)
958 {
959 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
960
961 if (dirty & FD_DIRTY_SHADER_TEX) {
962 bool needs_border = false;
963 needs_border |= fd6_emit_textures(ctx->pipe, ring, SB6_CS_TEX,
964 &ctx->tex[PIPE_SHADER_COMPUTE], 0);
965
966 if (needs_border)
967 emit_border_color(ctx, ring);
968
969 #if 0
970 OUT_PKT4(ring, REG_A6XX_TPL1_VS_TEX_COUNT, 1);
971 OUT_RING(ring, 0);
972
973 OUT_PKT4(ring, REG_A6XX_TPL1_HS_TEX_COUNT, 1);
974 OUT_RING(ring, 0);
975
976 OUT_PKT4(ring, REG_A6XX_TPL1_DS_TEX_COUNT, 1);
977 OUT_RING(ring, 0);
978
979 OUT_PKT4(ring, REG_A6XX_TPL1_GS_TEX_COUNT, 1);
980 OUT_RING(ring, 0);
981
982 OUT_PKT4(ring, REG_A6XX_TPL1_FS_TEX_COUNT, 1);
983 OUT_RING(ring, 0);
984 #endif
985 }
986
987 #if 0
988 OUT_PKT4(ring, REG_A6XX_TPL1_CS_TEX_COUNT, 1);
989 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_COMPUTE].enabled_mask ?
990 ~0 : ctx->tex[PIPE_SHADER_COMPUTE].num_textures);
991 #endif
992
993 if (dirty & FD_DIRTY_SHADER_SSBO)
994 emit_ssbos(ctx, ring, SB6_CS_SSBO, &ctx->shaderbuf[PIPE_SHADER_COMPUTE]);
995
996 if (dirty & FD_DIRTY_SHADER_IMAGE)
997 fd6_emit_images(ctx, ring, PIPE_SHADER_COMPUTE);
998 }
999
1000
1001 /* emit setup at begin of new cmdstream buffer (don't rely on previous
1002 * state, there could have been a context switch between ioctls):
1003 */
1004 void
1005 fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
1006 {
1007 //struct fd_context *ctx = batch->ctx;
1008
1009 fd6_cache_flush(batch, ring);
1010
1011 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1012 OUT_RING(ring, 0xfffff);
1013
1014 /*
1015 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
1016 0000000500024048: 70d08003 00000000 001c5000 00000005
1017 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
1018 0000000500024058: 70d08003 00000010 001c7000 00000005
1019
1020 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
1021 0000000500024068: 70268000
1022 */
1023
1024 WRITE(REG_A6XX_RB_CCU_CNTL, 0x7c400004);
1025 WRITE(REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
1026 WRITE(REG_A6XX_SP_UNKNOWN_AE04, 0x8);
1027 WRITE(REG_A6XX_SP_UNKNOWN_AE00, 0);
1028 WRITE(REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
1029 WRITE(REG_A6XX_SP_UNKNOWN_B605, 0x44);
1030 WRITE(REG_A6XX_SP_UNKNOWN_B600, 0x100000);
1031 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
1032 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
1033
1034 WRITE(REG_A6XX_VPC_UNKNOWN_9600, 0);
1035 WRITE(REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
1036 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
1037 WRITE(REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
1038 WRITE(REG_A6XX_SP_UNKNOWN_AB20, 0);
1039 WRITE(REG_A6XX_SP_UNKNOWN_B182, 0);
1040 WRITE(REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
1041 WRITE(REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
1042 WRITE(REG_A6XX_UCHE_CLIENT_PF, 4);
1043 WRITE(REG_A6XX_RB_UNKNOWN_8E01, 0x0);
1044 WRITE(REG_A6XX_SP_UNKNOWN_AB00, 0x5);
1045 WRITE(REG_A6XX_VFD_UNKNOWN_A009, 0x00000001);
1046 WRITE(REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
1047 WRITE(REG_A6XX_PC_MODE_CNTL, 0x1f);
1048
1049 OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
1050 OUT_RING(ring, 0);
1051
1052 WRITE(REG_A6XX_GRAS_UNKNOWN_8101, 0);
1053 WRITE(REG_A6XX_GRAS_UNKNOWN_8109, 0);
1054 WRITE(REG_A6XX_GRAS_UNKNOWN_8110, 0);
1055
1056 WRITE(REG_A6XX_RB_RENDER_CONTROL0, 0x401);
1057 WRITE(REG_A6XX_RB_RENDER_CONTROL1, 0);
1058 WRITE(REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
1059 WRITE(REG_A6XX_RB_UNKNOWN_8810, 0);
1060 WRITE(REG_A6XX_RB_UNKNOWN_8818, 0);
1061 WRITE(REG_A6XX_RB_UNKNOWN_8819, 0);
1062 WRITE(REG_A6XX_RB_UNKNOWN_881A, 0);
1063 WRITE(REG_A6XX_RB_UNKNOWN_881B, 0);
1064 WRITE(REG_A6XX_RB_UNKNOWN_881C, 0);
1065 WRITE(REG_A6XX_RB_UNKNOWN_881D, 0);
1066 WRITE(REG_A6XX_RB_UNKNOWN_881E, 0);
1067 WRITE(REG_A6XX_RB_UNKNOWN_88F0, 0);
1068
1069 WRITE(REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
1070 WRITE(REG_A6XX_VPC_UNKNOWN_9107, 0);
1071
1072 WRITE(REG_A6XX_VPC_UNKNOWN_9236, 1);
1073 WRITE(REG_A6XX_VPC_UNKNOWN_9300, 0);
1074
1075 WRITE(REG_A6XX_VPC_SO_OVERRIDE, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
1076
1077 WRITE(REG_A6XX_PC_UNKNOWN_9801, 0);
1078 WRITE(REG_A6XX_PC_UNKNOWN_9806, 0);
1079 WRITE(REG_A6XX_PC_UNKNOWN_9980, 0);
1080
1081 WRITE(REG_A6XX_PC_UNKNOWN_9B06, 0);
1082 WRITE(REG_A6XX_PC_UNKNOWN_9B06, 0);
1083
1084 WRITE(REG_A6XX_SP_UNKNOWN_A81B, 0);
1085
1086 WRITE(REG_A6XX_SP_UNKNOWN_B183, 0);
1087
1088 WRITE(REG_A6XX_GRAS_UNKNOWN_8099, 0);
1089 WRITE(REG_A6XX_GRAS_UNKNOWN_809B, 0);
1090 WRITE(REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1091 WRITE(REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1092 WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
1093 WRITE(REG_A6XX_VPC_UNKNOWN_9211, 0);
1094 WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
1095 WRITE(REG_A6XX_PC_UNKNOWN_9981, 0x3);
1096 WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
1097 WRITE(REG_A6XX_VPC_UNKNOWN_9108, 0x3);
1098 WRITE(REG_A6XX_SP_TP_UNKNOWN_B304, 0);
1099 WRITE(REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
1100 WRITE(REG_A6XX_RB_UNKNOWN_8804, 0);
1101 WRITE(REG_A6XX_GRAS_UNKNOWN_80A4, 0);
1102 WRITE(REG_A6XX_GRAS_UNKNOWN_80A5, 0);
1103 WRITE(REG_A6XX_GRAS_UNKNOWN_80A6, 0);
1104 WRITE(REG_A6XX_RB_UNKNOWN_8805, 0);
1105 WRITE(REG_A6XX_RB_UNKNOWN_8806, 0);
1106 WRITE(REG_A6XX_RB_UNKNOWN_8878, 0);
1107 WRITE(REG_A6XX_RB_UNKNOWN_8879, 0);
1108 WRITE(REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1109
1110 emit_marker6(ring, 7);
1111
1112 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
1113 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
1114
1115 WRITE(REG_A6XX_VFD_UNKNOWN_A008, 0);
1116
1117 OUT_PKT4(ring, REG_A6XX_PC_MODE_CNTL, 1);
1118 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
1119
1120 /* we don't use this yet.. probably best to disable.. */
1121 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1122 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1123 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1124 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1125 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1126 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1127
1128 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
1129 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
1130 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
1131 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
1132
1133 OUT_PKT4(ring, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
1134 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
1135 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1136
1137 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1138 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
1139
1140 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
1141 OUT_RING(ring, 0x00000000); /* UNKNOWN_E2AB */
1142
1143 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1144 OUT_RING(ring, 0x00000000);
1145 OUT_RING(ring, 0x00000000);
1146 OUT_RING(ring, 0x00000000);
1147
1148 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
1149 OUT_RING(ring, 0x00000000);
1150 OUT_RING(ring, 0x00000000);
1151 OUT_RING(ring, 0x00000000);
1152 OUT_RING(ring, 0x00000000);
1153 OUT_RING(ring, 0x00000000);
1154 OUT_RING(ring, 0x00000000);
1155
1156 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
1157 OUT_RING(ring, 0x00000000);
1158 OUT_RING(ring, 0x00000000);
1159 OUT_RING(ring, 0x00000000);
1160 OUT_RING(ring, 0x00000000);
1161 OUT_RING(ring, 0x00000000);
1162 OUT_RING(ring, 0x00000000);
1163
1164 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
1165 OUT_RING(ring, 0x00000000);
1166 OUT_RING(ring, 0x00000000);
1167 OUT_RING(ring, 0x00000000);
1168
1169 OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1);
1170 OUT_RING(ring, 0x00000000);
1171
1172 OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
1173 OUT_RING(ring, 0x00000000);
1174
1175 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1176 OUT_RING(ring, 0x00000000);
1177
1178 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
1179 OUT_RING(ring, 0x00000000);
1180 }
1181
1182 static void
1183 fd6_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
1184 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
1185 unsigned sizedwords)
1186 {
1187 struct fd_bo *src_bo = fd_resource(src)->bo;
1188 struct fd_bo *dst_bo = fd_resource(dst)->bo;
1189 unsigned i;
1190
1191 for (i = 0; i < sizedwords; i++) {
1192 OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
1193 OUT_RING(ring, 0x00000000);
1194 OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
1195 OUT_RELOC (ring, src_bo, src_off, 0, 0);
1196
1197 dst_off += 4;
1198 src_off += 4;
1199 }
1200 }
1201
1202 void
1203 fd6_emit_init(struct pipe_context *pctx)
1204 {
1205 struct fd_context *ctx = fd_context(pctx);
1206 ctx->emit_const = fd6_emit_const;
1207 ctx->emit_const_bo = fd6_emit_const_bo;
1208 ctx->emit_ib = fd6_emit_ib;
1209 ctx->mem_to_mem = fd6_mem_to_mem;
1210 }