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freedreno/a6xx: remove special handling based on MRT format
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_helpers.h"
32 #include "util/format/u_format.h"
33 #include "util/u_viewport.h"
34
35 #include "freedreno_resource.h"
36 #include "freedreno_query_hw.h"
37
38 #include "fd6_emit.h"
39 #include "fd6_blend.h"
40 #include "fd6_context.h"
41 #include "fd6_image.h"
42 #include "fd6_program.h"
43 #include "fd6_rasterizer.h"
44 #include "fd6_texture.h"
45 #include "fd6_format.h"
46 #include "fd6_zsa.h"
47
48 /* regid: base const register
49 * prsc or dwords: buffer containing constant values
50 * sizedwords: size of const value buffer
51 */
52 static void
53 fd6_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
54 uint32_t regid, uint32_t offset, uint32_t sizedwords,
55 const uint32_t *dwords, struct pipe_resource *prsc)
56 {
57 uint32_t i, sz, align_sz;
58 enum a6xx_state_src src;
59
60 debug_assert((regid % 4) == 0);
61
62 if (prsc) {
63 sz = 0;
64 src = SS6_INDIRECT;
65 } else {
66 sz = sizedwords;
67 src = SS6_DIRECT;
68 }
69
70 align_sz = align(sz, 4);
71
72 OUT_PKT7(ring, fd6_stage2opcode(type), 3 + align_sz);
73 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
74 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
75 CP_LOAD_STATE6_0_STATE_SRC(src) |
76 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
77 CP_LOAD_STATE6_0_NUM_UNIT(DIV_ROUND_UP(sizedwords, 4)));
78 if (prsc) {
79 struct fd_bo *bo = fd_resource(prsc)->bo;
80 OUT_RELOC(ring, bo, offset, 0, 0);
81 } else {
82 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
83 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
84 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
85 }
86
87 for (i = 0; i < sz; i++) {
88 OUT_RING(ring, dwords[i]);
89 }
90
91 /* Zero-pad to multiple of 4 dwords */
92 for (i = sz; i < align_sz; i++) {
93 OUT_RING(ring, 0);
94 }
95 }
96
97 static void
98 fd6_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
99 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
100 {
101 uint32_t anum = align(num, 2);
102 uint32_t i;
103
104 debug_assert((regid % 4) == 0);
105
106 OUT_PKT7(ring, fd6_stage2opcode(type), 3 + (2 * anum));
107 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
108 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS)|
109 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
110 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
111 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
112 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
113 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
114
115 for (i = 0; i < num; i++) {
116 if (prscs[i]) {
117 if (write) {
118 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
119 } else {
120 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
121 }
122 } else {
123 OUT_RING(ring, 0xbad00000 | (i << 16));
124 OUT_RING(ring, 0xbad00000 | (i << 16));
125 }
126 }
127
128 for (; i < anum; i++) {
129 OUT_RING(ring, 0xffffffff);
130 OUT_RING(ring, 0xffffffff);
131 }
132 }
133
134 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
135 * the same as a6xx then move this somewhere common ;-)
136 *
137 * Entry layout looks like (total size, 0x60 bytes):
138 */
139
140 struct PACKED bcolor_entry {
141 uint32_t fp32[4];
142 uint16_t ui16[4];
143 int16_t si16[4];
144 uint16_t fp16[4];
145 uint16_t rgb565;
146 uint16_t rgb5a1;
147 uint16_t rgba4;
148 uint8_t __pad0[2];
149 uint8_t ui8[4];
150 int8_t si8[4];
151 uint32_t rgb10a2;
152 uint32_t z24; /* also s8? */
153 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
154 uint8_t __pad1[56];
155 };
156
157 #define FD6_BORDER_COLOR_SIZE sizeof(struct bcolor_entry)
158 #define FD6_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD6_BORDER_COLOR_SIZE)
159
160 static void
161 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
162 {
163 unsigned i, j;
164 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
165
166 for (i = 0; i < tex->num_samplers; i++) {
167 struct bcolor_entry *e = &entries[i];
168 struct pipe_sampler_state *sampler = tex->samplers[i];
169 union pipe_color_union *bc;
170
171 if (!sampler)
172 continue;
173
174 bc = &sampler->border_color;
175
176 /*
177 * XXX HACK ALERT XXX
178 *
179 * The border colors need to be swizzled in a particular
180 * format-dependent order. Even though samplers don't know about
181 * formats, we can assume that with a GL state tracker, there's a
182 * 1:1 correspondence between sampler and texture. Take advantage
183 * of that knowledge.
184 */
185 if ((i >= tex->num_textures) || !tex->textures[i])
186 continue;
187
188 struct pipe_sampler_view *view = tex->textures[i];
189 enum pipe_format format = view->format;
190 const struct util_format_description *desc =
191 util_format_description(format);
192
193 e->rgb565 = 0;
194 e->rgb5a1 = 0;
195 e->rgba4 = 0;
196 e->rgb10a2 = 0;
197 e->z24 = 0;
198
199 unsigned char swiz[4];
200
201 fd6_tex_swiz(format, swiz,
202 view->swizzle_r, view->swizzle_g,
203 view->swizzle_b, view->swizzle_a);
204
205 for (j = 0; j < 4; j++) {
206 int c = swiz[j];
207 int cd = c;
208
209 /*
210 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the
211 * stencil border color value in bc->ui[0] but according
212 * to desc->swizzle and desc->channel, the .x/.w component
213 * is NONE and the stencil value is in the y component.
214 * Meanwhile the hardware wants this in the .w component
215 * for x24s8 and the .x component for x32_s8x24.
216 */
217 if ((format == PIPE_FORMAT_X24S8_UINT) ||
218 (format == PIPE_FORMAT_X32_S8X24_UINT)) {
219 if (j == 0) {
220 c = 1;
221 cd = (format == PIPE_FORMAT_X32_S8X24_UINT) ? 0 : 3;
222 } else {
223 continue;
224 }
225 }
226
227 if (c >= 4)
228 continue;
229
230 if (desc->channel[c].pure_integer) {
231 uint16_t clamped;
232 switch (desc->channel[c].size) {
233 case 2:
234 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
235 clamped = CLAMP(bc->ui[j], 0, 0x3);
236 break;
237 case 8:
238 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
239 clamped = CLAMP(bc->i[j], -128, 127);
240 else
241 clamped = CLAMP(bc->ui[j], 0, 255);
242 break;
243 case 10:
244 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
245 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
246 break;
247 case 16:
248 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
249 clamped = CLAMP(bc->i[j], -32768, 32767);
250 else
251 clamped = CLAMP(bc->ui[j], 0, 65535);
252 break;
253 default:
254 assert(!"Unexpected bit size");
255 case 32:
256 clamped = 0;
257 break;
258 }
259 e->fp32[cd] = bc->ui[j];
260 e->fp16[cd] = clamped;
261 } else {
262 float f = bc->f[j];
263 float f_u = CLAMP(f, 0, 1);
264 float f_s = CLAMP(f, -1, 1);
265
266 e->fp32[c] = fui(f);
267 e->fp16[c] = util_float_to_half(f);
268 e->srgb[c] = util_float_to_half(f_u);
269 e->ui16[c] = f_u * 0xffff;
270 e->si16[c] = f_s * 0x7fff;
271 e->ui8[c] = f_u * 0xff;
272 e->si8[c] = f_s * 0x7f;
273 if (c == 1)
274 e->rgb565 |= (int)(f_u * 0x3f) << 5;
275 else if (c < 3)
276 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
277 if (c == 3)
278 e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
279 else
280 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
281 if (c == 3)
282 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
283 else
284 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
285 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
286 if (c == 0)
287 e->z24 = f_u * 0xffffff;
288 }
289 }
290
291 #ifdef DEBUG
292 memset(&e->__pad0, 0, sizeof(e->__pad0));
293 memset(&e->__pad1, 0, sizeof(e->__pad1));
294 #endif
295 }
296 }
297
298 static void
299 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
300 {
301 struct fd6_context *fd6_ctx = fd6_context(ctx);
302 struct bcolor_entry *entries;
303 unsigned off;
304 void *ptr;
305
306 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
307
308 u_upload_alloc(fd6_ctx->border_color_uploader,
309 0, FD6_BORDER_COLOR_UPLOAD_SIZE,
310 FD6_BORDER_COLOR_UPLOAD_SIZE, &off,
311 &fd6_ctx->border_color_buf,
312 &ptr);
313
314 entries = ptr;
315
316 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
317 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
318 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
319
320 OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
321 OUT_RELOC(ring, fd_resource(fd6_ctx->border_color_buf)->bo, off, 0, 0);
322
323 u_upload_unmap(fd6_ctx->border_color_uploader);
324 }
325
326 static void
327 fd6_emit_fb_tex(struct fd_ringbuffer *state, struct fd_context *ctx)
328 {
329 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
330 struct pipe_surface *psurf = pfb->cbufs[0];
331 struct fd_resource *rsc = fd_resource(psurf->texture);
332
333 uint32_t texconst0 = fd6_tex_const_0(psurf->texture, psurf->u.tex.level,
334 psurf->format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
335 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W);
336
337 /* always TILE6_2 mode in GMEM.. which also means no swap: */
338 texconst0 &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
339 texconst0 |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
340
341 OUT_RING(state, texconst0);
342 OUT_RING(state, A6XX_TEX_CONST_1_WIDTH(pfb->width) |
343 A6XX_TEX_CONST_1_HEIGHT(pfb->height));
344 OUT_RINGP(state, A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
345 A6XX_TEX_CONST_2_FETCHSIZE(TFETCH6_2_BYTE),
346 &ctx->batch->fb_read_patches);
347 OUT_RING(state, A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size));
348
349 OUT_RING(state, A6XX_TEX_CONST_4_BASE_LO(ctx->screen->gmem_base));
350 OUT_RING(state, A6XX_TEX_CONST_5_BASE_HI(ctx->screen->gmem_base >> 32) |
351 A6XX_TEX_CONST_5_DEPTH(1));
352 OUT_RING(state, 0); /* texconst6 */
353 OUT_RING(state, 0); /* texconst7 */
354 OUT_RING(state, 0); /* texconst8 */
355 OUT_RING(state, 0); /* texconst9 */
356 OUT_RING(state, 0); /* texconst10 */
357 OUT_RING(state, 0); /* texconst11 */
358 OUT_RING(state, 0);
359 OUT_RING(state, 0);
360 OUT_RING(state, 0);
361 OUT_RING(state, 0);
362 }
363
364 bool
365 fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
366 enum pipe_shader_type type, struct fd_texture_stateobj *tex,
367 unsigned bcolor_offset,
368 /* can be NULL if no image/SSBO/fb state to merge in: */
369 const struct ir3_shader_variant *v, struct fd_context *ctx)
370 {
371 bool needs_border = false;
372 unsigned opcode, tex_samp_reg, tex_const_reg, tex_count_reg;
373 enum a6xx_state_block sb;
374
375 switch (type) {
376 case PIPE_SHADER_VERTEX:
377 sb = SB6_VS_TEX;
378 opcode = CP_LOAD_STATE6_GEOM;
379 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
380 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
381 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
382 break;
383 case PIPE_SHADER_TESS_CTRL:
384 sb = SB6_HS_TEX;
385 opcode = CP_LOAD_STATE6_GEOM;
386 tex_samp_reg = REG_A6XX_SP_HS_TEX_SAMP_LO;
387 tex_const_reg = REG_A6XX_SP_HS_TEX_CONST_LO;
388 tex_count_reg = REG_A6XX_SP_HS_TEX_COUNT;
389 break;
390 case PIPE_SHADER_TESS_EVAL:
391 sb = SB6_DS_TEX;
392 opcode = CP_LOAD_STATE6_GEOM;
393 tex_samp_reg = REG_A6XX_SP_DS_TEX_SAMP_LO;
394 tex_const_reg = REG_A6XX_SP_DS_TEX_CONST_LO;
395 tex_count_reg = REG_A6XX_SP_DS_TEX_COUNT;
396 break;
397 case PIPE_SHADER_GEOMETRY:
398 sb = SB6_GS_TEX;
399 opcode = CP_LOAD_STATE6_GEOM;
400 tex_samp_reg = REG_A6XX_SP_GS_TEX_SAMP_LO;
401 tex_const_reg = REG_A6XX_SP_GS_TEX_CONST_LO;
402 tex_count_reg = REG_A6XX_SP_GS_TEX_COUNT;
403 break;
404 case PIPE_SHADER_FRAGMENT:
405 sb = SB6_FS_TEX;
406 opcode = CP_LOAD_STATE6_FRAG;
407 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
408 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
409 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
410 break;
411 case PIPE_SHADER_COMPUTE:
412 sb = SB6_CS_TEX;
413 opcode = CP_LOAD_STATE6_FRAG;
414 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
415 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
416 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
417 break;
418 default:
419 unreachable("bad state block");
420 }
421
422 if (tex->num_samplers > 0) {
423 struct fd_ringbuffer *state =
424 fd_ringbuffer_new_object(pipe, tex->num_samplers * 4 * 4);
425 for (unsigned i = 0; i < tex->num_samplers; i++) {
426 static const struct fd6_sampler_stateobj dummy_sampler = {};
427 const struct fd6_sampler_stateobj *sampler = tex->samplers[i] ?
428 fd6_sampler_stateobj(tex->samplers[i]) : &dummy_sampler;
429 OUT_RING(state, sampler->texsamp0);
430 OUT_RING(state, sampler->texsamp1);
431 OUT_RING(state, sampler->texsamp2 |
432 A6XX_TEX_SAMP_2_BCOLOR_OFFSET((i + bcolor_offset) * sizeof(struct bcolor_entry)));
433 OUT_RING(state, sampler->texsamp3);
434 needs_border |= sampler->needs_border;
435 }
436
437 /* output sampler state: */
438 OUT_PKT7(ring, opcode, 3);
439 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
440 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
441 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
442 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
443 CP_LOAD_STATE6_0_NUM_UNIT(tex->num_samplers));
444 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
445
446 OUT_PKT4(ring, tex_samp_reg, 2);
447 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
448
449 fd_ringbuffer_del(state);
450 }
451
452 unsigned num_merged_textures = tex->num_textures;
453 unsigned num_textures = tex->num_textures;
454 if (v) {
455 num_merged_textures += v->image_mapping.num_tex;
456
457 if (v->fb_read)
458 num_merged_textures++;
459
460 /* There could be more bound textures than what the shader uses.
461 * Which isn't known at shader compile time. So in the case we
462 * are merging tex state, only emit the textures that the shader
463 * uses (since the image/SSBO related tex state comes immediately
464 * after)
465 */
466 num_textures = v->image_mapping.tex_base;
467 }
468
469 if (num_merged_textures > 0) {
470 struct fd_ringbuffer *state =
471 fd_ringbuffer_new_object(pipe, num_merged_textures * 16 * 4);
472 for (unsigned i = 0; i < num_textures; i++) {
473 static const struct fd6_pipe_sampler_view dummy_view = {};
474 const struct fd6_pipe_sampler_view *view = tex->textures[i] ?
475 fd6_pipe_sampler_view(tex->textures[i]) : &dummy_view;
476 struct fd_resource *rsc = NULL;
477
478 if (view->base.texture)
479 rsc = fd_resource(view->base.texture);
480
481 OUT_RING(state, view->texconst0);
482 OUT_RING(state, view->texconst1);
483 OUT_RING(state, view->texconst2);
484 OUT_RING(state, view->texconst3);
485
486 if (rsc) {
487 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
488 rsc = rsc->stencil;
489 OUT_RELOC(state, rsc->bo, view->offset,
490 (uint64_t)view->texconst5 << 32, 0);
491 } else {
492 OUT_RING(state, 0x00000000);
493 OUT_RING(state, view->texconst5);
494 }
495
496 OUT_RING(state, view->texconst6);
497
498 if (rsc && view->ubwc_enabled) {
499 OUT_RELOC(state, rsc->bo, view->ubwc_offset, 0, 0);
500 } else {
501 OUT_RING(state, 0);
502 OUT_RING(state, 0);
503 }
504
505 OUT_RING(state, view->texconst9);
506 OUT_RING(state, view->texconst10);
507 OUT_RING(state, view->texconst11);
508 OUT_RING(state, 0);
509 OUT_RING(state, 0);
510 OUT_RING(state, 0);
511 OUT_RING(state, 0);
512 }
513
514 if (v) {
515 const struct ir3_ibo_mapping *mapping = &v->image_mapping;
516 struct fd_shaderbuf_stateobj *buf = &ctx->shaderbuf[type];
517 struct fd_shaderimg_stateobj *img = &ctx->shaderimg[type];
518
519 for (unsigned i = 0; i < mapping->num_tex; i++) {
520 unsigned idx = mapping->tex_to_image[i];
521 if (idx & IBO_SSBO) {
522 fd6_emit_ssbo_tex(state, &buf->sb[idx & ~IBO_SSBO]);
523 } else {
524 fd6_emit_image_tex(state, &img->si[idx]);
525 }
526 }
527
528 if (v->fb_read) {
529 fd6_emit_fb_tex(state, ctx);
530 }
531 }
532
533 /* emit texture state: */
534 OUT_PKT7(ring, opcode, 3);
535 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
536 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
537 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
538 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
539 CP_LOAD_STATE6_0_NUM_UNIT(num_merged_textures));
540 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
541
542 OUT_PKT4(ring, tex_const_reg, 2);
543 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
544
545 fd_ringbuffer_del(state);
546 }
547
548 OUT_PKT4(ring, tex_count_reg, 1);
549 OUT_RING(ring, num_merged_textures);
550
551 return needs_border;
552 }
553
554 /* Emits combined texture state, which also includes any Image/SSBO
555 * related texture state merged in (because we must have all texture
556 * state for a given stage in a single buffer). In the fast-path, if
557 * we don't need to merge in any image/ssbo related texture state, we
558 * just use cached texture stateobj. Otherwise we generate a single-
559 * use stateobj.
560 *
561 * TODO Is there some sane way we can still use cached texture stateobj
562 * with image/ssbo in use?
563 *
564 * returns whether border_color is required:
565 */
566 static bool
567 fd6_emit_combined_textures(struct fd_ringbuffer *ring, struct fd6_emit *emit,
568 enum pipe_shader_type type, const struct ir3_shader_variant *v)
569 {
570 struct fd_context *ctx = emit->ctx;
571 bool needs_border = false;
572
573 static const struct {
574 enum fd6_state_id state_id;
575 unsigned enable_mask;
576 } s[PIPE_SHADER_TYPES] = {
577 [PIPE_SHADER_VERTEX] = { FD6_GROUP_VS_TEX, ENABLE_ALL },
578 [PIPE_SHADER_TESS_CTRL] = { FD6_GROUP_HS_TEX, ENABLE_ALL },
579 [PIPE_SHADER_TESS_EVAL] = { FD6_GROUP_DS_TEX, ENABLE_ALL },
580 [PIPE_SHADER_GEOMETRY] = { FD6_GROUP_GS_TEX, ENABLE_ALL },
581 [PIPE_SHADER_FRAGMENT] = { FD6_GROUP_FS_TEX, ENABLE_DRAW },
582 };
583
584 debug_assert(s[type].state_id);
585
586 if (!v->image_mapping.num_tex && !v->fb_read) {
587 /* in the fast-path, when we don't have to mix in any image/SSBO
588 * related texture state, we can just lookup the stateobj and
589 * re-emit that:
590 *
591 * Also, framebuffer-read is a slow-path because an extra
592 * texture needs to be inserted.
593 *
594 * TODO we can probably simmplify things if we also treated
595 * border_color as a slow-path.. this way the tex state key
596 * wouldn't depend on bcolor_offset.. but fb_read might rather
597 * be *somehow* a fast-path if we eventually used it for PLS.
598 * I suppose there would be no harm in just *always* inserting
599 * an fb_read texture?
600 */
601 if ((ctx->dirty_shader[type] & FD_DIRTY_SHADER_TEX) &&
602 ctx->tex[type].num_textures > 0) {
603 struct fd6_texture_state *tex = fd6_texture_state(ctx,
604 type, &ctx->tex[type]);
605
606 needs_border |= tex->needs_border;
607
608 fd6_emit_add_group(emit, tex->stateobj, s[type].state_id,
609 s[type].enable_mask);
610 }
611 } else {
612 /* In the slow-path, create a one-shot texture state object
613 * if either TEX|PROG|SSBO|IMAGE state is dirty:
614 */
615 if ((ctx->dirty_shader[type] &
616 (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
617 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) ||
618 v->fb_read) {
619 struct fd_texture_stateobj *tex = &ctx->tex[type];
620 struct fd_ringbuffer *stateobj =
621 fd_submit_new_ringbuffer(ctx->batch->submit,
622 0x1000, FD_RINGBUFFER_STREAMING);
623 unsigned bcolor_offset =
624 fd6_border_color_offset(ctx, type, tex);
625
626 needs_border |= fd6_emit_textures(ctx->pipe, stateobj, type, tex,
627 bcolor_offset, v, ctx);
628
629 fd6_emit_take_group(emit, stateobj, s[type].state_id,
630 s[type].enable_mask);
631 }
632 }
633
634 return needs_border;
635 }
636
637 static struct fd_ringbuffer *
638 build_vbo_state(struct fd6_emit *emit, const struct ir3_shader_variant *vp)
639 {
640 const struct fd_vertex_state *vtx = emit->vtx;
641 int32_t i, j;
642
643 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
644 4 * (10 * vp->inputs_count + 2), FD_RINGBUFFER_STREAMING);
645
646 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
647 if (vp->inputs[i].sysval)
648 continue;
649 if (vp->inputs[i].compmask) {
650 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
651 const struct pipe_vertex_buffer *vb =
652 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
653 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
654 enum pipe_format pfmt = elem->src_format;
655 enum a6xx_vtx_fmt fmt = fd6_pipe2vtx(pfmt);
656 bool isint = util_format_is_pure_integer(pfmt);
657 uint32_t off = vb->buffer_offset + elem->src_offset;
658 uint32_t size = fd_bo_size(rsc->bo) - off;
659 debug_assert(fmt != ~0);
660
661 #ifdef DEBUG
662 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
663 */
664 if (off > fd_bo_size(rsc->bo))
665 continue;
666 #endif
667
668 OUT_PKT4(ring, REG_A6XX_VFD_FETCH(j), 4);
669 OUT_RELOC(ring, rsc->bo, off, 0, 0);
670 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
671 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
672
673 OUT_PKT4(ring, REG_A6XX_VFD_DECODE(j), 2);
674 OUT_RING(ring, A6XX_VFD_DECODE_INSTR_IDX(j) |
675 A6XX_VFD_DECODE_INSTR_FORMAT(fmt) |
676 COND(elem->instance_divisor, A6XX_VFD_DECODE_INSTR_INSTANCED) |
677 A6XX_VFD_DECODE_INSTR_SWAP(fd6_pipe2swap(pfmt)) |
678 A6XX_VFD_DECODE_INSTR_UNK30 |
679 COND(!isint, A6XX_VFD_DECODE_INSTR_FLOAT));
680 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
681
682 OUT_PKT4(ring, REG_A6XX_VFD_DEST_CNTL(j), 1);
683 OUT_RING(ring, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
684 A6XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
685
686 j++;
687 }
688 }
689
690 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_0, 1);
691 OUT_RING(ring, A6XX_VFD_CONTROL_0_VTXCNT(j) | (j << 8));
692
693 return ring;
694 }
695
696 static struct fd_ringbuffer *
697 build_lrz(struct fd6_emit *emit, bool binning_pass)
698 {
699 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(emit->ctx->blend);
700 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(emit->ctx->zsa);
701 struct pipe_framebuffer_state *pfb = &emit->ctx->batch->framebuffer;
702 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
703 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
704 uint32_t rb_lrz_cntl = zsa->rb_lrz_cntl;
705
706 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
707 16, FD_RINGBUFFER_STREAMING);
708
709 if (zsa->invalidate_lrz) {
710 rsc->lrz_valid = false;
711 gras_lrz_cntl = 0;
712 rb_lrz_cntl = 0;
713 } else if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid) {
714 gras_lrz_cntl = 0;
715 rb_lrz_cntl = 0;
716 } else if (binning_pass && blend->lrz_write && zsa->lrz_write) {
717 gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_LRZ_WRITE;
718 }
719
720 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
721 OUT_RING(ring, gras_lrz_cntl);
722
723 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
724 OUT_RING(ring, rb_lrz_cntl);
725
726 return ring;
727 }
728
729 static void
730 fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3_stream_output_info *info)
731 {
732 struct fd_context *ctx = emit->ctx;
733 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
734 struct fd_streamout_stateobj *so = &ctx->streamout;
735
736 emit->streamout_mask = 0;
737
738 for (unsigned i = 0; i < so->num_targets; i++) {
739 struct pipe_stream_output_target *target = so->targets[i];
740
741 if (!target)
742 continue;
743
744 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(i), 3);
745 /* VPC_SO[i].BUFFER_BASE_LO: */
746 OUT_RELOCW(ring, fd_resource(target->buffer)->bo, target->buffer_offset, 0, 0);
747 OUT_RING(ring, target->buffer_size - target->buffer_offset);
748
749 if (so->reset & (1 << i)) {
750 unsigned offset = (so->offsets[i] * info->stride[i] * 4);
751 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(i), 1);
752 OUT_RING(ring, offset);
753 } else {
754 OUT_PKT7(ring, CP_MEM_TO_REG, 3);
755 OUT_RING(ring, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i)) |
756 CP_MEM_TO_REG_0_SHIFT_BY_2 | CP_MEM_TO_REG_0_UNK31 |
757 CP_MEM_TO_REG_0_CNT(0));
758 OUT_RELOC(ring, control_ptr(fd6_context(ctx), flush_base[i].offset));
759 }
760
761 OUT_PKT4(ring, REG_A6XX_VPC_SO_FLUSH_BASE_LO(i), 2);
762 OUT_RELOCW(ring, control_ptr(fd6_context(ctx), flush_base[i]));
763
764 so->reset &= ~(1 << i);
765
766 emit->streamout_mask |= (1 << i);
767 }
768
769 if (emit->streamout_mask) {
770 const struct fd6_streamout_state *tf = &prog->tf;
771
772 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * tf->prog_count));
773 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
774 OUT_RING(ring, tf->vpc_so_buf_cntl);
775 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0));
776 OUT_RING(ring, tf->ncomp[0]);
777 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1));
778 OUT_RING(ring, tf->ncomp[1]);
779 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(2));
780 OUT_RING(ring, tf->ncomp[2]);
781 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3));
782 OUT_RING(ring, tf->ncomp[3]);
783 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
784 OUT_RING(ring, A6XX_VPC_SO_CNTL_ENABLE);
785 for (unsigned i = 0; i < tf->prog_count; i++) {
786 OUT_RING(ring, REG_A6XX_VPC_SO_PROG);
787 OUT_RING(ring, tf->prog[i]);
788 }
789 } else {
790 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 4);
791 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
792 OUT_RING(ring, 0);
793 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
794 OUT_RING(ring, 0);
795 }
796 }
797
798 static void
799 emit_tess_bos(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3_shader_variant *s)
800 {
801 struct fd_context *ctx = emit->ctx;
802 const unsigned regid = s->shader->const_state.offsets.primitive_param * 4 + 4;
803 uint32_t dwords = 16;
804
805 OUT_PKT7(ring, fd6_stage2opcode(s->type), 3);
806 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid / 4) |
807 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS)|
808 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
809 CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(s->type)) |
810 CP_LOAD_STATE6_0_NUM_UNIT(dwords / 4));
811 OUT_RB(ring, ctx->batch->tess_addrs_constobj);
812 }
813
814 static void
815 emit_stage_tess_consts(struct fd_ringbuffer *ring, struct ir3_shader_variant *v,
816 uint32_t *params, int num_params)
817 {
818 const unsigned regid = v->shader->const_state.offsets.primitive_param;
819 int size = MIN2(1 + regid, v->constlen) - regid;
820 if (size > 0)
821 fd6_emit_const(ring, v->type, regid * 4, 0, num_params, params, NULL);
822 }
823
824 static void
825 fd6_emit_tess_const(struct fd6_emit *emit)
826 {
827 struct fd_context *ctx = emit->ctx;
828
829 struct fd_ringbuffer *constobj = fd_submit_new_ringbuffer(
830 ctx->batch->submit, 0x1000, FD_RINGBUFFER_STREAMING);
831
832 /* VS sizes are in bytes since that's what STLW/LDLW use, while the HS
833 * size is dwords, since that's what LDG/STG use.
834 */
835 unsigned num_vertices =
836 emit->hs ?
837 emit->info->vertices_per_patch :
838 emit->gs->shader->nir->info.gs.vertices_in;
839
840 uint32_t vs_params[4] = {
841 emit->vs->shader->output_size * num_vertices * 4, /* vs primitive stride */
842 emit->vs->shader->output_size * 4, /* vs vertex stride */
843 0,
844 0
845 };
846
847 emit_stage_tess_consts(constobj, emit->vs, vs_params, ARRAY_SIZE(vs_params));
848
849 if (emit->hs) {
850 uint32_t hs_params[4] = {
851 emit->vs->shader->output_size * num_vertices * 4, /* vs primitive stride */
852 emit->vs->shader->output_size * 4, /* vs vertex stride */
853 emit->hs->shader->output_size,
854 emit->info->vertices_per_patch
855 };
856
857 emit_stage_tess_consts(constobj, emit->hs, hs_params, ARRAY_SIZE(hs_params));
858 emit_tess_bos(constobj, emit, emit->hs);
859
860 if (emit->gs)
861 num_vertices = emit->gs->shader->nir->info.gs.vertices_in;
862
863 uint32_t ds_params[4] = {
864 emit->ds->shader->output_size * num_vertices * 4, /* ds primitive stride */
865 emit->ds->shader->output_size * 4, /* ds vertex stride */
866 emit->hs->shader->output_size, /* hs vertex stride (dwords) */
867 emit->hs->shader->nir->info.tess.tcs_vertices_out
868 };
869
870 emit_stage_tess_consts(constobj, emit->ds, ds_params, ARRAY_SIZE(ds_params));
871 emit_tess_bos(constobj, emit, emit->ds);
872 }
873
874 if (emit->gs) {
875 struct ir3_shader_variant *prev;
876 if (emit->ds)
877 prev = emit->ds;
878 else
879 prev = emit->vs;
880
881 uint32_t gs_params[4] = {
882 prev->shader->output_size * num_vertices * 4, /* ds primitive stride */
883 prev->shader->output_size * 4, /* ds vertex stride */
884 0,
885 0,
886 };
887
888 num_vertices = emit->gs->shader->nir->info.gs.vertices_in;
889 emit_stage_tess_consts(constobj, emit->gs, gs_params, ARRAY_SIZE(gs_params));
890 }
891
892 fd6_emit_take_group(emit, constobj, FD6_GROUP_PRIMITIVE_PARAMS, ENABLE_ALL);
893 }
894
895 static void
896 fd6_emit_consts(struct fd6_emit *emit, const struct ir3_shader_variant *v,
897 enum pipe_shader_type type, enum fd6_state_id id, unsigned enable_mask)
898 {
899 struct fd_context *ctx = emit->ctx;
900
901 if (v && ctx->dirty_shader[type] & (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST)) {
902 struct fd_ringbuffer *constobj = fd_submit_new_ringbuffer(
903 ctx->batch->submit, v->shader->ubo_state.cmdstream_size,
904 FD_RINGBUFFER_STREAMING);
905
906 ir3_emit_user_consts(ctx->screen, v, constobj, &ctx->constbuf[type]);
907 ir3_emit_ubos(ctx->screen, v, constobj, &ctx->constbuf[type]);
908 fd6_emit_take_group(emit, constobj, id, enable_mask);
909 }
910 }
911
912 void
913 fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
914 {
915 struct fd_context *ctx = emit->ctx;
916 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
917 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
918 const struct ir3_shader_variant *vs = emit->vs;
919 const struct ir3_shader_variant *hs = emit->hs;
920 const struct ir3_shader_variant *ds = emit->ds;
921 const struct ir3_shader_variant *gs = emit->gs;
922 const struct ir3_shader_variant *fs = emit->fs;
923 const enum fd_dirty_3d_state dirty = emit->dirty;
924 bool needs_border = false;
925
926 emit_marker6(ring, 5);
927
928 /* NOTE: we track fb_read differently than _BLEND_ENABLED since
929 * we might at some point decide to do sysmem in some cases when
930 * blend is enabled:
931 */
932 if (fs->fb_read)
933 ctx->batch->gmem_reason |= FD_GMEM_FB_READ;
934
935 if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE)) {
936 struct fd_ringbuffer *state;
937
938 state = build_vbo_state(emit, emit->vs);
939 fd6_emit_take_group(emit, state, FD6_GROUP_VBO, ENABLE_ALL);
940 }
941
942 if (dirty & FD_DIRTY_ZSA) {
943 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
944
945 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
946 fd6_emit_add_group(emit, zsa->stateobj_no_alpha, FD6_GROUP_ZSA, ENABLE_ALL);
947 else
948 fd6_emit_add_group(emit, zsa->stateobj, FD6_GROUP_ZSA, ENABLE_ALL);
949 }
950
951 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG)) && pfb->zsbuf) {
952 struct fd_ringbuffer *state;
953
954 state = build_lrz(emit, false);
955 fd6_emit_take_group(emit, state, FD6_GROUP_LRZ, ENABLE_DRAW);
956
957 state = build_lrz(emit, true);
958 fd6_emit_take_group(emit, state,
959 FD6_GROUP_LRZ_BINNING, CP_SET_DRAW_STATE__0_BINNING);
960 }
961
962 if (dirty & FD_DIRTY_STENCIL_REF) {
963 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
964
965 OUT_PKT4(ring, REG_A6XX_RB_STENCILREF, 1);
966 OUT_RING(ring, A6XX_RB_STENCILREF_REF(sr->ref_value[0]) |
967 A6XX_RB_STENCILREF_BFREF(sr->ref_value[1]));
968 }
969
970 /* NOTE: scissor enabled bit is part of rasterizer state: */
971 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
972 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
973
974 OUT_PKT4(ring, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
975 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
976 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
977 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
978 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
979
980 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
981 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
982 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
983 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
984 }
985
986 if (dirty & FD_DIRTY_VIEWPORT) {
987 struct pipe_scissor_state *scissor = &ctx->viewport_scissor;
988
989 OUT_PKT4(ring, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
990 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
991 OUT_RING(ring, A6XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
992 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
993 OUT_RING(ring, A6XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
994 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
995 OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
996
997 OUT_PKT4(ring, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
998 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
999 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
1000 OUT_RING(ring, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
1001 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
1002
1003 unsigned guardband_x = fd_calc_guardband(scissor->maxx - scissor->minx);
1004 unsigned guardband_y = fd_calc_guardband(scissor->maxy - scissor->miny);
1005
1006 OUT_PKT4(ring, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1007 OUT_RING(ring, A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_x) |
1008 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_y));
1009 }
1010
1011 if (dirty & FD_DIRTY_PROG) {
1012 fd6_emit_add_group(emit, prog->config_stateobj, FD6_GROUP_PROG_CONFIG, ENABLE_ALL);
1013 fd6_emit_add_group(emit, prog->stateobj, FD6_GROUP_PROG, ENABLE_DRAW);
1014 fd6_emit_add_group(emit, prog->binning_stateobj,
1015 FD6_GROUP_PROG_BINNING, CP_SET_DRAW_STATE__0_BINNING);
1016
1017 /* emit remaining streaming program state, ie. what depends on
1018 * other emit state, so cannot be pre-baked.
1019 */
1020 struct fd_ringbuffer *streaming = fd6_program_interp_state(emit);
1021
1022 fd6_emit_take_group(emit, streaming, FD6_GROUP_PROG_INTERP, ENABLE_DRAW);
1023 }
1024
1025 if (dirty & FD_DIRTY_RASTERIZER) {
1026 struct fd_ringbuffer *stateobj =
1027 fd6_rasterizer_state(ctx, emit->primitive_restart);
1028 fd6_emit_add_group(emit, stateobj,
1029 FD6_GROUP_RASTERIZER, ENABLE_ALL);
1030 }
1031
1032 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
1033 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
1034 emit->ctx->batch->submit, 5 * 4, FD_RINGBUFFER_STREAMING);
1035
1036 unsigned nr = pfb->nr_cbufs;
1037
1038 if (ctx->rasterizer->rasterizer_discard)
1039 nr = 0;
1040
1041 OUT_PKT4(ring, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1042 OUT_RING(ring, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1043 COND(fs->writes_smask && pfb->samples > 1,
1044 A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
1045 OUT_RING(ring, A6XX_RB_FS_OUTPUT_CNTL1_MRT(nr));
1046
1047 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL1, 1);
1048 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL1_MRT(nr));
1049
1050 fd6_emit_take_group(emit, ring, FD6_GROUP_PROG_FB_RAST, ENABLE_DRAW);
1051 }
1052
1053 fd6_emit_consts(emit, vs, PIPE_SHADER_VERTEX, FD6_GROUP_VS_CONST, ENABLE_ALL);
1054 fd6_emit_consts(emit, hs, PIPE_SHADER_TESS_CTRL, FD6_GROUP_HS_CONST, ENABLE_ALL);
1055 fd6_emit_consts(emit, ds, PIPE_SHADER_TESS_EVAL, FD6_GROUP_DS_CONST, ENABLE_ALL);
1056 fd6_emit_consts(emit, gs, PIPE_SHADER_GEOMETRY, FD6_GROUP_GS_CONST, ENABLE_ALL);
1057 fd6_emit_consts(emit, fs, PIPE_SHADER_FRAGMENT, FD6_GROUP_FS_CONST, ENABLE_DRAW);
1058
1059 if (emit->key.key.has_gs || emit->key.key.tessellation)
1060 fd6_emit_tess_const(emit);
1061
1062 /* if driver-params are needed, emit each time: */
1063 if (ir3_needs_vs_driver_params(vs)) {
1064 struct fd_ringbuffer *dpconstobj = fd_submit_new_ringbuffer(
1065 ctx->batch->submit, IR3_DP_VS_COUNT * 4, FD_RINGBUFFER_STREAMING);
1066 ir3_emit_vs_driver_params(vs, dpconstobj, ctx, emit->info);
1067 fd6_emit_take_group(emit, dpconstobj, FD6_GROUP_VS_DRIVER_PARAMS, ENABLE_ALL);
1068 } else {
1069 fd6_emit_take_group(emit, NULL, FD6_GROUP_VS_DRIVER_PARAMS, ENABLE_ALL);
1070 }
1071
1072 struct ir3_stream_output_info *info = &fd6_last_shader(prog)->shader->stream_output;
1073 if (info->num_outputs)
1074 fd6_emit_streamout(ring, emit, info);
1075
1076 if (dirty & FD_DIRTY_BLEND) {
1077 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
1078 uint32_t i;
1079
1080 for (i = 0; i < pfb->nr_cbufs; i++) {
1081 OUT_PKT4(ring, REG_A6XX_RB_MRT_CONTROL(i), 1);
1082 OUT_RING(ring, blend->rb_mrt[i].control);
1083
1084 OUT_PKT4(ring, REG_A6XX_RB_MRT_BLEND_CONTROL(i), 1);
1085 OUT_RING(ring, blend->rb_mrt[i].blend_control);
1086 }
1087
1088 OUT_PKT4(ring, REG_A6XX_RB_DITHER_CNTL, 1);
1089 OUT_RING(ring, blend->rb_dither_cntl);
1090
1091 OUT_PKT4(ring, REG_A6XX_SP_BLEND_CNTL, 1);
1092 OUT_RING(ring, blend->sp_blend_cntl);
1093 }
1094
1095 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK)) {
1096 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
1097
1098 OUT_PKT4(ring, REG_A6XX_RB_BLEND_CNTL, 1);
1099 OUT_RING(ring, blend->rb_blend_cntl |
1100 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(ctx->sample_mask));
1101 }
1102
1103 if (dirty & FD_DIRTY_BLEND_COLOR) {
1104 struct pipe_blend_color *bcolor = &ctx->blend_color;
1105
1106 OUT_PKT4(ring, REG_A6XX_RB_BLEND_RED_F32, 4);
1107 OUT_RING(ring, A6XX_RB_BLEND_RED_F32(bcolor->color[0]));
1108 OUT_RING(ring, A6XX_RB_BLEND_GREEN_F32(bcolor->color[1]));
1109 OUT_RING(ring, A6XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
1110 OUT_RING(ring, A6XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
1111 }
1112
1113 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_VERTEX, vs);
1114 if (hs) {
1115 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_TESS_CTRL, hs);
1116 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_TESS_EVAL, ds);
1117 }
1118 if (gs) {
1119 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_GEOMETRY, gs);
1120 }
1121 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_FRAGMENT, fs);
1122
1123 if (needs_border)
1124 emit_border_color(ctx, ring);
1125
1126 if (hs) {
1127 debug_assert(ir3_shader_nibo(hs) == 0);
1128 debug_assert(ir3_shader_nibo(ds) == 0);
1129 }
1130 if (gs) {
1131 debug_assert(ir3_shader_nibo(gs) == 0);
1132 }
1133
1134 #define DIRTY_IBO (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE | \
1135 FD_DIRTY_SHADER_PROG)
1136 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & DIRTY_IBO) {
1137 struct fd_ringbuffer *state =
1138 fd6_build_ibo_state(ctx, fs, PIPE_SHADER_FRAGMENT);
1139 struct fd_ringbuffer *obj = fd_submit_new_ringbuffer(
1140 ctx->batch->submit, 0x100, FD_RINGBUFFER_STREAMING);
1141
1142 OUT_PKT7(obj, CP_LOAD_STATE6, 3);
1143 OUT_RING(obj, CP_LOAD_STATE6_0_DST_OFF(0) |
1144 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1145 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1146 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_IBO) |
1147 CP_LOAD_STATE6_0_NUM_UNIT(ir3_shader_nibo(fs)));
1148 OUT_RB(obj, state);
1149
1150 OUT_PKT4(obj, REG_A6XX_SP_IBO_LO, 2);
1151 OUT_RB(obj, state);
1152
1153 /* TODO if we used CP_SET_DRAW_STATE for compute shaders, we could
1154 * de-duplicate this from program->config_stateobj
1155 */
1156 OUT_PKT4(obj, REG_A6XX_SP_IBO_COUNT, 1);
1157 OUT_RING(obj, ir3_shader_nibo(fs));
1158
1159 ir3_emit_ssbo_sizes(ctx->screen, fs, obj,
1160 &ctx->shaderbuf[PIPE_SHADER_FRAGMENT]);
1161 ir3_emit_image_dims(ctx->screen, fs, obj,
1162 &ctx->shaderimg[PIPE_SHADER_FRAGMENT]);
1163
1164 fd6_emit_take_group(emit, obj, FD6_GROUP_IBO, ENABLE_DRAW);
1165 fd_ringbuffer_del(state);
1166 }
1167
1168 if (emit->num_groups > 0) {
1169 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3 * emit->num_groups);
1170 for (unsigned i = 0; i < emit->num_groups; i++) {
1171 struct fd6_state_group *g = &emit->groups[i];
1172 unsigned n = g->stateobj ?
1173 fd_ringbuffer_size(g->stateobj) / 4 : 0;
1174
1175 debug_assert((g->enable_mask & ~ENABLE_ALL) == 0);
1176
1177 if (n == 0) {
1178 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1179 CP_SET_DRAW_STATE__0_DISABLE |
1180 g->enable_mask |
1181 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
1182 OUT_RING(ring, 0x00000000);
1183 OUT_RING(ring, 0x00000000);
1184 } else {
1185 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(n) |
1186 g->enable_mask |
1187 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
1188 OUT_RB(ring, g->stateobj);
1189 }
1190
1191 if (g->stateobj)
1192 fd_ringbuffer_del(g->stateobj);
1193 }
1194 emit->num_groups = 0;
1195 }
1196 }
1197
1198 void
1199 fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
1200 struct ir3_shader_variant *cp)
1201 {
1202 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
1203
1204 if (dirty & (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
1205 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) {
1206 struct fd_texture_stateobj *tex = &ctx->tex[PIPE_SHADER_COMPUTE];
1207 unsigned bcolor_offset = fd6_border_color_offset(ctx, PIPE_SHADER_COMPUTE, tex);
1208
1209 bool needs_border = fd6_emit_textures(ctx->pipe, ring, PIPE_SHADER_COMPUTE, tex,
1210 bcolor_offset, cp, ctx);
1211
1212 if (needs_border)
1213 emit_border_color(ctx, ring);
1214
1215 OUT_PKT4(ring, REG_A6XX_SP_VS_TEX_COUNT, 1);
1216 OUT_RING(ring, 0);
1217
1218 OUT_PKT4(ring, REG_A6XX_SP_HS_TEX_COUNT, 1);
1219 OUT_RING(ring, 0);
1220
1221 OUT_PKT4(ring, REG_A6XX_SP_DS_TEX_COUNT, 1);
1222 OUT_RING(ring, 0);
1223
1224 OUT_PKT4(ring, REG_A6XX_SP_GS_TEX_COUNT, 1);
1225 OUT_RING(ring, 0);
1226
1227 OUT_PKT4(ring, REG_A6XX_SP_FS_TEX_COUNT, 1);
1228 OUT_RING(ring, 0);
1229 }
1230
1231 if (dirty & (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)) {
1232 struct fd_ringbuffer *state =
1233 fd6_build_ibo_state(ctx, cp, PIPE_SHADER_COMPUTE);
1234
1235 OUT_PKT7(ring, CP_LOAD_STATE6_FRAG, 3);
1236 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
1237 CP_LOAD_STATE6_0_STATE_TYPE(ST6_IBO) |
1238 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1239 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_CS_SHADER) |
1240 CP_LOAD_STATE6_0_NUM_UNIT(ir3_shader_nibo(cp)));
1241 OUT_RB(ring, state);
1242
1243 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_LO, 2);
1244 OUT_RB(ring, state);
1245
1246 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_COUNT, 1);
1247 OUT_RING(ring, ir3_shader_nibo(cp));
1248
1249 fd_ringbuffer_del(state);
1250 }
1251 }
1252
1253
1254 /* emit setup at begin of new cmdstream buffer (don't rely on previous
1255 * state, there could have been a context switch between ioctls):
1256 */
1257 void
1258 fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
1259 {
1260 //struct fd_context *ctx = batch->ctx;
1261
1262 fd6_cache_inv(batch, ring);
1263
1264 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1265 OUT_RING(ring, 0xfffff);
1266
1267 OUT_WFI5(ring);
1268
1269 WRITE(REG_A6XX_RB_UNKNOWN_8E04, 0x0);
1270 WRITE(REG_A6XX_SP_UNKNOWN_AE04, 0x8);
1271 WRITE(REG_A6XX_SP_UNKNOWN_AE00, 0);
1272 WRITE(REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
1273 WRITE(REG_A6XX_SP_UNKNOWN_B605, 0x44);
1274 WRITE(REG_A6XX_SP_UNKNOWN_B600, 0x100000);
1275 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
1276 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
1277
1278 WRITE(REG_A6XX_VPC_UNKNOWN_9600, 0);
1279 WRITE(REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
1280 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE04, 0x80000);
1281 WRITE(REG_A6XX_SP_UNKNOWN_AE03, 0x1430);
1282 WRITE(REG_A6XX_SP_IBO_COUNT, 0);
1283 WRITE(REG_A6XX_SP_UNKNOWN_B182, 0);
1284 WRITE(REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
1285 WRITE(REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
1286 WRITE(REG_A6XX_UCHE_CLIENT_PF, 4);
1287 WRITE(REG_A6XX_RB_UNKNOWN_8E01, 0x1);
1288 WRITE(REG_A6XX_SP_UNKNOWN_AB00, 0x5);
1289 WRITE(REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
1290 WRITE(REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
1291 WRITE(REG_A6XX_PC_MODE_CNTL, 0x1f);
1292
1293 OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
1294 OUT_RING(ring, 0);
1295
1296 WRITE(REG_A6XX_GRAS_UNKNOWN_8101, 0);
1297 WRITE(REG_A6XX_GRAS_SAMPLE_CNTL, 0);
1298 WRITE(REG_A6XX_GRAS_UNKNOWN_8110, 0x2);
1299
1300 WRITE(REG_A6XX_RB_UNKNOWN_8818, 0);
1301 WRITE(REG_A6XX_RB_UNKNOWN_8819, 0);
1302 WRITE(REG_A6XX_RB_UNKNOWN_881A, 0);
1303 WRITE(REG_A6XX_RB_UNKNOWN_881B, 0);
1304 WRITE(REG_A6XX_RB_UNKNOWN_881C, 0);
1305 WRITE(REG_A6XX_RB_UNKNOWN_881D, 0);
1306 WRITE(REG_A6XX_RB_UNKNOWN_881E, 0);
1307 WRITE(REG_A6XX_RB_UNKNOWN_88F0, 0);
1308
1309 WRITE(REG_A6XX_VPC_UNKNOWN_9236,
1310 A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(0));
1311 WRITE(REG_A6XX_VPC_UNKNOWN_9300, 0);
1312
1313 WRITE(REG_A6XX_VPC_SO_OVERRIDE, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
1314
1315 WRITE(REG_A6XX_PC_UNKNOWN_9806, 0);
1316 WRITE(REG_A6XX_PC_UNKNOWN_9990, 0);
1317 WRITE(REG_A6XX_PC_UNKNOWN_9980, 0);
1318
1319 WRITE(REG_A6XX_PC_UNKNOWN_9B07, 0);
1320
1321 WRITE(REG_A6XX_SP_UNKNOWN_A81B, 0);
1322
1323 WRITE(REG_A6XX_SP_UNKNOWN_B183, 0);
1324
1325 WRITE(REG_A6XX_GRAS_UNKNOWN_8099, 0);
1326 WRITE(REG_A6XX_GRAS_UNKNOWN_809B, 0);
1327 WRITE(REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1328 WRITE(REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1329 WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
1330 WRITE(REG_A6XX_VPC_UNKNOWN_9211, 0);
1331 WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
1332 WRITE(REG_A6XX_PC_UNKNOWN_9981, 0x3);
1333 WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
1334 WRITE(REG_A6XX_VPC_UNKNOWN_9108, 0x3);
1335 WRITE(REG_A6XX_SP_TP_UNKNOWN_B304, 0);
1336 /* NOTE blob seems to (mostly?) use 0xb2 for SP_TP_UNKNOWN_B309
1337 * but this seems to kill texture gather offsets.
1338 */
1339 WRITE(REG_A6XX_SP_TP_UNKNOWN_B309, 0xa2);
1340 WRITE(REG_A6XX_RB_UNKNOWN_8804, 0);
1341 WRITE(REG_A6XX_GRAS_UNKNOWN_80A4, 0);
1342 WRITE(REG_A6XX_GRAS_UNKNOWN_80A5, 0);
1343 WRITE(REG_A6XX_GRAS_UNKNOWN_80A6, 0);
1344 WRITE(REG_A6XX_RB_UNKNOWN_8805, 0);
1345 WRITE(REG_A6XX_RB_UNKNOWN_8806, 0);
1346 WRITE(REG_A6XX_RB_UNKNOWN_8878, 0);
1347 WRITE(REG_A6XX_RB_UNKNOWN_8879, 0);
1348 WRITE(REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1349
1350 emit_marker6(ring, 7);
1351
1352 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
1353 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
1354
1355 WRITE(REG_A6XX_VFD_UNKNOWN_A008, 0);
1356
1357 OUT_PKT4(ring, REG_A6XX_PC_MODE_CNTL, 1);
1358 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
1359
1360 /* we don't use this yet.. probably best to disable.. */
1361 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1362 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1363 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1364 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1365 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1366 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1367
1368 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1369 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
1370
1371 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1372 OUT_RING(ring, 0x00000000);
1373
1374 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
1375 OUT_RING(ring, 0x00000000);
1376 }
1377
1378 static void
1379 fd6_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
1380 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
1381 unsigned sizedwords)
1382 {
1383 struct fd_bo *src_bo = fd_resource(src)->bo;
1384 struct fd_bo *dst_bo = fd_resource(dst)->bo;
1385 unsigned i;
1386
1387 for (i = 0; i < sizedwords; i++) {
1388 OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
1389 OUT_RING(ring, 0x00000000);
1390 OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
1391 OUT_RELOC (ring, src_bo, src_off, 0, 0);
1392
1393 dst_off += 4;
1394 src_off += 4;
1395 }
1396 }
1397
1398 /* this is *almost* the same as fd6_cache_flush().. which I guess
1399 * could be re-worked to be something a bit more generic w/ param
1400 * indicating what needs to be flushed.. although that would mean
1401 * figuring out which events trigger what state to flush..
1402 */
1403 static void
1404 fd6_framebuffer_barrier(struct fd_context *ctx)
1405 {
1406 struct fd6_context *fd6_ctx = fd6_context(ctx);
1407 struct fd_batch *batch = ctx->batch;
1408 struct fd_ringbuffer *ring = batch->draw;
1409 unsigned seqno;
1410
1411 seqno = fd6_event_write(batch, ring, CACHE_FLUSH_AND_INV_EVENT, true);
1412
1413 OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);
1414 OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
1415 CP_WAIT_REG_MEM_0_POLL_MEMORY);
1416 OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
1417 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(seqno));
1418 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(~0));
1419 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
1420
1421 fd6_event_write(batch, ring, UNK_1D, true);
1422 fd6_event_write(batch, ring, UNK_1C, true);
1423
1424 seqno = fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
1425
1426 fd6_event_write(batch, ring, 0x31, false);
1427
1428 OUT_PKT7(ring, CP_WAIT_MEM_GTE, 4);
1429 OUT_RING(ring, CP_WAIT_MEM_GTE_0_RESERVED(0));
1430 OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
1431 OUT_RING(ring, CP_WAIT_MEM_GTE_3_REF(seqno));
1432 }
1433
1434 void
1435 fd6_emit_init_screen(struct pipe_screen *pscreen)
1436 {
1437 struct fd_screen *screen = fd_screen(pscreen);
1438 screen->emit_const = fd6_emit_const;
1439 screen->emit_const_bo = fd6_emit_const_bo;
1440 screen->emit_ib = fd6_emit_ib;
1441 screen->mem_to_mem = fd6_mem_to_mem;
1442 }
1443
1444 void
1445 fd6_emit_init(struct pipe_context *pctx)
1446 {
1447 struct fd_context *ctx = fd_context(pctx);
1448 ctx->framebuffer_barrier = fd6_framebuffer_barrier;
1449 }