src/gallium/drivers/freedreno/a6xx/fd6_emit.h

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #ifndef FD6_EMIT_H
  29 #define FD6_EMIT_H
  30
  31 #include "pipe/p_context.h"
  32
  33 #include "freedreno_context.h"
  34 #include "fd6_context.h"
  35 #include "fd6_format.h"
  36 #include "fd6_program.h"
  37 #include "ir3_gallium.h"
  38
  39 struct fd_ringbuffer;
  40
  41 /* To collect all the state objects to emit in a single CP_SET_DRAW_STATE
  42  * packet, the emit tracks a collection of however many state_group's that
  43  * need to be emit'd.
  44  */
  45 enum fd6_state_id {
  46         FD6_GROUP_PROG_CONFIG,
  47         FD6_GROUP_PROG,
  48         FD6_GROUP_PROG_BINNING,
  49         FD6_GROUP_LRZ,
  50         FD6_GROUP_LRZ_BINNING,
  51         FD6_GROUP_VBO,
  52         FD6_GROUP_VS_CONST,
  53         FD6_GROUP_HS_CONST,
  54         FD6_GROUP_DS_CONST,
  55         FD6_GROUP_GS_CONST,
  56         FD6_GROUP_FS_CONST,
  57         FD6_GROUP_VS_DRIVER_PARAMS,
  58         FD6_GROUP_PRIMITIVE_PARAMS,
  59         FD6_GROUP_VS_TEX,
  60         FD6_GROUP_HS_TEX,
  61         FD6_GROUP_DS_TEX,
  62         FD6_GROUP_GS_TEX,
  63         FD6_GROUP_FS_TEX,
  64         FD6_GROUP_IBO,
  65         FD6_GROUP_RASTERIZER,
  66         FD6_GROUP_ZSA,
  67 };
  68
  69 struct fd6_state_group {
  70         struct fd_ringbuffer *stateobj;
  71         enum fd6_state_id group_id;
  72         /* enable_mask controls which states the stateobj is evaluated in,
  73          * b0 is binning pass b1 and/or b2 is draw pass
  74          */
  75         uint8_t enable_mask;
  76 };
  77
  78 /* grouped together emit-state for prog/vertex/state emit: */
  79 struct fd6_emit {
  80         struct fd_context *ctx;
  81         const struct fd_vertex_state *vtx;
  82         const struct pipe_draw_info *info;
  83         struct ir3_cache_key key;
  84         enum fd_dirty_3d_state dirty;
  85
  86         uint32_t sprite_coord_enable;  /* bitmask */
  87         bool sprite_coord_mode;
  88         bool rasterflat;
  89         bool no_decode_srgb;
  90
  91         /* in binning pass, we don't have real frag shader, so we
  92          * don't know if real draw disqualifies lrz write.  So just
  93          * figure that out up-front and stash it in the emit.
  94          */
  95         bool no_lrz_write;
  96
  97         /* cached to avoid repeated lookups: */
  98         const struct fd6_program_state *prog;
  99
 100         struct ir3_shader_variant *bs;
 101         struct ir3_shader_variant *vs;
 102         struct ir3_shader_variant *hs;
 103         struct ir3_shader_variant *ds;
 104         struct ir3_shader_variant *gs;
 105         struct ir3_shader_variant *fs;
 106
 107         unsigned streamout_mask;
 108
 109         struct fd6_state_group groups[32];
 110         unsigned num_groups;
 111 };
 112
 113 static inline const struct fd6_program_state *
 114 fd6_emit_get_prog(struct fd6_emit *emit)
 115 {
 116         if (!emit->prog) {
 117                 struct fd6_context *fd6_ctx = fd6_context(emit->ctx);
 118                 struct ir3_program_state *s =
 119                                 ir3_cache_lookup(fd6_ctx->shader_cache, &emit->key, &emit->ctx->debug);
 120                 emit->prog = fd6_program_state(s);
 121         }
 122         return emit->prog;
 123 }
 124
 125 static inline void
 126 fd6_emit_take_group(struct fd6_emit *emit, struct fd_ringbuffer *stateobj,
 127                 enum fd6_state_id group_id, unsigned enable_mask)
 128 {
 129         debug_assert(emit->num_groups < ARRAY_SIZE(emit->groups));
 130         struct fd6_state_group *g = &emit->groups[emit->num_groups++];
 131         g->stateobj = stateobj;
 132         g->group_id = group_id;
 133         g->enable_mask = enable_mask;
 134 }
 135
 136 static inline void
 137 fd6_emit_add_group(struct fd6_emit *emit, struct fd_ringbuffer *stateobj,
 138                 enum fd6_state_id group_id, unsigned enable_mask)
 139 {
 140         fd6_emit_take_group(emit, fd_ringbuffer_ref(stateobj), group_id, enable_mask);
 141 }
 142
 143 static inline unsigned
 144 fd6_event_write(struct fd_batch *batch, struct fd_ringbuffer *ring,
 145                 enum vgt_event_type evt, bool timestamp)
 146 {
 147         unsigned seqno = 0;
 148
 149         fd_reset_wfi(batch);
 150
 151         OUT_PKT7(ring, CP_EVENT_WRITE, timestamp ? 4 : 1);
 152         OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(evt));
 153         if (timestamp) {
 154                 struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
 155                 seqno = ++fd6_ctx->seqno;
 156                 OUT_RELOCW(ring, control_ptr(fd6_ctx, seqno));  /* ADDR_LO/HI */
 157                 OUT_RING(ring, seqno);
 158         }
 159
 160         return seqno;
 161 }
 162
 163 static inline void
 164 fd6_cache_inv(struct fd_batch *batch, struct fd_ringbuffer *ring)
 165 {
 166         fd6_event_write(batch, ring, CACHE_INVALIDATE, false);
 167 }
 168
 169 static inline void
 170 fd6_cache_flush(struct fd_batch *batch, struct fd_ringbuffer *ring)
 171 {
 172         struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
 173         unsigned seqno;
 174
 175         seqno = fd6_event_write(batch, ring, CACHE_FLUSH_AND_INV_EVENT, true);
 176
 177         OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);
 178         OUT_RING(ring, 0x00000013);
 179         OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
 180         OUT_RING(ring, seqno);
 181         OUT_RING(ring, 0xffffffff);
 182         OUT_RING(ring, 0x00000010);
 183
 184         seqno = fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
 185
 186         OUT_PKT7(ring, CP_UNK_A6XX_14, 4);
 187         OUT_RING(ring, 0x00000000);
 188         OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
 189         OUT_RING(ring, seqno);
 190 }
 191
 192 static inline void
 193 fd6_emit_blit(struct fd_batch *batch, struct fd_ringbuffer *ring)
 194 {
 195         emit_marker6(ring, 7);
 196         fd6_event_write(batch, ring, BLIT, false);
 197         emit_marker6(ring, 7);
 198 }
 199
 200 static inline void
 201 fd6_emit_lrz_flush(struct fd_ringbuffer *ring)
 202 {
 203         OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 204         OUT_RING(ring, LRZ_FLUSH);
 205 }
 206
 207 static inline uint32_t
 208 fd6_stage2opcode(gl_shader_stage type)
 209 {
 210         switch (type) {
 211         case MESA_SHADER_VERTEX:
 212         case MESA_SHADER_TESS_CTRL:
 213         case MESA_SHADER_TESS_EVAL:
 214         case MESA_SHADER_GEOMETRY:
 215                 return CP_LOAD_STATE6_GEOM;
 216         case MESA_SHADER_FRAGMENT:
 217         case MESA_SHADER_COMPUTE:
 218         case MESA_SHADER_KERNEL:
 219                 return CP_LOAD_STATE6_FRAG;
 220         default:
 221                 unreachable("bad shader type");
 222         }
 223 }
 224
 225 static inline enum a6xx_state_block
 226 fd6_stage2shadersb(gl_shader_stage type)
 227 {
 228         switch (type) {
 229         case MESA_SHADER_VERTEX:
 230                 return SB6_VS_SHADER;
 231         case MESA_SHADER_TESS_CTRL:
 232                 return SB6_HS_SHADER;
 233         case MESA_SHADER_TESS_EVAL:
 234                 return SB6_DS_SHADER;
 235         case MESA_SHADER_GEOMETRY:
 236                 return SB6_GS_SHADER;
 237         case MESA_SHADER_FRAGMENT:
 238                 return SB6_FS_SHADER;
 239         case MESA_SHADER_COMPUTE:
 240         case MESA_SHADER_KERNEL:
 241                 return SB6_CS_SHADER;
 242         default:
 243                 unreachable("bad shader type");
 244                 return ~0;
 245         }
 246 }
 247
 248 static inline enum a6xx_tess_spacing
 249 fd6_gl2spacing(enum gl_tess_spacing spacing)
 250 {
 251         switch (spacing) {
 252         case TESS_SPACING_EQUAL:
 253                 return TESS_EQUAL;
 254         case TESS_SPACING_FRACTIONAL_ODD:
 255                 return TESS_FRACTIONAL_ODD;
 256         case TESS_SPACING_FRACTIONAL_EVEN:
 257                 return TESS_FRACTIONAL_EVEN;
 258         case TESS_SPACING_UNSPECIFIED:
 259         default:
 260                 unreachable("spacing must be specified");
 261         }
 262 }
 263
 264 bool fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
 265                 enum pipe_shader_type type, struct fd_texture_stateobj *tex,
 266                 unsigned bcolor_offset,
 267                 const struct ir3_shader_variant *v, struct fd_context *ctx);
 268
 269 void fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit);
 270
 271 void fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 272                 struct ir3_shader_variant *cp);
 273
 274 void fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring);
 275
 276 void fd6_emit_init_screen(struct pipe_screen *pscreen);
 277 void fd6_emit_init(struct pipe_context *pctx);
 278
 279 static inline void
 280 fd6_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
 281 {
 282         emit_marker6(ring, 6);
 283         __OUT_IB5(ring, target);
 284         emit_marker6(ring, 6);
 285 }
 286
 287 #define WRITE(reg, val) do {                                    \
 288                 OUT_PKT4(ring, reg, 1);                                 \
 289                 OUT_RING(ring, val);                                    \
 290         } while (0)
 291
 292
 293 #endif /* FD6_EMIT_H */